JPH02244497A - Josephson latching circuit - Google Patents

Abstract

PURPOSE:To use a latching circuit for a unipolar AC driving system by inputting a signal brought to product operation of a true signal and a latch enable signal to one of two input lines, and inputting a signal brought to product operation of a complementary signal and a latch enable signal to the other. CONSTITUTION:A data holding loop is constituted of a single or plural Josephson junctions 3 and superconductive inductances 4-6. A true signal input line 1 and a complementary signal input line 2 are coupled magnetically to a part of the data holding loop, and sense circuits 7, 71 are connected directly to a part of the data holding loop. Also, output circuits 8-13 and 19 read information held in the data holding loop by the sense circuits 7, 71 and generates a true signal and a complementary signal. Subsequently, to the true signal input line 1, a signal brought to product operation of the true signal and a latch enable signal is inputted, and to the complementary signal input line 2, a signal brought to product operation of the complementary signal and the latch enable signal is inputted. In this case, a latching circuit can be used at the time of a unipolar AC driving system, and no timing sequence is required for its operation.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a latch circuit using a Josephson junction, more specifically, a dual rail circuit that inputs and outputs a true signal and a complementary signal in the circuit. This invention relates to a latch circuit that temporarily stores information in a logic circuit of the system.

(Prior Art) Once switched to a voltage state, a Josephson junction element performs a latching operation in which the voltage state is maintained unless the power supply current is turned off. For this reason, in logic circuits using Josephson junctions, an AC power supply system in which the power supply current is reset to 0 once is common. In this power supply system, a latch circuit that holds the calculated results while the power supply current is 0 is essential. On the other hand, it is more difficult to construct an inverter in logic circuits using Josephson junctions than in semiconductors, and a dual rail system is generally adopted. The dual rail method is a circuit method in which the complementary signal of the input signal to the logic circuit is input at the same time, and the complementary signal of the output signal is also generated simultaneously in the logic circuit, and it uses an inverter that requires a timing signal. Since this is not necessary, it is possible to increase the speed of the circuit. Therefore, a dual-rail type latch circuit is required in which both the true signal and the complementary signal are outputted from the above-mentioned latch circuit.

In the past, several latch circuits have been proposed and studied, and here, a conventional example shown in FIG. 4, which is superior in terms of the area occupied by the circuit, will be described as an example. The operation of this conventional latch circuit is described in the literature Journal of Applied Physics.
Physics) vol, 59(9), pp319
6-3201, so I will only briefly describe it here. FIG. 4 shows an equivalent circuit of a conventional example, in which 40 is a data input line, 41 is a latch enable signal line, 42, 43, 44, 47, 48 are Josephson junctions, 45 is an inductance, and 46 is a sense Signal input line, 4
9, 400, 401 are resistors, 402 is an auxiliary signal output line,
403 is a true signal output line, and Josephson junction 42
and an inductance 45 constitute a data holding loop. When writing data "1", a data signal and a latch enable signal are input to the data holding loop through a data input line and a latch enable signal line. This causes Josephson junction 42 to switch and store data in the data retention loop as a persistent current. The latch enable signal is used to notify the timing of writing to the latch circuit and to reset the data in the data holding loop. Since the latch circuit is used in bipolar AC driving, a latch enable signal having a polarity different from the input signal input to the data holding loop during the previous machine cycle is input to the next stage. Therefore, the persistent current flowing in the data retention loop and the latch enable signal are superimposed at the Josephson junction 42, and the Josephson junction 42 switches to reset the persistent current. Reading is performed at the rise of the sense current flowing through the sense signal input line 46. When a persistent current flows in the data retention loop, an output appears on the true signal output line 403 from the Josephson junctions 43 and 44 as the sense gate current rises. If no persistent current flows in the data retention loop, the critical current value of the Josephson junction 47 is exceeded at the final stage when the sense gate current rises, and the Josephson junction 47 switches, followed by the Josephson junction 48. Auxiliary signal output line 402
The output appears. The Josephson latch circuit can be realized in the manner described above.

(Problems to be Solved by the Invention) However, the above-described latch circuit has the following problems. That is, when resetting data, a gate current with a polarity different from that of the previous machine cycle is required. In other words, it can only be used in bipolar AC driven systems. Needless to say, Josephson integrated circuits require not only logic circuits but also memory circuits. Since most Josephson memory circuits carry information on the polarity of current or operate by superimposing currents, it is difficult to operate them with bipolar AC drive. Therefore, other driving methods include DC drive or unipolar AC drive, but considering that the logic circuit must also be driven, it is considered difficult to operate with DC drive. Therefore, a unipolar AC drive system was thought to be optimal, but in that case, the conventional launch circuit cannot be used as described above.

(Means for Solving the Problems) According to the present invention, a data retention loop consisting of a single or multiple Josephson junctions and a superconducting inductance;
a true signal input line and an auxiliary signal input line each magnetically coupled to a portion of the data retention loop; a sense circuit directly connected to the portion of the data retention loop; and a sense circuit connected to the data retention loop by the sense circuit. It consists of an output circuit that reads the held information and generates a true signal and a complementary signal.One of the two input lines mentioned above receives a signal obtained by multiplying the true signal and the latch enable signal, and the other A Josephson latch circuit is obtained in which a signal obtained by multiplying a complementary signal and a latch enable signal is input.

(Operation) In the data retention loop of the present invention, data is written by a switch of the Josephson junction, which is composed of a Josephson junction and an inductance.

When the data is "1", the true signal is input so as to exceed the critical current value of the Josephson junction, and the persistent current is written. When the data is "0", the complementary signal is superimposed on the persistent current and the Josephson junction The persistent current is reset by inputting the signal so that it exceeds the critical current value of The data held in the data holding loop is read out by a sense gate circuit connected directly to the data holding loop, and a true signal and a complementary signal are output.

(Example) Figures 1 to 3 are diagrams for explaining the present invention in detail.
FIG. 1 shows an equal number of circuits of the embodiment, in which 1 is a true signal input line, 2 is an auxiliary signal input line, 3.7, 8, 19 .
71 is a Josephson junction, 4 and 5.6 are inductances, 9 is a gate current line, 10.11 is an output resistance, 12 is a true signal output line, 13 is a supplementary signal output line, 14 is a latch enable signal line, 15. 16 is a product calculation circuit, 17 is a true signal line, and 18 is a complementary signal line. Assuming that the phase difference of the order parameters of the Josephson junction 3 is θ, the current-phase characteristics of the current I8 input from the true signal input line 1 are as shown in FIG. 21 to 2 in Figure 2
The numbers up to 6 indicate operating points. This current.

The phase characteristics are determined by the critical current value of Josephson junction 3 and the inductance value of inductance 4, 5.6,
It can be set to have the characteristics shown in the figure.

In addition, Fig. 3 shows the gate current I- of the Josephson logic circuit.
An example of a waveform schematically shows the case of unipolar AC drive, where 31 is an operating area, 32 is a data writing area, and 33 is a waveform example.
34 represents a data holding area, 34 represents a machine cycle, and 35 represents a data read area.

The results calculated in the operating region 31 shown in FIG.
Alternatively, it is input to 16. The latch enable signal is input to the product calculation circuits 15 and 16 and enters the data write area 32, and data is input to the data holding loop via the true signal input line 1 or the auxiliary signal input line 2.

If the calculation result is "1", a true signal is input, a current is induced in the data holding loop, and the Josephson junction 3 is switched. That is, in FIG. 2, the operating point passes through 21 and moves to 22. After the gate current falls, the operating point is 23
The data is held during the data holding area 33.

On the other hand, if the calculation result is "0", the complementary signal is input.

The current induced in the data retention loop by the complementary signal is in the opposite direction to that of the true signal at Josephson junction 3, so
The operating point moves from 23 through 24.25 to 26, resetting the persistent current in the data retention loop. Next, at the time of reading, a gate current is applied to the Josephson junctions 7 and 71 through the gate current line between the data read region 35. If a persistent current is flowing in the data retention loop, the Josephson junction 7.71 switches, the data is read out, and a signal appears on the true signal output line. At this time, the gate current is also shunted to the resistor 10, but the resistors 10 and 11 can be appropriately selected so that this shunted current does not switch the Josephson junction 19. When no persistent current flows in the data retention loop, the Josephson junction 8 switches at the final stage of the rise of the gate current, and then the Josephson junction 19 switches and an output signal appears on the auxiliary signal output line. At this time, since no gate current flows through the Josephson junctions 7 and 71 in the operating region, even if the state of the data retention loop changes, it does not affect the output.

As described above, a Josephson latch circuit can be realized using this circuit. This circuit is a latch circuit using a dual rail system, and is a latch circuit used in a unipolar AC drive system. As outputs, a true signal and a complementary signal are generated.

(Effects of the Invention) The launch circuit of the present invention can be used in a unipolar AC drive system and does not require a special timing sequence for its operation. Furthermore, a single Josephson junction is used for writing data, so the area occupied by the circuit can be reduced. Further, by directly connecting the sense gate circuit to the data holding loop, the circuit can be further miniaturized.

[Brief explanation of drawings]

1, 2, and 3 are diagrams for explaining the present invention in detail. FIG. 1 is an equivalent circuit diagram of an embodiment, FIG. 2 is a current one-phase characteristic diagram of a data retention loop, and FIG. Figure 3 is a gate current waveform diagram of the unipolar AC drive system. FIG. 4 is an equivalent circuit diagram of a conventional example. In each figure, 1... true signal input line, 2..., auxiliary signal input line, 3
．． 7, 8, 19, 71... Josephson junction, 4, 5
．． 6... Inductance, 9... Gate current line,
10.11... Output resistance, 12... True signal output line, 13... Complementary signal output line, 14... Latch enable signal line, 15.16... Product calculation circuit, 17...
True signal line, 18... Auxiliary signal line, 21, 22, 23, 2
4, 25.26... Operating point, 31... Operating area, 3
2... Data write area, 33... Data holding area, 34... Machine cycle, 35... Data read area, 40... Data input line, 41... Latch enable signal line, 42 ,43,44,47.48...
・Josephson junction, 45...Inductance, 46
...Sense signal input line, 49.400,401...
Resistor, 402... supplementary signal output line, 403... true signal output line.

Claims (1)

[Claims] a data retention loop consisting of a single or multiple Josephson junctions and a superconducting inductance; a true signal input line and an auxiliary signal input line each magnetically coupled to a portion of the data retention loop; and one of the data retention loops. It consists of a sense circuit directly connected to the data holding loop, and an output circuit that reads the information held in the data holding loop by the sense circuit and generates a true signal and a complementary signal. A Josephson latch circuit is characterized in that a signal obtained by multiplying a true signal and a latch enable signal is input, and a signal obtained by multiplying a complementary signal and a latch enable signal is inputted.