JPH012416A - superconducting logic gate circuit - Google Patents
superconducting logic gate circuitInfo
- Publication number
- JPH012416A JPH012416A JP62-158034A JP15803487A JPH012416A JP H012416 A JPH012416 A JP H012416A JP 15803487 A JP15803487 A JP 15803487A JP H012416 A JPH012416 A JP H012416A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- potential
- logic gate
- gate circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 241000238366 Cephalopoda Species 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は超伝導ジョセフソン素子を利用した超電導論
理ゲート回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a superconducting logic gate circuit using a superconducting Josephson element.
第３図は電子通信学会・超伝導集積回路に示された従来
の量子干渉計を用いた論理ゲート回路図である。FIG. 3 is a logic gate circuit diagram using a conventional quantum interferometer shown in the IEICE/Superconducting Integrated Circuits.
量子干渉計を用いたゲートの基本は第３因に示すような
、２個のインダクタンスＬＬ、Ｌ２、及び２個の接合Ｊ
１． Ｊ２をループ内に含み、外部制御線とループとを
結合させた構造のものである。このゲートの基本動作は
つぎのとおりとなる。図のようにバイアス信号Ｉｎを印
加すると、バイアス電流はジョセフソン接合Ｊｌ側とＪ
２側とに分かれて流れ、それぞれ
となる。更に制御信号が与えられると、相互インダクタ
ンス’ Ｃ’ｒＬｌ＋ ７は結合係数）、Ｍｚ（＝７Ｌ
２）を通じて、干渉計ループに周回電流Ｉｃ１ｒ （；
ｒＩｃ）が流れる。その結果、ジョセフソシ接合Ｊ１．
Ｊ２に流れる正味の電流は、
Ｌｌ
１２ ＝ Ｉｌ２− Ｉｃ１ｒ ＝−Ｌ１＋Ｌ２Ｉａ
−１−ｒｆｃとなる。もし、Ｉｌが接合Ｊ１の臨界電流
ＩＪｔより大きくなるようなＩｎとＩＣが与えられると
、ジョセフソン接合合５１は電圧状態にスイッチし、今
までＩｌ側に流れていた電流ＩｌをＪ２側に押しやるよ
うに作用する。このとき、接合Ｊ２側に押しやられた電
流と、もともとＪ２側に流れていた電流との和がＩＪ２
よりも大きくなると、接合Ｊ２も電圧状態に転移し、結
局干渉針内の二つの接合が共に電圧状態となって、ノー
ドＡ−Ｂ間に電圧が現れる。The basics of a gate using a quantum interferometer are two inductances LL, L2, and two junctions J, as shown in the third factor.
1. It has a structure in which J2 is included in the loop and the external control line and the loop are coupled. The basic operation of this gate is as follows. When the bias signal In is applied as shown in the figure, the bias current flows between the Josephson junction Jl side and J
It separates into two sides and flows, becoming each side. Furthermore, when a control signal is given, the mutual inductance 'C'rLl+ 7 is the coupling coefficient), Mz (=7L
2), the circulating current Ic1r (;
rIc) flows. As a result, Joseph Soci junction J1.
The net current flowing through J2 is Ll 12 = Il2- Ic1r = -L1+L2Ia
-1-rfc. If In and IC are applied such that Il becomes larger than the critical current IJt of junction J1, the Josephson junction 51 switches to a voltage state and pushes the current Il that was previously flowing to Il side to J2 side. It works like this. At this time, the sum of the current pushed to the junction J2 side and the current originally flowing to the J2 side is IJ2
, the junction J2 also transitions to a voltage state, and eventually both junctions in the interference needle become voltage states, and a voltage appears between nodes A and B.
従来の論理ゲートは以上のように構成されていたので、
量子干渉針（ＳＱＵＩＤ）と呼ばれる閉ループを形成し
なければならず、相互イ〉ダクタンスの結合係数を適切
な値に選ぶことが必要であり、一つの論理ゲートとして
は複雑であるという問題点があった。Conventional logic gates were configured as described above, so
It is necessary to form a closed loop called a quantum interference needle (SQUID), and it is necessary to select an appropriate value for the coupling coefficient of mutual inductance, which poses the problem of being complex as a single logic gate. Ta.
この発明は上記のような問題点を解消するためになされ
たもので、回路構造が簡単にできることを目的とする。This invention was made to solve the above-mentioned problems, and aims to simplify the circuit structure.
この発明に係る謙理ゲート回路は量子干渉計をな（し、
抵抗ジョセフソン素子だけで論理ゲート −回路を構成
したものである。The Kenri gate circuit according to this invention functions as a quantum interferometer (
A logic gate circuit is constructed using only resistive Josephson elements.
この発明における論理ゲート回路は、抵抗とジョセフソ
ン素子だけで回路を構成しているので、簡単な回路構造
が実現でき、その電気特性がわかりやすくなる。Since the logic gate circuit according to the present invention consists of only resistors and Josephson elements, a simple circuit structure can be realized and its electrical characteristics can be easily understood.
以下、この発明の一実施例を図に基づいて説明する。第
１図において、１１１ 、１２１ 、 Ｇ引、 １４１
、 ＋５＋ 、 １６１は端子（ノード）であり、（
７１、１８１、＋９１はそれぞれ端子（１１と＋２１
、 ＋４１と１５１ 、１３１と（６１の間に取りつけ
られた抵抗で、その抵抗値をそれぞれＲ７，Ｒ８、Ｒ９
とする。ｕｕ 、 （１１）は出力時の抵抗である。ｕ
ｚ、ｕｉはそれぞれ端子（２１と１３１ 、 Ｉ：引と
（４）の間に取り付けられたト〉ネル形超伝導ジョセフ
ソン素子で、以下Ｊ１２ 、 Ｊ１３と呼ぶ。Hereinafter, one embodiment of the present invention will be described based on the drawings. In Figure 1, 111, 121, G pull, 141
, +5+, 161 are terminals (nodes), (
71, 181, +91 are terminals (11 and +21
, +41 and 151, 131 and (61), and the resistance values are R7, R8, and R9, respectively.
shall be. uu, (11) is the resistance at the time of output. u
Z and ui are tunnel-type superconducting Josephson elements installed between terminals (21 and 131, I: and (4), respectively, and are hereinafter referred to as J12 and J13.
次に、動作について説明する。Next, the operation will be explained.
ジョセフソン素子Ｊ１２． Ｊ１３の電流−電圧特性を
第２図に示す。Josephson element J12. Figure 2 shows the current-voltage characteristics of J13.
ます、端子１１＋の電位ト”ｃ／２（Ｖ） 、 端子１
５１ （”）１１位を−”／２ （Ｖ）一端子（６１）
電位ヲＯＬＶ） Ｋ設定Ｔル。The potential of terminal 11+ is c/2 (V), terminal 1
51 ('') 11th place -''/2 (V) One terminal (61)
Potential (OLV) K setting T.
抵抗１７１ 、１８１ 、１９１についてはＲｔ＝Ｈｓ
（Ｑ）、 ｍ＝９ｆｌｘａｓ （ａ）とする。この
回路の電流電圧状態は、端子１１１ 、１５１に電圧を
かけた直後として、ジョセフソン素子Ｊ１２とＪ１３の
抵抗はほとんどなく、端子１１１と（５１間の電流１１
Ｂは
工１５＝−芸一 （Ａ）
で、端子１３１１１６１間にはほとんど流れていないと
いう状態にあるとする。このとき、出力ＬＪＵＴｌ。For resistors 171, 181 and 191, Rt=Hs
(Q), m=9flxas (a). The current and voltage state of this circuit is immediately after voltage is applied to terminals 111 and 151, there is almost no resistance in Josephson elements J12 and J13, and current 11 between terminals 111 and
Suppose that B is in a state where 15 = - 1 (A), and there is almost no flow between terminals 1311161. At this time, the output LJUTl.
０ＵＴ２の電位はほぼＯＬＶ）である。この状態をＡ状
態とする。The potential of 0UT2 is approximately OLV). This state is called A state.
次に端子（６１に正のパルス電圧ＶＰＬＶ）をかける。Next, apply a positive pulse voltage VPLV to the terminal (61).
Ｖｐは
Ｖｐ ）Ｖｃ＋Ｉｍ （Ｒａ＋Ｒｓ ） ＝Ｖｃ＋ ｌ
ＯＦ、ｓ Ｌｍを満たすものとする。Vp is Vp)Vc+Im (Ra+Rs) =Vc+l
OF, s Lm shall be satisfied.
これにより、ジョセフソン素子Ｊ１３に臨界電流Ｉｔｎ
よりも大きくなるような電流が流れ、ジョセフソン素子
Ｊ１３は電圧状態にスイッチする。端子＋６１にかかる
電位が□ｖにもどると、ジョセフソン素子Ｊ＋３には電
流が流れな（なり、端子（３１の電位■３はとなり、ジ
ョセフソン素子Ｊ１２の抵抗はほぼ０Ωと考えられるの
で、端子（２１の電位■２もｏ Ｖｃ Ｖ
ｃ
Ｖ２＝ｍ（ｚ’〜了（Ｖ）
を示す。端子（４１の電位はジョセフソン素子Ｊ１３の
抵抗が非常に大きくなっていることを考えるとＶｃ
Ｖ４ ＝ −−ＬＶ）
となっており、ノード１２１ 、 （４１間に電圧〜Ｖ
ｃが現われる。また、Ａ状態にあるもので、端子（６）
に負のパルス電圧−Ｖｐ（Ｖ）をかけると、先と同様に
してジョセフソン素子Ｊ１２が電圧状態になりＶ２＝＝
ヱ（−！−！−）〔ｖ〕
で、ノード１２＋ 、 １４１間に電圧−ＶＣが祝われ
ゐ。This causes the Josephson element J13 to have a critical current Itn.
Flows a current greater than , and Josephson element J13 switches to a voltage state. When the potential applied to terminal +61 returns to □v, no current flows through Josephson element J+3, and the potential of terminal (31 becomes □3. Since the resistance of Josephson element J12 is considered to be approximately 0Ω, (Potential of 21■2 is also o Vc V
c V2 = m (z'~represents (V).The potential of terminal (41 is Vc V4 = --LV) considering that the resistance of Josephson element J13 is very large. The voltage between nodes 121 and 41 is ~V
c appears. Also, in the A state, terminal (6)
When a negative pulse voltage -Vp (V) is applied to
At ヱ(-!-!-) [v], a voltage -VC is celebrated between nodes 12+ and 141.
〔発１の効果〕
以上のようにこの発明によれば、超伝導ジョセフソン素
子と抵抗たけで、論理ゲート回路を構成したので、回路
構造が極めて簡単で製作しやすく、かつ極めて安価で精
度の高いものが得られる効果がある。[Effects of Irradiation 1] As described above, according to this invention, a logic gate circuit is constructed using only a superconducting Josephson element and a resistor, so the circuit structure is extremely simple and easy to manufacture, and it is also extremely inexpensive and highly accurate. It has the effect of getting expensive things.
第１図はこの発明の一実施例による論理ゲート回路図、
第２図はトシネル形ジョセフソシ素子の電流−電圧特性
曲線図、第３図は従来の論理ゲート回路図である。
図において、ｉｌ＋ 、 （２１、ｌ滲、 （４１、１
５＋ 、 （６１は端子、＋７１ 、１８１ 、１９１
、 Ｑ［Ｉ 、αυは抵抗、ｔｌり１３はトンネル形
超伝導ジョセフソン素子である。FIG. 1 is a logic gate circuit diagram according to an embodiment of the present invention.
FIG. 2 is a current-voltage characteristic curve diagram of a Tossinel-type Joseph Sochi element, and FIG. 3 is a conventional logic gate circuit diagram. In the figure, il+ , (21, l 滲, (41, 1
5+, (61 is the terminal, +71, 181, 191
, Q[I, αυ are resistances, and t13 is a tunnel type superconducting Josephson device.
Claims (1)
方の端子１に抵抗１を取り付け、抵抗１を介してある電
位１を与え、上記ジョセフソン素子のもう一方の端子に
は、別のトンネル形ジョセフソン素子２を取り付け、そ
の取り付けた端子に抵抗２を取り付け、その抵抗２を介
した端子２に基準電位を与え、またはパルス電位ジョセ
フソン素子２のもう一方の端子３には、抵抗３を取り付
け、抵抗３を介して、電位２を与え、基準電位が電位１
と電位２の間にあるようにし、端子２を入力端子、端子
１と端子３を出力端子としたことを特徴とする超伝導論
理ゲート回路。A two-terminal tunnel-type Josephson element 1 and a resistor 1 are attached to one terminal 1 of the element, a certain potential 1 is applied through the resistor 1, and another tunnel-type element is connected to the other terminal of the Josephson element. Attach the Josephson element 2, attach the resistor 2 to the attached terminal, and apply a reference potential to the terminal 2 via the resistor 2, or connect the resistor 3 to the other terminal 3 of the pulsed potential Josephson element 2. Attach, apply potential 2 through resistor 3, and set the reference potential to potential 1.
A superconducting logic gate circuit characterized in that the terminal 2 is an input terminal, and the terminals 1 and 3 are output terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158034A JPS642416A (en) | 1987-06-25 | 1987-06-25 | Superconductive logic gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158034A JPS642416A (en) | 1987-06-25 | 1987-06-25 | Superconductive logic gate circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH012416A true JPH012416A (en) | 1989-01-06 |
| JPS642416A JPS642416A (en) | 1989-01-06 |
Family
ID=15662826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62158034A Pending JPS642416A (en) | 1987-06-25 | 1987-06-25 | Superconductive logic gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642416A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5170080A (en) * | 1991-08-14 | 1992-12-08 | Westinghouse Electric Corp. | Superconducting push-pull flux quantum digital logic circuits |
| JP2009076556A (en) * | 2007-09-19 | 2009-04-09 | Denso Corp | Transformer with short ring |
-
1987
- 1987-06-25 JP JP62158034A patent/JPS642416A/en active Pending
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