JPS62176321A - Input noise shutting off system - Google Patents

Input noise shutting off system

Info

Publication number
JPS62176321A
JPS62176321A JP1929786A JP1929786A JPS62176321A JP S62176321 A JPS62176321 A JP S62176321A JP 1929786 A JP1929786 A JP 1929786A JP 1929786 A JP1929786 A JP 1929786A JP S62176321 A JPS62176321 A JP S62176321A
Authority
JP
Japan
Prior art keywords
circuit
output
circuits
input
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1929786A
Other languages
Japanese (ja)
Inventor
Takashi Matsumoto
隆 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1929786A priority Critical patent/JPS62176321A/en
Publication of JPS62176321A publication Critical patent/JPS62176321A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To protect the entire circuit of the titled system from the noise attended with an output circuit switching by disconnecting a signal from an input terminal during the transient period of the output circuit. CONSTITUTION:The input of an exclusive OR circuit is connected to each input/ output of n-set of output circuits 11, 12-1n capable of being operated simultaneously and an output of exclusive OR circuits 21, 22-2n connects to a NOR circuit 3. When at least one of the n-set of output circuits 11-1n is in the transient state, the output of the NOR circuit 3 goes to '0' to interrupt latch circuits 61-6m inserted between input terminals 41-4m and an internal circuit 5. In applying the system to an input terminal susceptible to a noise, the circuit is protected from the noise at the time of output circuit switching.

Description

【発明の詳細な説明】 〔産業上の利用分野」 本発明は、半導体集積回路の中にあって、出力回路がス
イッチングする際の過度電流により発生する雑音の入力
端子からの進入をしゃ断する方式〔従来の技術〕 一般に、論理集積回路において、多出力同時動作によっ
て引き起こされる動作不良がある。これは、多くの出力
回路が同時に動作する事による多大な過渡電流が、着目
している論理集積回路のGNDレベルを変動せしめ、等
測的に入力端子から雑音が進入する事により回路を誤動
作に至らしめるものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for blocking noise generated by transient current when an output circuit switches from entering from an input terminal in a semiconductor integrated circuit. [Prior Art] Generally, in logic integrated circuits, there are malfunctions caused by simultaneous operation of multiple outputs. This is because large transient currents caused by many output circuits operating simultaneously cause the GND level of the logic integrated circuit to fluctuate, and noise enters isometrically from the input terminals, causing the circuit to malfunction. It is something that leads to.

従来、この種の出力回路同時動作が及ぼす悪影響から回
路を守り動作安定化を行なう手段として、複数の出力回
路の過渡電流が一時期に集中しない様な配慮を行なって
きた。
Conventionally, as a means of protecting circuits from the adverse effects of this kind of simultaneous operation of output circuits and stabilizing their operation, consideration has been taken to prevent transient currents of a plurality of output circuits from concentrating at a single time.

それは第4図に示すように、同時に動作する可能性のあ
る複数の出力回路11.12〜1oに対し、その前段に
信号広幅遅延時間の相互に異なる遅延回路82〜8nを
挿入する事で実現されてきた。
This is achieved by inserting delay circuits 82 to 8n with mutually different signal width delay times in front of multiple output circuits 11.12 to 1o that may operate simultaneously, as shown in Figure 4. It has been.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の方式は、以下2点の欠点を持つ。 The conventional method described above has the following two drawbacks.

先ず、第1に出力回路に過渡電流が流れている期間、す
なわち出力回路出力値が変化している期間に応じて遅延
回路に設定すべき遅延量を決めなければならない点が挙
げられる。一般に出力回路の過渡期間は出力回路に接続
される負荷により変化する。そのため、この方式を適用
する場合は出力負荷条件に応じた遅延回路の設計が必要
となり、回路設計を難しくしてしまう。
First, the amount of delay to be set in the delay circuit must be determined in accordance with the period during which a transient current is flowing through the output circuit, that is, the period during which the output value of the output circuit is changing. Generally, the transient period of an output circuit changes depending on the load connected to the output circuit. Therefore, when this method is applied, it is necessary to design a delay circuit according to the output load conditions, which makes circuit design difficult.

第2に、内部回路からの出力信号が出力回路前段の遅延
回路に到達する時刻がかわっていないと、この方式が適
用できないという点である。
Second, this method cannot be applied unless the time at which the output signal from the internal circuit reaches the delay circuit before the output circuit changes.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の入力雑音しゃ断力式は、出力回路が過渡期間中
にある時は、出力過度状態検出回路によりその事を表示
する信号を出し、その信号により入力端子と内部回路と
の間の信号伝播経路をしゃ断してしまう事で、回路動作
の安定化を企ろうとするものである。
In the input noise cutting force type of the present invention, when the output circuit is in a transient period, the output transient state detection circuit outputs a signal indicating this, and the signal propagates the signal between the input terminal and the internal circuit. This attempts to stabilize circuit operation by cutting off the route.

1、実施例〕 次に、本発明について図面を参照して説明する。1. Example] Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図であり、第2図は第
1図の回路の動作を示すタイムチャー1−である。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart 1- showing the operation of the circuit of FIG.

同時に動作する可能性のあるn個の出力回路11.12
.〜1nの各々の入出力に排他的論理和回路の入力を接
続し、さらにこれら排他的論理和回路21’、22.〜
2nの出力をNOR回路3に接続しである。n個の出力
回路11〜1nの内部なくとも1ケが過渡期間中にある
時は、第2図のタイムチャーI・に示す如く、NOR回
路3の出力値は“0′となり、入力端子41〜4mと内
部回路5との間に挿入したラッチ回路61〜6mをしゃ
断する。
n output circuits that may operate simultaneously 11.12
.. . ~
The output of 2n is connected to the NOR circuit 3. When at least one of the n output circuits 11 to 1n is in the transition period, the output value of the NOR circuit 3 becomes "0" as shown in time chart I in FIG. 4m and the internal circuit 5 are cut off.

重力式をフリップフロップのクロック、リセット等に接
続される雑音に弱い入力端子に適用する事で、出力回路
スイッチング時の雑音から回路を守る事が出来る。
By applying the gravity method to input terminals that are susceptible to noise, such as those connected to flip-flop clocks and resets, the circuit can be protected from noise during output circuit switching.

さらに、本発明の効果を増す応用例として第3図に示す
2つの回路を紹介する。同図(a)は出力回路出力端子
と排他的論理回路との間に遅延回路を挿入したものであ
り、同図(b)は遅延回路の代わりにヒステリシス回路
を挿入したものである。共に、出力回路の実際の過渡期
間と、排他的論理和回路から出力される過渡状態表示信
号との間のずれを補償する効果がある。
Furthermore, two circuits shown in FIG. 3 will be introduced as application examples that increase the effects of the present invention. 4A shows a circuit in which a delay circuit is inserted between the output terminal of the output circuit and the exclusive logic circuit, and FIG. 2B shows a circuit in which a hysteresis circuit is inserted in place of the delay circuit. Both have the effect of compensating for the deviation between the actual transient period of the output circuit and the transient state display signal output from the exclusive OR circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、出力回路過渡期間中は入
力端子からの信号をしゃ断する事で、回路を出力回路ス
イッチングに伴なう雑音から守る効果がある。
As explained above, the present invention has the effect of protecting the circuit from noise caused by output circuit switching by cutting off the signal from the input terminal during the output circuit transition period.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は第1
図の動作を示すタイムチャート、第3図(a>、(b)
は本発明の他の実施例の回路図、第4図は従来例の回路
図である。 11 、 12.〜l n−出力回路、21.22゜〜
20・・・排他的論理和回路、3・・・NOR回路、5
・・・内部回路、61.〜6m・・・ラッチ回路。 男1図 、lv7m)7/ 7−13  □ 第2区
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Time chart showing the operation shown in Fig. 3 (a>, (b))
4 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional example. 11, 12. ~l n-output circuit, 21.22°~
20... Exclusive OR circuit, 3... NOR circuit, 5
...internal circuit, 61. ~6m...Latch circuit. Male 1 figure, lv7m) 7/ 7-13 □ Ward 2

Claims (1)

【特許請求の範囲】[Claims]  出力回路の入力信号と出力信号との排他的論理和をと
る事により出力回路が過渡状態にある事を表示する信号
を得て、この信号で入力端子と内部回路との間の信号伝
播経路をしや断する事により、出力回路動作に伴ない発
生する雑音の入力端子からの進入を阻止する事を特徴と
する入力雑音しや断方式。
By taking the exclusive OR of the input signal and output signal of the output circuit, a signal indicating that the output circuit is in a transient state is obtained, and this signal is used to determine the signal propagation path between the input terminal and the internal circuit. An input noise shielding method characterized by blocking noise generated due to output circuit operation from entering from the input terminal by shielding the input terminal.
JP1929786A 1986-01-30 1986-01-30 Input noise shutting off system Pending JPS62176321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1929786A JPS62176321A (en) 1986-01-30 1986-01-30 Input noise shutting off system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1929786A JPS62176321A (en) 1986-01-30 1986-01-30 Input noise shutting off system

Publications (1)

Publication Number Publication Date
JPS62176321A true JPS62176321A (en) 1987-08-03

Family

ID=11995487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1929786A Pending JPS62176321A (en) 1986-01-30 1986-01-30 Input noise shutting off system

Country Status (1)

Country Link
JP (1) JPS62176321A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586621A (en) * 1981-07-03 1983-01-14 Mitsubishi Electric Corp Malfunction preventing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586621A (en) * 1981-07-03 1983-01-14 Mitsubishi Electric Corp Malfunction preventing circuit

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