JPH02237215A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To compensate phase shift without an external circuit by adding a delay/compensation circuit compensating the difference of a signal delay on a signal transmission line to the internal part of a circuit. CONSTITUTION:One of a signal synchronized by a trigger signal T1 and outputted from flip flops 1 and 2 is outputted from an output driving element 6 through inverters 3 and 4 and the other signal is outputted from an output driving element 7 through an inverter 5. In such a case, a delay time in the inverter 5 and the total delay time in the inverters 3 and 4 become equal and phase shift can be prevented since an equivalent delay element 8 comes to be a load with respect to the inverter 5 and the delay time in the inverter 5 becomes large. Since the delay/compensation circuit is incorporated in an integrated circuit, phase shift due to the difference of the number of elements on the signal transmission line can be prevented without adjustment by the external circuit and the number of parts in a device using the circuit can be reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit that performs logical operations.

[Conventional technology]

FIG. 2 shows a conventional semiconductor integrated circuit, in which 1
, 2 is a flip-flop, 3 to 5 are inverters, 6, 7
is an output driving element.

Next, the operation will be explained.

Logic signals generated by other logic circuits are connected to the internal terminal DI.
, D2, respectively. These signals are applied to data terminals D of flip-flops 1 and 2. On the other hand, a trigger signal is applied from the T1 terminal to the toggle terminal T of the flip-flop, and the signal applied to the data terminal is output from the flip-flop in synchronization. flip flop 1
. When it is necessary to output signals with opposite phases to output terminals 01 and 02 as in this circuit, the number of elements between the synchronized outputs of flip-flops 1 and 2 and output terminals 01.02 is one stage. It will be different.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, since the number of element stages differs between the two signals, the difference in delay time for the signal to pass through the element increases, causing a phase shift in the signals output to output terminals 01 and 02. There was a problem. Compensation for this phase shift must be performed by attaching an external circuit, which poses problems such as an increase in the number of parts and difficulty in adjustment.

This invention was made to solve the above-mentioned problems, and it is possible to correct the phase shift of the signal due to the difference in delay time between two signals in which the number of stages of elements through which the signal passes differs without using an external circuit. The purpose is to obtain a semiconductor integrated circuit that can compensate.

[Means to solve the problem]

The semiconductor integrated circuit according to the present invention is capable of compensating for phase shifts without an external circuit by adding a delay compensation circuit inside the circuit to compensate for differences in signal delays on signal transmission paths.

[Effect]

The delay compensation circuit according to the present invention increases the signal delay amount on the signal transmission path of the signal passing through the element with a shorter delay time by using the equivalent delay generation element and the termination processing element for automatic placement and wiring. The amount of signal delay between the two signals becomes equal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention, in which 1.2 is a flip-flop, 3 to 5 are inverters, 6 and 7 are output driving elements, 8 is an equivalent delay generating element, and 9 is an inverter. is a termination processing element for automatic placement and wiring.

Next, the operation will be explained. One of the signals output from the flip-flops 1 and 2 in synchronization with the trigger signal T1 passes through the inverters 3 and 4 and is output from the output drive element 6, and the other passes through the inverter 5 and is output from the output drive element 7. Ru. In this case, although the number of elements passing through the path described later is smaller, the added equivalent delay element 8 becomes a load on the inverter 5, and the delay time in the inverter 5 increases. Therefore, the delay time in inverter 5 becomes equal to the total delay time in inverters 3 and 4, and phase shift can be prevented. In addition, in the case of automatic placement and wiring, which automatically determines the position of each element in an integrated circuit (generally referred to as placement) and automatically performs signal wiring between each element (generally referred to as wiring), internal elements are used as both input and output. Since it is necessary to connect it in some way, in this case, in order to prevent the output of equivalent delay element 8 from becoming unconnected, a termination processing element 9 is connected to this.
is added. The output of the termination processing element 9 is looped to its input to avoid opening of the output terminal.

Further, in the above embodiment, a three-man NAND element was used as the termination processing element 9, but a flip-flop 9b may be used as shown in another embodiment of the present invention in FIG. It has a similar effect.

Further, in the above embodiment, a circuit in which only an inverter is interposed between the flip-flops 1 and 2 and the output drive elements 6 and 7 has been described, but this is not applicable to a NAND circuit or an AND circuit other than an inverter. A logic element such as an OR circuit or a NOR circuit may be involved, and a logic element other than an inverter may be used as the equivalent delay element, and the same effect as described above can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the delay compensation circuit is built into the integrated circuit, phase shifts due to differences in the number of elements in the signal transmission path can be eliminated without adjustment by an external circuit. This has the effect of reducing the number of parts of a device using the circuit and also reducing costs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a signal transmission circuit using a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional signal transmission circuit, and FIG. 3 is a signal transmission circuit according to another embodiment of the invention. FIG. In the figure, 1 and 2 are Furi Sop Fro Sop, 3, 4,
5 is an inverter, 6 and 7 are output driving elements, 8 is an equivalent delay generating element, and 9 is a termination processing element for automatic placement and wiring.

Claims (1)

[Claims] 1) In a semiconductor integrated circuit having a plurality of logic circuits that are triggered by one signal, a delay compensation circuit that compensates for differences in delays on signal transmission paths of signals output from each of the logic circuits. A semiconductor integrated circuit characterized by comprising: