JPH0645879A - Flip flop - Google Patents

Abstract

PURPOSE:To provide a flip flop which is capable of quick operation and easily controls data selection by selecting prescribed data out of plural various input data by a selecting means provided in a master part and supplying this selected data as output data of the slave to a slave part. CONSTITUTION:Data Da is latched in a clocked inverter 55 and an inverter 56 through a clocked inverter 51 in the master part, and data Db is latched in a clocked inverter 57 and an inverter 58 through a clocked inverter 52. One of latched data Da and Db is selected by clocked inverters 53 and 54 and is sent to the slave part. In the slave part, the selection result is taken into a clocked inverter 59 and an inverter 60 and is outputted as output data Q through an inverter 61. These operations are controlled by control signals CP and CA or CB and their inverted signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop in a semiconductor integrated circuit (IC or LSI) which is required to operate at high speed.

[0002]

2. Description of the Related Art In recent years, L which requires high performance
In SI, a design that meets the demand for high-speed operation is required. In order to meet this request, in the conventional combinational logic circuit, when either one of the two data is selected and taken into a flip-flop (hereinafter, simply referred to as F / F), for example, the configuration shown in FIG. The logic circuit of was used.

FIG. 5 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit.

As shown in the figure, this semiconductor integrated circuit has clocked inverters 1 and 2 and inverters 3 and 4.
And a F / F5. One of the data Da and Db input to the clocked inverters 1 and 2 is selected by the enable signal ei and its inverted signal eh, and is taken into the F / F 5 via the inverter 4. . Here, a circuit diagram showing the internal configuration of the clocked inverter 1 is shown in FIG.

In FIG. 6, the clocked inverter 1 includes P-MOSs 1a and 1b and N-MOSs 1c and 1d.
It is composed of. The enable signal ei is supplied to the gate of the P-MOS 1a, and the inverted signal eh of the enable signal ei is supplied to the gate of the N-MOS 1d.
Data D is applied to the gates of -MOS1b and N-MOS1c.
a is supplied. And P-MOS
The drains of 1b and the N-MOS 1c are output terminals for the output signal f. In the clocked inverter 2, the signal eh is supplied to the N-MOS 1d instead of the signal ei supplied to the P-MOS 1a.
Instead of being supplied with the signal ei, it has the same configuration as the clocked inverter 1.

FIG. 7 is a circuit diagram showing the internal structure of the F / F 5.

The F / F 5 is composed of clocked inverters 5a, 5b, 5c, 5d and inverters 5e, 5f, 5g as shown in FIG.
b and the inverter 5e, and the clocked inverter 5d and the inverter 5f form a latch circuit. The data input terminal D is connected to the input side of the clocked inverter 5a, and the output terminal Q is connected to the output side of the inverter 5g.
Are connected. The clocked inverter 5a,
5b and 5c and the inverter 5e constitute a master unit, and the clocked inverter 5d and inverters 5f and 5g constitute a slave unit.

Further, these clocked inverters 5a ...
The generation circuit of the control signals CP and CPN supplied to 5d is
As shown in FIG. 8, the inverters 6a and 6b are connected in cascade to receive the clock CK.

In the active operation of the semiconductor integrated circuit configured as described above, in which the clock CK is at "H" level, the data Da is at "H" level when the enable signal ei is at "L" level. At this time, the data b is selected. The selected data is taken into the F / F 5, and the F / F 5 operates based on the operation truth table shown in FIG.

[0010]

However, in the semiconductor integrated circuit having the above configuration, for example, when the data Db is selected and fetched into the F / F5, as shown in the timing chart of FIG. In order to capture in the F / F5, it is necessary to determine the A data before the time Z which is the setup time m of the F / F5 plus the delay time n (delay time of the clocked inverter 1 and the inverter 4) of the multiplexer. is there. If it is not in time, wrong B data will be taken in and no malfunction will occur. As described above, the point that the A data needs to be determined before the time Z has been an obstacle to the high speed operation.

Further, the enable signal ei for selecting the data Da or the data Db must be determined before the data A, which causes a problem that the control becomes complicated.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to realize an F / F which enables high-speed operation and can easily control data selection.
Is to provide F.

[0013]

In order to achieve the above object, a feature of the first invention is that a master unit for taking in input data in synchronization with a clock and output data of the master unit for synchronizing with the clock. In a flip-flop provided with a slave unit that takes in at a predetermined timing, the master unit selects predetermined data from a plurality of different input data and supplies the predetermined data to the slave unit as output data of the slave. It is characterized by having means.

A feature of the second invention is that the selecting means in the first invention comprises a tri-state circuit, and a control signal for controlling the tri-state circuit is provided during an upper or lower level period of the clock. It is characterized in that it is configured to hold a value.

[0015]

According to the first aspect of the invention as described above, since the selecting means provided in the master section performs the data selecting function of selecting the input data, the F / F is the original flip-flop function and the data. It will also have a selection function. As a result, the delay time for fetching the input data only needs to be considered for the flip-flop setup time. Further, the control signal for controlling the tri-state circuit may be determined before the rising edge of the next clock. This makes it easy to control the selection of data.

According to the second invention, the enable signal is
Since the value is held during the upper or lower level of the clock, there is no problem even if the enable signal changes during this period.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an F / F showing a first embodiment of the present invention.

As shown in FIG. 1, this F / F is an F / F having a multiplexer function for selecting data.
The master unit having the multiplexer function is provided with the data D
Clocked inverter 5 to which a and Db are respectively supplied
1, 52, clocked inverters 53, 54 connected to the output side thereof, and the clocked inverters 51, 53
A latch circuit connected between the clocked inverter 55 and the inverter 56, and the clocked inverter 5
The latch circuit is composed of a clocked inverter 57 and an inverter 58, which is connected between 2 and 54.

The slave section includes a latch circuit composed of a clocked inverter 59 and an inverter 60, and an output data Q output inverter 6 connected to the output side thereof.
It is composed of 1 and 1.

Clocked inverters 51, 52, 55,
57 and 59 are controlled by the control signal CP and its inverted signal CPN, and the clocked inverter 53 is controlled by the control signal CA and its inverted signal CAN. The clocked inverter 54 also controls the control signal CB and its inverted signal CBN.
Controlled by.

FIG. 2 is a circuit diagram of a control signal generation circuit for generating a control signal to be supplied to the clocked inverter.

This control signal generating circuit is composed of an inverter 7
1, 72, 73, 74, 75 and 2-input NOR gate 7
It is composed of 6,77. The output side of the inverter 71 is connected to the input side of the inverter 73 and the NOR gates 76, 7
One input side of 7 is connected, and the output side of the inverter 72 is connected to the other input side of the NOR gate 76. The input side of the inverter 72 is the NOR gate 7
NOR gates 76, 77 connected to the other input side of
The output side of is connected to the input sides of the inverters 74 and 75, respectively. The clock CK is the inverter 7
1, the enable signal (control signal) ei is the inverter 7
The control signal CPN is output from the output side of the inverter 71, and the control signal CP is output from the output side of the inverter 73. Further, the control signal CA is output from the output side of the NOR gates 76 and 77.
N and CBN are output respectively, and the inverters 74 and 75 are output.
The control signals CA and CB are respectively output from the output side of.

According to the circuit of FIG. 1, the data Da is transferred to the clocked inverter 5 via the clocked inverter 51.
5 and the inverter 56, and similarly data Db
Are latched by the clocked inverter 57 and the inverter 58 via the clocked inverter 52. Then, one of the latched data Da and Db is selected by the clocked inverters 53 and 54,
The selection result is fetched by the clocked inverters 59 and 60, and then output as output data Q via the inverter 61.

More specifically, in the latter half (“L” level) of the clock CK, both the data Da and Db are taken into each latch circuit. Then, in the first half of the clock (“H” level) and when the enable signal ei is at “L” level, the control signal CA is activated and the data Da
Is output as output data Q. In the first half of the clock (“H” level) and the enable signal ei is “H”.
At the level, the control signal CB is activated and the data D
b is output as output data Q. For example, the timing chart of FIG. 3 shows a timing example when the enable signal ei changes from the “L” level to the “H” level and the data Db is selected.

As is apparent from FIG. 3, in the conventional case, the delay n of the multiplexer is delayed by the rise of the clock CK.
Although the data had to be settled before the time Z, which is the sum of the F / F setup time m, in the present embodiment, the delay n is eliminated, and the same logic circuit accelerates by the clock CK. It is possible to contribute to the speeding up of the system.

Further, regarding the enable signal ei,
Conventionally, the enable signal e is set before the data Da is determined.
i had to be determined, but in this embodiment,
Since it is only necessary to determine the rise of the clock CK, the enable signal ei becomes easier in terms of timing,
Wider range of design.

FIG. 4 shows F / which shows the second embodiment of the present invention.
It is a principal part circuit diagram of F.

The present embodiment is different from the first embodiment in that the control signal generating circuit for generating the control signal to be supplied to the clocked inverter is changed from that shown in FIG. 2 to that shown in FIG. Is.

In the first embodiment, there is a constraint that the enable signal ei should not change during the period when the clock CK is at "H" level, but this embodiment improves this point. .

As shown in FIG. 4, the control signal generating circuit of the present embodiment is a latch circuit including a clocked inverter 81, a clocked inverter 82 and an inverter 83 instead of the inverter 72 in the first embodiment. And the enable signal ei is supplied to the input side of the clocked inverter 81. The clocked inverters 81 and 82 are controlled by the control signal CP and its inverted signal CPN.

With this configuration, the enable signal ei is latched during the period in which the clock CK is at "H" level, so the enable signal ei may change during this period. The problem of the embodiment is improved.

[0032]

As described in detail above, according to the first aspect of the present invention, a master unit that takes in input data in synchronization with a clock and a slave that takes in output data of the master unit at a predetermined timing synchronized with the clock are provided. In the flip-flop having a section, the master section includes selection means for selecting predetermined data from a plurality of different input data and supplying the predetermined data to the slave section as output data of the slave. Conventionally, data selection means such as a multiplexer, which is provided outside, is not required. As a result, the delay time for fetching input data only needs to be considered for the flip-flop setup time, and high-speed operation is possible. Also,
Easy data selection control.

In a second invention, the selecting means in the first invention comprises a tri-state circuit, and a control signal for controlling the tri-state circuit keeps its value during an upper or lower level period of the clock. Since the constitution is such that the first invention is held, the effect of the first invention becomes more remarkable.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an F / F showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a control signal generation circuit that generates a control signal to be supplied to the clocked inverter in the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIG. 4 is a circuit diagram of a main part of an F / F showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit.

FIG. 6 is a circuit diagram showing an internal configuration of a clocked inverter.

FIG. 7 is a circuit diagram showing an internal configuration of a conventional F / F.

FIG. 8 is a diagram showing a control signal generation circuit.

FIG. 9 is a timing chart showing an operation of a conventional semiconductor integrated circuit.

FIG. 10 is a diagram showing an operation truth value of a conventional F / F.

[Explanation of symbols]

51, 52, 53, 54, 55, 57, 59 Clocked inverters 56, 58, 60, 61, 71, 72, 73, 74, 7
5 Inverter ei enable signal (control signal) CK clock

Claims (2)

[Claims] 1. A flip-flop comprising a master unit for capturing input data in synchronization with a clock and a slave unit for capturing output data of the master unit at a predetermined timing in synchronization with the clock, wherein the master unit comprises: A flip-flop, comprising: selecting means for selecting predetermined data from a plurality of different input data and supplying the predetermined data to the slave section as output data of the slave. 2. The selecting means comprises a tri-state circuit, and a control signal for controlling the tri-state circuit is configured to hold its value during a period of an upper level or a lower level of the clock. The flip-flop according to claim 1, wherein: