JP3651659B2 - Latch circuit with enable - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an enable latch circuit capable of controlling the input timing of data latched by an enable signal.
[0002]
[Prior art]
FIG. 3 is a circuit diagram of a conventional latch circuit with enable. The NAND of the enable signal 100 and the clock 200 is taken by NAND1, its output is ClkNN, and the output is inverted by the inverter 2 to create Clk. Clk is supplied to the clocked inverter 3, and ClkNN is supplied to the clocked inverter 5.
[0003]
When the enable signal 100 is at a low level, the output ClkNN of the NAND 1 is at a high level and Clk is at a low level. Therefore, the clocked inverter 3 is cut off, and the data 300 is stored in the latch unit composed of the inverter 4 and the clocked inverter 5. Not entered.
[0004]
When the enable signal 100 becomes high level, Clk becomes high level, so that the clocked inverter 3 operates and the data 300 is input to the inverter 4 of the latch section through the clocked inverter 3. Thereafter, when the enable signal 100 becomes low level, the clocked inverter 3 is cut off, ClkNN becomes high level, the clocked inverter 5 operates, and the input data is held. The retained data is output via inverters 6 and 7.
[0005]
[Problems to be solved by the invention]
By the way, in the conventional latch circuit with enable as described above, the enable signal 100 must be at a low level in a certain clock half cycle period. However, when the enable signal 100 changes from a high level to a low level in the middle of this clock half cycle period, There is a problem in that the shut-off timing of the inverter 3 is shifted and erroneous data is held in the latch portion.
[0006]
That is, in the middle of the clock (Clock) half-cycle period (t0, t1) shown in FIG. 4 (A), the enable signal 100 that should originally be at the low level in this half-cycle period is shown in FIG. 4 (B). As shown in FIG. 4, when the high level is changed to the low level in the middle (time borrow of the enable signal 100), Clk temporarily becomes the high level as shown in FIG. 4C at the beginning of this half cycle period. In this half-cycle period, the clocked inverter 3 that must be cut off temporarily operates temporarily, and a malfunction occurs in which data 300 that should not be input is input to the inverter 4 and erroneous data is retained. .
[0007]
Therefore, in the conventional latch circuit with enable as described above, the enable signal 100 cannot be time borrowed, and the path to the enable signal becomes timing critical. As a result, the previous stage logic must be designed so that the time borrow does not occur. If the previous stage logic becomes an obstacle to speeding up or the above time borrow occurs, the previous stage logic will be revised. Therefore, there is a problem that designing takes time and effort.
[0008]
The present invention has been made in order to solve the above-described conventional problems, and an object of the present invention is to enable enabling to retain correct data without retaining erroneous data even when the enable signal is time-bored. A latch circuit is provided.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized in that, in a latch circuit with an enable for controlling an input timing of data to be held by an enable signal, first data holding means for holding the data, and the first data A second data holding means for holding data held in the holding means with a delay of a half cycle of the clock; and by the enable signal, the input data is held in the first data holding means, or the second data Data selection means for selecting whether the data held by the holding means is held by the first data holding means, and the first data holding means and the second data holding means are inverted clocks of the clock. And connecting with a pass gate that conducts and shuts off , and outputting output data from the first data holding means .
[0011]
Another feature of the present invention is a latch circuit with an enable for controlling an input timing of data to be held by an enable signal. The latch circuit is held by the first data holding means for holding the data and the first data holding means. The second data holding means for holding the data that is delayed by a half cycle of the clock and the enable signal to cause the first data holding means to hold the input data, or the holding data of the second data holding means And a data selection means for selecting whether the first data holding means holds the pass gate, wherein the first data holding means and the second data holding means are turned on and off by an inverted clock of the clock. in connected, the data selections means multiplexer circuit comprising two clocked inverters, said first, second Data holding means is composed of a data storage circuit composed of the inverter and clocked inverter respectively, these circuits is that the operation by the inverted clock and the clock is controlled.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration according to an embodiment of a latch circuit with enable of the present invention. The latch circuit with enable selects either the input data 300 or the held data 301 of the slave latch 50 and inputs the multiplexer 30, the master latch 40 that holds the input data 300, and the held data of the master latch 40 in a half cycle. It consists mainly of a slave latch 50 that holds it late.
[0014]
The multiplexer 30 includes clocked inverters 12 and 14, the master latch 40 includes an inverter 16 and a clocked inverter 17, and the slave latch 50 includes an inverter 19 and a clocked inverter 20.
[0015]
In addition to the above circuit, the enable latch circuit includes an inverter 11 that generates an inverted clock ClkNN of the clock 200, an inverter 13 that generates an inverted signal of the enable signal 100, a clocked inverter 15 that blocks input of data 300, and a master latch. 40 has a pass gate 18 connecting the slave latch 50 and an inverter 21 for holding data output.
[0016]
Next, the operation of this embodiment will be described. The enable signal 100 of this example is used for selection control of the multiplexer 30. That is, when the enable signal 100 is at a high level, the clocked inverter 12 operates, and the clocked inverter 14 to which the inverted signal of the enable signal 100 is input to the control terminal is cut off. Thus, the multiplexer 30 selectively inputs the input data 300 and inputs it to the clocked inverter 15. At this time, if the clock 200 is at a high level, the clocked inverter 15 operates and the data 300 is input to the inverter 16 of the master latch 40.
[0017]
Next, when the clock 200 becomes low level, the clocked inverter 15 is cut off. At this time, ClkNN becomes high level, the clocked inverter 17 operates, and the master latch 40 holds the input data. At this time, since the pass gate 18 becomes conductive, the data held in the master latch 40 is input to the inverter 19 of the slave latch 50, and when the clock 200 subsequently becomes high level, the clocked inverter 20 operates and the data Is held in the slave latch 50. Therefore, the same data as the data held in the master latch 40 is held in the slave latch 50.
[0018]
Thereafter, when the enable signal 100 becomes low level, the clocked inverter 12 is cut off and the clocked inverter 14 is operated, so that the data held in the slave latch 50 is input to the clocked inverter 15. Thereafter, the same data is continuously held by repeating the cycle that the data held in the slave latch 50 is held in the master latch 40.
[0019]
Here, an operation when a time borrow occurs in the enable signal 100 will be described with reference to a time chart of FIG. The enable signal 100 must originally be at a low level in the clock half cycle period (t0, t1) shown in FIG. 2, but in the middle of this clock half cycle period, the enable signal 100 is shown in FIG. Thus, at the beginning of this half cycle period, the clocked inverter 12 becomes conductive, and data 300 (b) as shown in FIG. I will enter it.
[0020]
During this half-cycle period, since Clk is at the high level, the clocked inverter 15 inputs the input data 300 (b) to the master latch 40. At this time, since ClkNN is at the low level, the pass gate 18 Is cut off, and the input data 300 (b) is not input to the slave latch 50, and the slave latch 50 holds the data 301 (a) that should be originally held.
[0021]
Thereafter, when the enable signal 100 becomes a low level during the half cycle period, the clocked inverter 12 is cut off and the clocked inverter 14 is operated, so that it is held in the slave latch 50 as shown in FIG. The data 301 (a) thus inputted is inputted to the master latch 40 through the clocked inverters 14 and 15.
[0022]
Next, when the clock 200 becomes low level, ClkNN becomes high level, the clocked inverter 17 operates, and the data 301 (a) is held in the master latch 40. The subsequent steps are the same as in the normal operation described above.
[0023]
According to the present embodiment, even if the enable signal 100 is time-borrowed, the error data captured for a moment is repaired and the normal data held in the slave latch 50 is held in the master latch 40. Even if the borrow is allowed, the malfunction of the latch can be eliminated.
[0024]
Accordingly, the enable signal 100 can be time-bored, the critical path can be deleted, and the logic of the previous stage can be easily designed, and the speed of the logic can be easily realized. it can.
[0025]
In addition, when replacing the latch circuit with enable in this example with the old one, it is possible to replace it without changing the peripheral circuit, and it is not necessary to perform RTL correction / logic synthesis, etc., so the time borrow is easily permitted. The effect which can be obtained can be acquired and the period of change design can be shortened.
[0026]
Furthermore, if the latch circuit with enable of this example is a standard cell, there is no need to consider the wiring length or hold violation between latches, as in the case where the same configuration is realized by changing the logic, and the logic design is extremely It can be done easily.
[0027]
【The invention's effect】
As described above in detail, according to the latch circuit with enable according to the present invention, even if the enable signal is time borrowed, it is possible to retain correct data without retaining erroneous data. And the logic of the previous stage can be easily increased in speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration according to an embodiment of an enable latch circuit of the present invention.
FIG. 2 is a time chart for explaining an operation when a time borrow of an enable signal occurs in the circuit shown in FIG. 1;
FIG. 3 is a circuit diagram showing a configuration example of a conventional latch circuit with enable.
4 is a time chart for explaining an operation when a time borrow of an enable signal occurs in the circuit shown in FIG. 3; FIG.
[Explanation of symbols]
11, 13, 16, 19, 21 Inverters 12, 14, 15, 17, 20 Clocked inverter 18 Pass gate 30 Multiplexer 40 Master latch 1 Slave latch

Claims (2)

In a latch circuit with enable for controlling the input timing of data to be held by an enable signal,
First data holding means for holding the data;
Second data holding means for holding the data held in the first data holding means with a delay of half a clock cycle;
Data selection means for selecting whether to hold input data in the first data holding means or hold data in the second data holding means in the first data holding means in accordance with the enable signal; , And
An enable characterized in that the first data holding means and the second data holding means are connected by a pass gate which is turned on and off by an inverted clock of the clock, and output data is output from the first data holding means. With latch circuit. In a latch circuit with enable for controlling the input timing of data to be held by an enable signal,
First data holding means for holding the data;
Second data holding means for holding the data held in the first data holding means with a delay of half a clock cycle;
Data selection means for selecting whether to hold input data in the first data holding means or hold data in the second data holding means in the first data holding means in accordance with the enable signal; , And
The first data holding means and the second data holding means are connected by a pass gate that is turned on and off by an inverted clock of the clock,
The data selection means is a multiplexer circuit composed of two clocked inverters, and the first and second data holding means are each composed of a data storage circuit composed of an inverter and a clocked inverter. A latch circuit with an enable, the operation of which is controlled by an inverted clock.

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