JP2002009613A - Reconfiguration method for circuit function, and programmable logic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reconfiguration method for a circuit function and a programmable logic circuit device, that can continue processing for regions other than the reconfigured region, in the case of partially reconfiguring the circuit function in operation. SOLUTION: A tree-like block line 18, circulated on a programmable logic circuit device 10, is divided into two systems: a clock line 18A for supplying a clock signal to each logic cell 12 of a region 30A and a clock line 18B to supply the clock signal to each logic cell 12 of a region 30B and the regions 30A, 30B independently control the supply of the clock signal. Thus, in the case of reconfiguring the circuit function that is configured on the region 30A or 30B, the supply of the clock signal to the reconfiguration region only is stopped, and the supply of the clock signal is continued to the other region so as to continue the processing by the circuit function configured in the other regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reconfiguring circuit functions and a programmable logic circuit device, and more particularly to a method for reconfiguring circuit functions in a programmable logic circuit device capable of partially reconfiguring circuit functions. And a programmable logic circuit device.

[0002]

2. Description of the Related Art In recent years, in the field of digital logic circuit products, particularly application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have been developed in order to shorten the development period of products.
Such programmable logic circuit devices are widely used.

In these devices, by reading circuit information describing a logic circuit, a connection between internal logic circuits and a logic circuit can be freely configured. This allows
This eliminates the need for weeks to months of integrated circuit fabrication after circuit design, which was required before the use of programmable logic circuits. In particular, U.S. Pat.
Electrically reconfigurable programmable logic devices, such as the invention disclosed in US Patent No. 187, have the advantage of allowing a circuit once fabricated to be freely modified as often as needed, and are becoming more and more widely used. It has become.

[0004] Recently, logic circuits have increased in complexity, and the circuit scale has been increased to a scale that cannot be realized by a single programmable logic circuit device.

[0005] One way to solve this problem is to:
That is, a plurality of programmable logic circuit devices are connected and used. However, since the number of input / output connections of the programmable logic device is limited, it is difficult to realize all circuits by this method. Further, even if it can be realized, a new drawback that power consumption increases with an increase in the number of programmable logic circuit devices to be used is caused.

[0006] Another solution is to reconfigure the programmable logic circuit device again in the middle of processing so that the same programmable logic circuit device realizes a different logic circuit. In this case, when reconfiguring, it is necessary to read the circuit information into the internal storage device (SRAM) again, which has the disadvantage that extra time is required. Furthermore, reconfiguring in the middle of processing requires suspending the processing, storing the data at that time in a storage device external to the programmable logic circuit device, and then reading new circuit information to reconfigure. No. That is, before and after reconstruction,
Extra processing of inputting and outputting data to and from an external storage device is required.

In order to solve this problem, for example, a programmable logic circuit device represented by Model No. AT40K or Model No. AT6000 manufactured by Atmel Inc. of the United States has a data storage device for storing data when performing reconfiguration. The time required for reconfiguration is kept to a minimum by reading a part of the circuit information from an external storage device and partially reconfiguring the circuit even while the circuit is operating (Atmel US data book "CONFIGURABLE LOGIC" reference).

[0008]

However, when performing the above partial reconfiguration, even when reconfiguring only a part of the circuit in the chip, the clock of the entire chip is stopped.
Circuit information for reconfiguration must be loaded into the SRAM. Further, data input to the circuit after reconfiguration needs to be held in a register, and the clock of this register must also be stopped. At this time, it is not possible to proceed with the processing in other parts in the chip because the clock is stopped, so that an overhead corresponding to the load time of the circuit data is generated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. When a circuit function is partially reconfigured during operation, a circuit function that can continue processing in a region other than the reconfiguration area can be reconfigured. It is an object to provide a configuration method and a programmable logic circuit device.

[0010]

To achieve the above object, a method for reconfiguring a circuit function according to claim 1 is a method for reconfiguring a circuit function in a programmable logic circuit device capable of partially reconfiguring a circuit function. A configuration method, wherein a clock line in an area where a circuit function to be reconfigured is arranged is separated from a clock line in another area, and a clock in an area where the circuit function to be reconfigured is arranged is reconfigured. It is characterized in that the supply of the clock signal is stopped only for the line and the circuit function is reconfigured.

In the method for reconfiguring a circuit function according to the first aspect, an area in which the reconfigured circuit function is arranged (hereinafter referred to as a region).
The clock line in the “reconstruction area” is separated from the other area clock lines, and when performing the reconstruction, the supply of the clock signal is stopped only in the clock line in the reconstruction area and the circuit function Is reconstructed. That is, the supply of the clock signal to the area other than the reconfiguration area does not need to be stopped, and when the circuit function is partially reconfigured, the processing is not performed in the circuit function configured in the area other than the reconfiguration area. It can be done continuously.

According to a second aspect of the present invention, there is provided a programmable logic circuit device including a plurality of logic cells, wherein the programmable logic circuit is divided into a plurality of regions in which circuit functions can be reconfigured.
A clock line connected to each of the plurality of regions so as to be capable of independently supplying a clock signal; and clock signal supply stopping means for supplying and stopping a clock signal for each clock line.

[0013] In the programmable logic circuit device according to the second aspect, the programmable logic circuit including a large number of logic cells is divided into a plurality of areas in which circuit functions can be reconfigured. A clock line is connected to each of the divided areas so that a clock signal can be supplied independently. The clock signal supply stopping means supplies and stops the clock signal for each clock line.
The supply of the clock signal can be controlled for each of the divided areas.

Thus, when the circuit function is reconfigured,
The reconfiguration can be performed by stopping and controlling only the supply of the clock signal to the area where the circuit function to be reconfigured is arranged, and the circuit function configured in the area other than the reconfiguration area should continue processing. Can be.

According to a third aspect of the present invention, there is provided a programmable logic circuit device comprising: a programmable logic circuit including a plurality of logic cells; a clock line provided to supply a clock signal to each of the logic cells; A switching unit that is provided on a line and switches to one of a supply state and a stop state of a clock signal for each of the logic cells, so that the clock line can be divided into a plurality of clock lines; And clock signal supply stopping means for supplying and stopping a clock signal for each clock line.

According to a third aspect of the present invention, a clock line is provided so that a clock signal can be supplied to each of a large number of logic cells provided in the programmable logic circuit. This clock line is divided into a plurality of parts by switching the clock signal to the supply state or the stop state for each logic cell by the switching means. For each of the divided clock lines, the clock signal supply stop means Supply and shutdown are performed.

The clock line connected to all the logic cells may be cut at an arbitrary point by the switching means to divide the clock line into a plurality of parts, or the clock line may be fragmented and switched. The clock line may be divided into a plurality of parts by connecting at arbitrary points by means.

According to this, if the switching unit divides the clock line for each area where the circuit function to be reconfigured is arranged, only the supply of the clock signal to the area where the circuit function to be reconfigured is arranged is stopped and controlled. Reconfiguration can be performed, and processing can be continued in circuit functions configured in an area other than the reconfiguration area. Further, a reconfiguration area can be arbitrarily set on the programmable logic circuit according to the circuit design.

However, the number of logic cells to which the divided clock lines supply the clock signal changes depending on the circuit design. Therefore, when the clock signal is supplied by the clock signal supply stopping means as described in claim 4, It is preferable to further comprise a setting means for setting the driving capability of each of the clock lines divided by the switching means in accordance with the number of logic cells supplying the clock signal by the clock line.

[0020]

Next, an example of an embodiment according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a schematic configuration of a programmable logic circuit device to which the present invention is applied. As shown in FIG. 1, the programmable logic circuit device 10 includes a plurality of logic cells 12 arranged two-dimensionally.
, A wiring region 14, and an input / output terminal 16.
The logic cell 12, the wiring region 14, and the input / output terminal 16 constitute a programmable logic circuit of the present invention (see claims 2 and 3).

In the logic cell 12, an arbitrary logic function can be generated by changing the internal circuit configuration. In the wiring area 14, it is possible to arbitrarily connect between the logic cells 12 and between the logic cells 12 and the input / output terminals 16.

The logic cell 12 and the wiring area 14 are provided with rewritable memory elements such as SRAMs and DRAMs. The programmable logic circuit device 10 includes a configuration memory constituted by these memory elements. (Not shown).

When an address is given to this configuration memory (not shown) and new circuit information data is stored, the circuit configuration in the logic cell 12 and the space between each logic cell 12 and each logic cell are stored in accordance with this circuit information. The connection state of the wiring region 14 for interconnecting the I / O terminal 12 and the input / output terminal 16, that is, the circuit function (hereinafter simply referred to as “circuit”) of the programmable logic circuit device 10 is reconfigured. This series of operations is called a configuration.

In the programmable logic circuit device 10, a part of the configuration memory (not shown) is rewritten so that the circuit can be partially reconfigured even while the programmable logic circuit device 10 is operating. Has become.

The configuration operation can be performed only when a configuration enable signal (Config_enable) input from the outside is in an enabled state.

Next, the configuration related to the supply of the clock signal in the programmable logic circuit device 10 will be described in detail. FIG. 2 shows this programmable logic circuit device 10.
1 shows a detailed configuration of a clock signal supply mechanism.

As shown in FIG. 2, in the programmable logic circuit device 10, a clock line 18 is arranged in a tree shape in order to supply a clock signal to each logic cell 12. The tree-shaped clock line 18 includes a clock line 18A connected to each logic cell 12 in one area 30A obtained by dividing the circuit forming area 30 on the programmable logic circuit device 10 into two parts, and a clock line 18A in the other area 30B. Clock line 18B connected to each logic cell 12
It is composed of

In the present embodiment, the areas 30A, 30A
The circuit function is reconfigured for each B. That is, the regions 30A and 30B correspond to “a plurality of regions in which circuit functions can be reconfigured” of the present invention,
A and 18B correspond to "a plurality of clock lines" (see claim 2).

In the present embodiment, the clock signal is externally supplied to the programmable logic circuit device 10 by a single system (a plurality of systems may be provided). Is entered. The output of the clock pad 20 is a PLL (Phase Lo
ck Loop) circuit 22, and the output of the PLL circuit 22 is branched into two.

One of the branches is a clock control circuit 24A.
Is connected to the clock buffer 26A, and the other is connected to the clock buffer 2A via the clock control circuit 24B.
6B. Thus, an external clock signal is supplied to the clock buffers 26A and 26B.

The clock line 18A is connected to the clock buffer 26A.
The clock signal output from A is supplied to each logic cell 12 in the area 30A. The clock line 18B is connected to the clock buffer 26B,
The clock signal output from the clock buffer 26B is supplied to each logic cell 12 in the area 30B.

The clock control circuit 24 relays the output of the PLL circuit 22 to clock buffers 26A and 26B.
A and 24B are enable signal input terminals 28, respectively.
A, 28B.

An external clock control signal (Clk_Ctrl_A) is input to the clock control circuit 24A via an enable signal input terminal 28A. The clock control circuit 24 switches the supply of the clock signal (Clk_A) to the logic cell 12 by the clock line 18A to the enable state / stop state based on the clock control signal (Clk_Ctrl_A).

Similarly, an external clock control signal (Clk_Ctrl_B) is input to the clock control circuit 24B via an enable signal input terminal 28B, and a clock line is generated based on the clock control signal (Clk_Ctrl_B). 18B to the logic cell 12 (Clk_
The supply of B) is switched between the enable state and the stop state.

That is, the programmable logic circuit device 1
At 0, the supply of the clock signal to each logic cell 12 in the area 30A and the supply of the clock signal to each logic cell 12 in the area 30B can be controlled independently.

As described above, in the present embodiment, the clock pad 20, the PLL circuit 22, the clock control circuit 24
A, 24B, clock buffers 26A, 26B, and enable signal input terminals 28A, 28B constitute a clock signal supply stopping means of the present invention (see claim 2).

(Example of System Configuration) The programmable logic circuit device 10 having the above configuration is used, for example, incorporated in an information processing system as shown in FIG. In the information processing system 50 shown in FIG.
4 is connected to a main memory 58 composed of, for example, a DRAM via a main controller (not shown) included in the chipset 56.

The host bus 54 is connected to the chip set 5
6 is also connected to a PCI bus 60 via a host-PCI bridge (not shown) included in 6. This PCI
The programmable logic circuit device 10 is connected to the bus 60 via an interface 62. Also, PC
A hard disk drive 66 is connected to the I bus 60 via an interface 64. The hard disk drive 66 stores application programs and circuit information.

The CPU 52 includes a hard disk drive 6
6 to load the application program into the main storage memory 58 and execute it. During execution of the application program, circuit information is read out from the hard disk drive 66 as necessary, and is loaded into a configuration memory (not shown) of the programmable logic circuit device 10. And data processing is performed in the circuit (hereinafter, data processing in the programmable logic circuit device 10 is referred to as “hardware processing”).

That is, the CPU 52 controls the configuration of the programmable logic circuit device 10 and the input and output of input data and output data to and from the circuits configured on the programmable logic circuit device 10.

(Operation) Next, the operation of the first embodiment will be described. FIG. 4 shows a control routine when the programmable logic circuit device 10 is operated to perform hardware processing. This control routine is executed by the CPU 52, for example.

In the following, as shown in FIG. 5, the circuits constituting the programmable logic circuit device 10 are referred to as a "circuit a plus circuit b" circuit 70 and a "circuit a plus circuit c".
In the case where the circuit a and the area 30 are used by switching between the circuit 72 and the area 72 as shown in FIG.
The case where the circuit b or the circuit c is designed to be arranged in the region 76 in B will be described as an example.

The flow of data processing at this time is as follows. When the circuit 70 is formed on the programmable logic circuit device 10, input data is input to the circuit a, and the circuit a → the circuit b →
Processing is performed in the order of the circuit a to obtain output data from the circuit a. When the circuit 72 is configured, input data is input to the circuit a, and the circuit a → the circuit c → the circuit a To obtain output data from the circuit a.

As shown in FIG. 4, when operating the programmable logic circuit device 10, first, in step 100,
In, the information of the initial circuit is loaded into a configuration memory (not shown), the initial circuit is configured, and the initial circuit is configured on the programmable logic circuit device.

Specifically, the configuration enable signal (Config_enable) is enabled, the clock signal control signals (Clk_Ctrl_A, Clk_Ctrl_B) input to the clock control circuits 24A and 24B are stopped, and the “circuit a plus circuit b” is turned off. The circuit information is loaded into a configuration memory (not shown). This allows the programmable logic circuit device 10 to execute the function of the circuit 70 of “circuit a plus circuit b”.

Next, at step 102, the programmable logic circuit device 10
Determine if the above circuit needs to be reconfigured.

If it is necessary to reconstruct the data on the way, the process proceeds to step 104. Also in this example, when switching from the circuit 70 to the circuit 72, it is necessary to reconfigure.
Go to 04.

In step 104, input of input data to the programmable logic circuit device 10 is started (hardware processing starts). Specifically, the configuration enable signal (Config_enable) is disabled, the clock signal control signals (Clk_Ctrl_A, Clk_Ctrl_B) to the clock control circuits 24A and 24B are enabled, and input data is input to the programmable logic circuit device 10.

Thereafter, the programmable logic circuit device 10
When the processing in the circuit to be reconfigured among the circuits configured above is completed (Yes in step 106), the process proceeds to step 108. In step 108, the circuit information is reloaded only in the region (partial circuit) to be reconfigured, thereby performing a partial configuration to partially reconfigure the circuit configuration on the programmable logic circuit device 10.

Specifically, the circuit b for the last data processed in the circuit 70 of “circuit a plus circuit b”
Is completed, the process proceeds to step 108, where the configuration enable signal (Config_enable)
Is enabled, and the clock signal control signal (Clk_Ctrl_B) to the clock control circuit 24B is stopped.
Thereby, the logic cell 12 by the clock line 18B is
The supply of the clock signal (Clk_B) to is stopped.

When the configuration enable signal is enabled, the circuit information for reconfiguration can be transmitted from the outside, and the circuit information of the circuit c is stored in the address of the configuration memory (not shown) corresponding to the area 30B. Loaded. Thereby, the area 30B
The circuit c is configured in the programmable logic circuit device 1
At 0, the function of “circuit a plus circuit c”, that is, the function of the circuit 72 can be executed.

During this reconfiguration process, the clock signal control signal (Clk_Ctrl_A) to the clock control circuit 24A remains enabled. Therefore, the supply of the clock signal (Clk_A) to each logic cell 12 in the area 30A by the clock line 18A is continued, and the circuit a is operable even during the reconfiguration of the circuit.

When the reconfiguration of the circuit is completed, the configuration enable signal (Config_enable) is disabled, and the clock control signal (Clk_Ctrl_B) to the clock control circuit 24B is returned to the enabled state.

Next, at step 110, it is determined whether or not a circuit to be reconfigured remains. If there is a circuit to be reconfigured, the process returns to step 106 for the next reconfiguration. In this example, since the reconstruction is performed only once, it is determined that all necessary reconstructions have been completed (step 110).
Negative determination).

All necessary reconfigurations have been completed (step 1
10), the programmable logic circuit device 10
All the input data to the input is completed (step 11).
2) When the output of the result (output data) ends (step 114), the process ends.

On the other hand, if it is not necessary to perform the reconfiguration on the way, the flow advances to step 116 to start inputting input data to the programmable logic circuit device (start of hardware processing). Thereafter, the input of all the input data is completed (step 112), and when the output of the result (output data) is completed (step 114), the processing is terminated.

Next, an example of the above operation will be specifically described with reference to the timing chart of FIG.

The programmable logic circuit device 10 has a “circuit
When the “a plus circuit b” circuit is configured, first, the input data D10 is input to the circuit a (t1), and after four cycles (t5),
The processing result D11 appears in the input register of the circuit b. In response, the processing of D11 is performed in the next circuit b.

While the circuit b is performing the processing of D11,
The next input data D20 is input to the circuit a (t6). The processing in the circuit b ends in two cycles, and D12 appears in the output register of the circuit b (t7).

At the same time (t7), the configuration enable signal (Config_enable) changes to the enable state, and the clock control signal (Clk_Ctrl_B) to the clock control circuit 24B changes to the stop state.

The configuration of the circuit c is completed in two cycles, and the configuration enable signal (Config_enable) and the clock control signal (Clk_Ctrl_B) to the clock control circuit 24B return to the original state (t9).

During this period (t7 to t9), the clock signal (Clk_B) to each logic cell 12 in the area 30B is stopped, but the clock signal (Clk_A) to each logic cell 12 in the area 30A operates. ing.

As a result, in the circuit a, the processing of the input D20 can be continuously performed, and the output result D21 appears in the input register of the circuit c (t10). Further, the processing of the value D12 of the output register of the circuit b is also performed, and D13 is output to the output register of the circuit a after four cycles (t1).
1).

In the circuit c newly formed on the programmable logic circuit device 10, the process is performed on the value D21 of the input register of the circuit c (t10), and after two cycles,
The result D22 is output to the output register of the circuit c (t12).
During the period (t10 to t12) until D22 is output, the output register of the circuit c is in an undefined state.

When D22 is output to the output register of the circuit c, the processing for this D22 is started in the circuit a in the same manner as in the case of D12, and D23 is output to the output register of the circuit a after four cycles ( t16).

As described above, in the first embodiment, the tree-shaped clock line 18 circulated on the programmable logic circuit device 10 is connected to the clock line 18A that supplies a clock signal to each logic cell 12 in the area 30A. , And a clock line 18B for supplying a clock signal to each logic cell 12 in the region 30B, so that the supply of the clock signal can be controlled independently in the region 30A and the region 30B. ing.

Thus, when reconfiguring a circuit configured in one of the areas 30A and 30B, the supply of the clock signal can be stopped only to the reconfigured area. The supply of the clock signal to the other area can be continued, and the processing in the circuit configured in the other area can be continued.

In the above description, the clock line 18 is connected to 2
Although the case of dividing into systems has been described, the present invention can be similarly applied to a case of three or more systems.

(Second Embodiment) Next, a second embodiment of the present invention will be described. Note that the schematic configuration of the programmable logic circuit device according to the second embodiment is the same as that of the first embodiment (see FIG. 1), and the description of the schematic configuration is omitted here, and the clock signal supply mechanism is omitted. I will explain only.

FIG. 8 shows a detailed configuration of the clock signal supply mechanism in the programmable logic circuit device 80 according to the second embodiment. FIG. 8 shows the programmable logic circuit device 10 described in the first embodiment.
The same members as those shown in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The programmable logic circuit device 8 shown in FIG.
0, the programmable logic circuit device 80
A single clock signal is supplied to the clock pad 20 (a plurality of clock signals may be supplied), and an external clock signal is input to the clock pad 20. The output of the clock pad 20 is connected to a PLL circuit 22, and the output of the PLL circuit 22 is branched into three,
A, 24B and 24C, the clock buffer 26
A, 26B, 26C.

The clock buffers 26A, 26B, 2
6C, a tree-like clock line 18 for connecting to all the logic cells 12 on the programmable logic circuit device 80 and supplying a clock signal to each logic cell 12 is connected.

A plurality of severable points 82 are provided on the clock line 18 so that the clock line 18 can be severed at any point. This disconnectable point 82 corresponds to the switching means of the present invention (see claim 3).

The logic cells 12 to which each of the clock buffers 26A, 26B, 26C supplies a clock signal are determined by whether or not the disconnection is possible at each of the disconnectable points 82. Each of the clock buffers 26A, 26B, and 26C has a programmable (variable) drive capability based on the scale of the clock line 18 (the number of logic cells 12 that supplies a clock signal). That is, each of the clock buffers 26A, 26B, 26C corresponds to the setting means of the present invention (see claim 4).

The clock control circuits 24A, 24B, 24C for relaying the output of the PLL circuit 22 to the clock buffers 26A, 26B, 26C are connected to enable signal input terminals 28A, 28B, 28C, respectively.
The clock control circuits 24A, 24B, and 24C switch the supply of the clock signal between the enable state and the stop state based on the clock control signals input from the outside via the enable signal input terminals 28A, 28B, and 28C. Has become.

As described above, in the present embodiment, the clock pad 20, the PLL circuit 22, the clock control circuit 24
A, 24B, 24C, clock buffers 26A, 26
B, 26C, enable signal input terminals 28A, 28B,
The clock signal supply stopping means of the present invention is constituted by 28C (see claim 3).

The reason why the number of the clock buffers and the number of the clock control circuits are three each is that the linear clock line 1 is used.
This is to show an example in which 8 can be divided into three. Any number of clock buffers and clock control circuits may be used as long as they are plural.

Next, the operation of the second embodiment will be described. Hereinafter, a case will be described in which the programmable logic circuit device 80 is operated using the same example as in the first embodiment (see FIGS. 5 and 6).

At the time of layout design, the designer can change the layout of the circuits a, b, and c on the programmable logic circuit device 80 so that the functions of the circuit b and the circuit c can be switched by partial reconfiguration. To determine. For example, the layout is determined so that the circuit 90 is replaced in the area 90 and the circuit b and the circuit c are replaced in the area 92 (see FIG. 9).

According to the layout result, the circuit data for configuration, the area for dividing the clock line 18 in a tree shape,
A clock buffer 26 for driving the clock line 18 in each area and its driving capability are determined.

Before using the programmable logic circuit device 80, the cuttable point 82 is cut based on the divided data of the clock line 18. This disconnection method is the same as a well-known method used when writing a PROM or configuring a circuit of an antifuse type programmable logic circuit device (FPGA), according to an address indicating a location and bit data indicating disconnection / connection. To melt the wiring made of polysilicon or the like.

FIG. 9 shows the result of cutting the cuttable point 82. In FIG. 9, X is added to a black point indicating the severable point 82 to indicate the severable point 82 that has been cut.

As shown in FIG. 9, the clock line 1 connecting the clock buffer 26C and the logic cell 12
8 is disconnected at the disconnectable point 82 and the PLL circuit 22 is disconnected.
And the clock control circuit 24C is also disconnected. Also,
The clock line 18 connecting the clock buffer 26B and the logic cell 12 in the area 90 is also disconnected at the disconnectable point 82.

As a result, the clock line 18 is divided into two systems, and the logic cell 12 in the area 90 receives the clock signal from the clock buffer 26A, and the logic cell 12 in the area 92 receives the clock signal from the clock buffer 26B. Supplied.

In each of the regions 90 and 92, the clock line 18 is disconnected so that the clock signal is supplied only to the logic cell 12 to be used. In the clock buffer 26A, the eight logic cells 12 and the clock buffer 2 are provided.
In 6B, a clock signal is supplied to six logic cells 12. The drive capacity of each clock buffer is programmed according to the number of the logic cells 12 to which the clock signal is supplied.

As a result, the clock line 18 can be divided into the region 90 and the region 92.
As in the embodiment, the programmable logic circuit device 8
0, the programmable logic circuit device 80 is connected to the “circuit a + circuit b” circuit 70 and the “circuit a + circuit c”
The function can be switched by using the circuit 72.

As described above, in the second embodiment, the number of clock lines 18 is one at first, and the clock lines 18 can be divided according to the area of the circuit to be reconfigured at the time of circuit design. That is, the region to be reconstructed (region 9
The system of the clock line 18 can be divided into 2) and a region where the reconfiguration is unnecessary (region 90). This allows
At the time of reconfiguration, only the clock signal in the reconfiguration area can be stopped, and the same effect as in the first embodiment can be obtained. In addition, an arbitrary area on the programmable logic circuit device 80 can be set as the reconfiguration area. Yes (high degree of freedom)

In this case, the clock buffers 26A, 26B, 2
Since the scale of the clock line 18 driven by the 6C (the number of the logic cells 12 that supplies the clock signal) changes, it is preferable to set the driving capability according to the scale of the clock line 18 driven by each.

The same effect as in the second embodiment can also be obtained by preliminarily fragmenting the tree-shaped clock line 18 with a diode or the like and short-circuiting this diode based on the divided data of the clock line 18. Can be obtained.

[0091]

As described above, the present invention has an excellent effect that, when a circuit is partially reconfigured during operation, processing can be continued in areas other than the reconfiguration area.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a programmable logic circuit device according to a first embodiment.

FIG. 2 is a detailed configuration diagram of a clock signal supply mechanism of the programmable logic circuit device according to the first embodiment.

FIG. 3 is a diagram illustrating an example of an information processing system into which a programmable logic circuit device is incorporated.

FIG. 4 is a flowchart illustrating a control routine for operating the programmable logic circuit device.

FIG. 5 is a diagram illustrating an example of a circuit configuration that causes a programmable logic circuit device to function.

FIG. 6 is an example in which the circuit configuration shown in FIG. 5 is applied to the programmable logic circuit device according to the first embodiment.

FIG. 7 is a timing chart showing an example of the operation of the programmable logic circuit device.

FIG. 8 is a detailed configuration diagram of a clock signal supply mechanism of the programmable logic circuit device according to the second embodiment.

FIG. 9 is an example in which the circuit configuration shown in FIG. 5 is applied to the programmable logic circuit device according to the second embodiment.

[Explanation of symbols]

 10, 80 Programmable logic circuit device 12 Logic cell 18, 18A, 18B Clock line 24A, 24B, 24C Clock control circuit 26A, 26B, 26C Clock buffer 28A, 28B, 28C Enable signal input terminal 30A, 30B Area 70, 72 Circuit 74 , 76 area 82 Severable point 90, 92 area

Claims (4)

[Claims] 1. A method of reconfiguring a circuit function in a programmable logic circuit device capable of partially reconfiguring a circuit function, comprising: changing a clock line in a region where the reconfigured circuit function is arranged to a clock line in another region. A circuit function which is separated from a clock line, and at the time of reconfiguration, the supply of a clock signal is stopped only to a clock line in an area where the reconfigured circuit function is arranged, and the circuit function is reconfigured. Reconstruction method. 2. A programmable logic circuit comprising a large number of logic cells and divided into a plurality of regions capable of reconfiguring circuit functions, and connected to each of the plurality of regions so as to be capable of independently supplying a clock signal. A programmable logic circuit device comprising: a clock line; and clock signal supply stopping means for supplying and stopping a clock signal for each clock line. 3. A programmable logic circuit having a large number of logic cells, a clock line provided to supply a clock signal to each of the logic cells, and each of the logic cells being provided on the clock line. Switching means for switching the clock signal to one of a supply state and a stop state to divide the clock line into a plurality of clock lines; and supplying and stopping the clock signal for each clock line divided by the switching means. And a clock signal supply stopping means for performing the following. 4. The driving capability at the time of supplying a clock signal by said clock signal supply stopping means is determined according to the number of logic cells supplying said clock signal by said clock line for each clock line divided by said switching means. The programmable logic circuit according to claim 3, further comprising setting means for setting.