WO2005034353A1

WO2005034353A1 - Field programmable gate array rewrite system

Info

Publication number: WO2005034353A1
Application number: PCT/JP2003/012725
Authority: WO
Inventors: Masaki Yamamoto; Takayasu Mochida
Original assignee: Fujitsu Limited
Priority date: 2003-10-03
Filing date: 2003-10-03
Publication date: 2005-04-14
Also published as: JPWO2005034353A1; JP4156626B2

Abstract

Information on the address not used in a circuit decision RAM of a field programmable gate array is stored in a previous write address storage section and circuit decision data is stored in a novel data storage section. According to the address not used in the circuit decision RAM, a write address addition section adds a circuit decision address to the circuit decision data stored in the novel data storage section and outputs it. An address decoder makes the circuit decision RAM store the circuit decision data according to the circuit decision address.

Description

Description Field programmable gate array rewriting system

The present invention relates to a field programmable gate array rewriting system, an address management device, and a field programmable gate array rewriting method. Background art

In a field programmable gate array (hereinafter simply referred to as an FPGA), add a circuit (add function) to an unused area (unused circuit part) of the circuit determination RAM while the operation is continued. The following rewriting technologies are considered as rewriting technologies.

First, an address decoder is added to the circuit determination RAM.

Then, the circuit determination address and the circuit determination data are input into the FPGA in the FPGA operation continuation state.

Then, the address decoder stores the circuit determining data in the circuit determining RAM according to the circuit determining address.

Patent Document 1

Japanese Patent Application Laid-Open No. H10-10-233667

Patent Document 2

JP-A-64-36120

Patent Document 3

Japanese Patent Application Laid-Open No. 2000-292974

Non-patent document 1

"Programmable ■ Logic ■ Device 'Family", [on Iine], [Search August 27, 2003], Internet UR: http: // www. A Itera. GO. Jp / literature / ds / apexj .pdf> Non-patent document 2

"Configuration for APEX and FEX devices", [on Iine], [Search on August 27, 2003], Internet http: // ww. Altera, co.jp/literature / ds / dscon T _ J-P df>

In the above technology, for example, in order to rewrite a circuit in an FPGA in an operation continuation state, a user manually operates or a method equivalent to manual as shown in FIG. Determines the circuit determination address for each circuit determination data.

Then, for each circuit determination data, the user transmits the circuit determination data to the circuit determination RAM in the FPGA together with the circuit determination address.

That is, in the above-described technology, the user has only to rewrite the FPG A circuit by managing the circuit determination address manually or by a method similar to manual.

As described above, in the above technology, when rewriting a circuit for adding a function or correcting a defect in an FPGA that can be rewritten in an operation-continued state, the circuit determination data to the FPGA is transferred to the circuit determination RAM. In this case, the user determines the circuit determining address for each circuit determining data.

Therefore, the FPGA of the above technology was difficult to use.

According to the present invention, when rewriting a circuit of a field programmable gate array, even if a user does not give a circuit determination address of an unused area of the circuit determination information storage means, the circuit determination information is stored in the circuit determination information. It is an object of the present invention to provide a field programmable gate array rewriting system, an address X management device, and a field programmable gate array rewriting method which can be stored in an unused area of a storage means. . Disclosure of the invention

A rewriting system for a field programmable gate array according to the present invention is a circuit for indicating a storage area of the circuit determining information in a circuit determining information storage unit for storing circuit determining information which is information of a circuit to be generated. Dress for decision A field programmable gate array comprising a storage destination determining means for storing the circuit determining information in the circuit determining information storage means,

Storage means for storing the circuit determination information,

Address storage means for storing information of addresses not used in the circuit determination information storage means;

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and Address management means having information and additional means for outputting the circuit determination address.

Also, in the field programmable gate array rewriting system of the present invention, the address management means may include:

A control unit is provided for controlling the timing at which the circuit determining information and the circuit determining address are output from the adding unit.

Further, in the field programmable gate array rewriting system according to the present invention, the circuit determining information storage means stores the circuit determining information in a state where the operation of the field programmable gate array is continued. You.

Further, in the field programmable gate array rewriting system of the present invention, the circuit determination information may include:

The information includes information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.

A writing unit that inputs the circuit determining information and the circuit determining address output from the adding unit and outputs the circuit determining information and the circuit determining address in parallel to the field programmable gate array.

Further, in the rewriting system for a field programmable gate array according to the present invention, the address management means may include:

The circuit determining information and the circuit determining address output from the adding means are input, and the circuit determining information and the circuit determining address are multiplexed and serially multiplexed. Writing means for outputting to the field programmable gate array.

Also, in the field programmable gate array rewriting system according to the present invention, the address storage means may include:

The information of the circuit determining address added to the circuit determining information by the adding means is stored as the information of the used address.

Further, the address management device of the present invention

According to a circuit determination address indicating a storage area of the circuit determination information, in the circuit determination information storage means for storing circuit determination information which is information of a circuit to be generated, the circuit determination information is stored in the circuit determination information storage unit. An address management device connected to a field programmable gate array including storage destination determination means for storing in a circuit determination information storage means,

Storage means for storing the circuit determination information,

Address storage means for storing information on addresses not used in the circuit determination information storage means;

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and Additional means for outputting information and the circuit determination address.

Further, the address management device of the present invention

The circuit determination information includes:

Further, the address management device of the present invention

A writing means for inputting the circuit determining information and the circuit determining address output from the adding means and outputting the circuit determining information and the circuit determining address in parallel to the field-programmable gate array . Further, the address management device of the present invention

The circuit determining information and the circuit determining address output from the adding means are input, and the circuit determining information and the circuit determining address are multiplexed and serially output to the field programmable gate array. Writing means for writing.

Further, the address management device of the present invention

The address storage means,

Also, a rewriting method of the field programmable gate array of the present invention includes a storage step of storing circuit determination information for determining a circuit generated in the field programmable gate array in a storage means,

An address storing step of storing information of an address not used in the circuit determining information storing means of the field programmable gate array in the address storing means;

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and An additional step for outputting information and the circuit determination address,

A circuit determining information storage step for storing the circuit determining information in the circuit determining information storage means in accordance with a circuit determining address indicating a storage area of the circuit determining information.

Further, the rewriting method of the field programmable gate array of the present invention includes a control step of controlling a timing at which the circuit determining information and the circuit determining address are output from the additional step.

In the field programmable gate array rewriting method of the present invention, the circuit determining information storage means stores the circuit determining information in a state where the operation of the field programmable gate array is continued.

Further, in the method for rewriting a field programmable gate array according to the present invention, the circuit determining information may include: The information includes information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.

Further, the method for rewriting a field programmable gate array according to the present invention includes a writing step of making the circuit determining information and the circuit determining address output in the additional step parallel and outputting the parallel information to the field programmable gate array. Is provided.

The rewriting method of the field programmable gate array according to the present invention may further comprise a method of multiplexing the circuit determining information and the circuit determining address output in the adding step and serially outputting the multiplexed information to the field programmable gate array. Comprising steps.

Further, in the method for rewriting a field programmable gate array according to the present invention, the information of the circuit determining address added to the circuit determining information in the adding step is stored as the address of the used address. The method includes a step of storing a used address to be stored in the means.

The present invention has an address management means for adding a circuit determining address to circuit determining information such as circuit determining data and outputting the FPGA which can be rewritten in an operation continuation state.

Here, the circuit determination information is information for determining a circuit generated in the FPGA. This circuit determination information is created by the user and input to the address management means. The circuit determination information is, for example, information indicating a logical expression of a circuit generated in FPGA.

The FPGA circuit generation unit has, for example, an S-RAM and a flip-flop (hereinafter, also simply referred to as FF), and the S-RAM and the flip-flop form a circuit corresponding to the circuit determination information.

That is, a look-up table indicating an output corresponding to a predetermined input is created by S-RAM, and a predetermined delay is given by FF to form a circuit corresponding to the circuit determination information.

The circuit determining address is an address indicating an area for storing circuit determining information in the circuit determining information storage means. Then, in the present invention, the address storage means provided in the address management means stores the address information of the unused area in the circuit determination information storage means such as the circuit determination RAM in the FPGA.

Then, the adding means adds a circuit determining address to the circuit determining information to be written in the circuit determining information storing means and outputs the information to the FPGA.

Therefore, in the present invention, when a user rewrites a circuit such as adding a new circuit or modifying a new circuit to the FPGA, the user needs to determine a circuit determining address for each circuit determining information. Disappears.

That is, in the present invention, in rewriting the circuit of the FPGA, the user does not determine the address of the unused area of the circuit determination information storage means, but the circuit determination information is stored in the unused area of the circuit determination information storage means. Can be stored.

In other words, when a user rewrites a circuit, such as adding a new circuit or modifying a new circuit, to the FPGA, the unused area of the circuit determination information storage means is stored for each circuit determination information for changing the FPGA circuit. There is no need to determine the address.

Further, according to the present invention, it is possible to collectively input a plurality of pieces of circuit determination information for rewriting the FPGA circuit to the address management means.

Therefore, according to the present invention, after the user inputs the circuit determination information for changing the circuit of the FPGA to the address management means, the rewriting of the circuit of the FPGA is performed as a series of operations without the involvement of the user. It can be done by automation.

Further, in the present invention, since the address management means manages the unused addresses of the circuit determination information storage means, an additional circuit is generated in an unused area of the circuit determination information storage means while the operation of the FPGA is continued. Then, the circuit can be rewritten.

Therefore, in the present invention, when rewriting the circuit of the FPGA, even if the FPGA continues to operate, the circuit used for the operation is not overwritten and rewritten, so that the operation continuation state of the FPGA is changed. The circuit can be rewritten while maintaining it.

For example, in the present invention, it is possible to generate a replacement circuit and a switching circuit for a defective circuit in an operation continuation state of the FPGA to remedy the defective circuit. Thus, in the present invention, for example, in an exchange device or the like in which a system down is not recognized. It is possible to rewrite the FPGA circuit, such as adding functions and fixing bugs, while continuing operation.

Furthermore, in the conventional technology, a method of providing a circuit determining address and circuit determining information to a circuit determining information storage means for an FPGA that can be rewritten in an operation continuous state, that is, the circuit determining address is used. The way of writing the circuit determination information into the circuit determination information storage means was undefined.

That is, in the conventional technology, the circuit specification address and the interface specification between the circuit determination information and the circuit determination information storage unit are undefined.

On the other hand, as in the present invention, when the address management means adds the circuit determination address to the circuit determination information and outputs it, the circuit determination information storage means stores the circuit determination address and the circuit determination information. It is necessary to prepare the peripheral environment of the FPGA so that the method of writing to the FPGA can be defined.

In the present invention, since the circuit determining address and the method of writing the circuit determining information are defined, the storage destination determining means such as an address decoder stores which circuit determining information in which circuit determining address. It is possible to determine whether to store.

Therefore, in the present invention, after the user inputs the address for circuit determination and the information for circuit determination to the address management means, even if the user does not manage the operation, an address decoder or the like is automatically provided. The circuit of the FPGA having the storage destination determining means can be rewritten.

In addition, since the address management means includes control means for controlling the circuit determining address of the adding means and the output timing of the circuit determining information, the user can control the address of the circuit determining information of the circuit to be rewritten. There is no need to decide when to enter control measures.

Note that rewriting the circuit of the field programmable gate array refers to adding a new circuit to the field programmable gate array, modifying a circuit already formed on the field programmable gate array, and modifying the field programmable gate array. This includes any of the cases where the circuits already formed in the array are deleted, the case where wiring for connecting each circuit is generated, or any combination thereof. Also, field programmable gate array failures include It can include operations other than normal operations such as failure of the grammar gate array and operation delay.

In addition, adding means for adding a circuit determining address to circuit determining information and outputting the circuit determining information means that the circuit determining information and the circuit determining address of the circuit determining information are associated with each other and output. . Brief Description of Drawings

FIG. 1 is an overall schematic diagram of a first embodiment of a field programmable gate array rewriting system of the present invention;

Figure 2 is an internal block diagram of the address management unit shown in Figure 1;

FIG. 3 is a timing chart showing an example of the write timing of the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 4 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 5 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 6 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 7 is a schematic diagram of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 8 is a schematic diagram of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 9 shows the rewriting system of the field programmable gate array of the present invention. FIG. 4 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the present invention;

FIG. 10 is a table showing a sequence of a method of switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 11 is an overall schematic diagram of a second embodiment of the field programmable gate array rewriting system of the present invention;

FIG. 12 is a timing chart showing an example of the write timing of the second embodiment of the field programmable gate array rewriting system of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment of Field Programmable Gate Array Rewriting System)

A first embodiment of a field programmable gate array rewriting system according to the present invention will be described.

First, a first embodiment of a field programmable gate array rewriting system according to the present invention will be described with reference to FIG. FIG. 1 is an overall schematic diagram of a first embodiment of a field programmable gate array rewriting system according to the present invention.

As shown in FIG. 1, the field programmable gate array rewriting system of the present embodiment includes an address management unit 100 and a field programmable gate array 101.

The field programmable gate array 101 is composed of an address decoder 102, a circuit determining RAM 103, a connection net 104, and circuit generators 108, 109, 110, 1 1 1, 1 1 1, 1 1 2, 1 1 3, 1 1 4, 1 1 5. In this embodiment, the number of circuit generators is not limited to the number shown in FIG. 1, but may be another number.

The circuit determining RAM 103 stores circuit determining data 105 for generating a circuit. Store. The circuit determination data 105 stored in the circuit determination RAM I 03 is circuit data already generated in each circuit generation unit.

The circuit determination RAM 103 has a used area 106 and an unused area 107. In the used area 106 and the unused area 107, an area for storing circuit determination data is specified by an address.

In addition, the connection net 104 is formed by wiring that connects each circuit generation unit shown in FIG.

Note that each circuit generating unit shown in FIG. 1 corresponds to the address of the circuit determining RAM 103. In each of these circuit generation units, a circuit corresponding to the circuit determination data 105 stored in the circuit determination RAM 103 is generated.

For example, each circuit generation unit of FPGA 101 includes an S-RAM for generating a logic circuit and flip-flops (FF). Further, each circuit generator of FPGA 101 has an FF for switching the circuit generator to another circuit generator.

When a circuit corresponding to the circuit determination data 105 stored in the circuit determination RAM 103 is generated in each circuit generation unit, a look-up table indicating an output corresponding to a predetermined input by the S-RAM Then, a circuit corresponding to the circuit determination data is formed by giving a predetermined delay to the FF.

The look-up table formed in S—RAM is determined by the circuit determination data stored in the circuit determination RAM103.

The circuit generation unit 108 can function as, for example, a switching circuit. Further, the circuit generation unit 109 can function as, for example, a correction circuit. The switching circuit is a circuit for switching a defective circuit to a correction circuit when there is a defective circuit. A repair circuit is a circuit that can be switched in place of a circuit in which a failure has occurred.

As an example, a description will be given below assuming that a bug (fault) has occurred in the circuit generator 110 and the circuit generator 110 has become a faulty circuit.

As shown in FIG. 1, the address management unit 100 outputs a circuit determination address (FPGAADDRESS) and circuit determination data (FPGADATA). Here, the circuit determination data is information for determining a circuit generated in the circuit generation unit of the FPGA. That is, the circuit determination data is information for determining a logic circuit determined by a combination of the S-RAM lookup table and the FF of the circuit generation unit.

This circuit determination data is stored in the circuit determination RAM 103. Then, based on the circuit determination data 105 stored in the circuit determination RAM 103, a circuit corresponding to the circuit determination data is generated in the circuit generation unit.

Further, the circuit determination address is an address for indicating an area for storing circuit determination data 105 in the circuit determination RAM 103.

The circuit determining address output from the address management unit 100 is input to the address decoder 102.

The circuit determination data output from the address management unit 100 is input to the circuit determination RAM 103.

The address decoder 102 stores the circuit determination data in the address indicated by the circuit determination RAM 103 based on the input circuit determination address.

Here, in the present embodiment, the circuit determination data is the same as the circuit determination address of the circuit determination RAM 103 regardless of whether or not the operation of the FPGA 101 is continuing. Can be stored in the area.

In the conventional FPGA, if the circuit determination data is written while the operation of the FPGA is continued, the operation of the device using the FPGA may be temporarily suspended. In this embodiment, the circuit determination RAM 103 is used. Since the circuit determination data is stored in the unused area of the FPGA, the operation of the device using the FPGA is not interrupted.

Then, a circuit corresponding to the circuit determination data stored in the circuit determination RAM 103 is generated by the circuit generation unit.

Next, the address management unit 100 shown in FIG. 1 will be described in more detail with reference to FIG. FIG. 2 is an internal block diagram of the address management unit shown in FIG. As shown in FIG. 2, the address management unit writes the FPGA data interface 201, the new data storage unit 202, the previously written address storage unit 203, and It includes a write order control unit 204, a write address addition unit 205, and an FPGA write interface 206.

The circuit determination data is input to the FPGA data interface 201 in accordance with the order of rewriting of the FPGA circuit which the user intends to perform.

The FPGA data interface 201 receives circuit determination data to be output to the FPGA, and outputs the data to the new data storage unit 202.

The new data storage unit 202 stores the circuit determination data output from the FPGA data interface 201.

The write order control unit 204 notifies the write address addition unit 205 of the timing to output the circuit determination data to which the circuit determination address has been added. The write order control unit 204 determines the circuit to which the next circuit determination address is added after the circuit determination data to which the circuit determination address is added is written to the FPGA to generate the circuit. Notifying the write address addition unit 205 of the timing of writing the data for FPGA to the FPGA to generate the circuit.

Here, the write order control unit 204 counts the number of write clocks, and the circuit determination address with the circuit determination address added to the write address addition unit 205. Notify when to output data for FPGA to FPGA write interface 206.

As described above, in the present embodiment, the write order control unit 204 controls the timing of writing the circuit determination data to which the circuit determination address has been added to the FPGA 101, so that the user This eliminates the need to determine the timing for inputting the determination data to the address management unit 100.

In the previously written address storage section 203, information on the address of the used area of the circuit determination RAM in the FPGA used up to the previous rewrite and the information of the unused area of the circuit determination RAM in the FPGA are used. Stores dress information.

The write address adding unit 205 obtains the address of the unused area of the circuit determination RAM from the previous write address storage unit 203. In the write address adding section 205, the address of the unused area of the circuit determination RAM acquired from the previous write address storage section 203 becomes the circuit determination address. The write address adding unit 205 stores the circuit determination data obtained from the new data storage unit 202 and the circuit determination address of the unused area obtained from the previous write address storage unit 203. Are output to the FPGA write interface 206 in accordance with the order in which the circuit determination data is input to the FPGA data interface 201 and the timing notified from the write order control unit 204. That is, the write address adding unit 205 adds the circuit determination address of the unused area previously obtained from the previous write address storage unit 203 to the circuit determination data obtained from the new data storage unit 202. Is added and output.

In the previous write address storage section 203, for the next write, the address of the circuit determining RAM used this time is stored as the address of the use area of the circuit determining RAM in the FPGA.

In the FPGA write interface 206, the circuit determining address and the circuit determining data are output to the circuit determining RAM in the FPGA in the order output from the write address adding section 205.

(Interface between the address management unit and the field programmable gate array)

Next, an interface between the address management unit and the field programmable gate array in the first embodiment of the field programmable gate array rewriting system according to the present invention will be described with reference to FIGS. explain. FIG. 3 is a timing chart showing an example of the write timing of the first embodiment of the field programmable gate array rewriting system of the present invention. As shown in FIG. 1, from the address management unit 100, an address for circuit determination and data for circuit determination are multiplexed and output serially.

The operation of multiplexing the circuit determination address and the circuit determination data and serially outputting them is performed by the FPGA write interface 206 shown in FIG.

In an FPGA that can be rewritten in an operation-continued state, circuit decision data such as additional circuits and correction circuits are written to the circuit decision RAM so that the address decoder can distinguish between the circuit decision address and the circuit decision data. Data to the FPGA is there.

Therefore, in this embodiment, as shown in FIGS. 2 and 3, the FPGA write interface 206 outputs the circuit determination address and the circuit determination data 303 to the FPGA 101 in serial. I do.

The FPGA write interface 206 writes all of the circuit determination address and the circuit determination data 303 to the FPGA 101 in synchronization with the write clock 302.

The FPGA write interface 206 inputs the write start enable 301 to the FPGA 101 and then outputs the circuit determination address and the circuit determination data 303 to the FPGA. Do.

If the circuit determination address and circuit determination data 303 are serial inputs, the FPGA write interface 206 outputs the first bit of the circuit determination address to the FPGA 101 at the rising edge of the clock. .

If all bits of the first circuit determination address have not been output to the FPGA 101, the FPGA write interface 206 determines the first circuit at the next rising edge of the clock. The remaining bits of the address are output to the FPGA 101.

After the output of all the bits of the first circuit determination address is completed, the FPGA write interface 206 similarly outputs the circuit determination data of the first circuit determination address at every rising edge of the clock. To the FPGA 101.

Then, when the FPGA write interface 206 finishes outputting the final circuit determination address and circuit determination data, it stops the write clock 302 and ends the write.

(How to activate the correction circuit)

Next, the operation of the field programmable gate array rewriting system according to the present embodiment when a defective circuit is generated in the field programmable gate array and the defective circuit is replaced with a correction circuit will be described below.

In the case of an FPGA that can be rewritten in a continuous operation state, in order to activate the correction circuit, It is necessary to switch the defective circuit to the corrected circuit when the operation of the defective circuit coincides with the operation of the corrected circuit.

However, the operation of the faulty circuit does not match the operation of the repair circuit due to the fault.

A method for finding and switching between timings at which the operation of the defective circuit and the operation of the correction circuit match will be described below with reference to FIGS. FIGS. 4 to 9 are schematic diagrams of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention, and FIG. 10 shows the field of the present invention. 6 is a table showing an order of a method of switching a defective circuit to a repair circuit in the first embodiment of the programmable gate array rewriting system.

Note that, in FIG. 10, the circuit generation XX of the write A d ress means the RAM A d d X X area for circuit determination in FIG. 4 to FIG.

Further, the circuit-determining RAMAddXX region shown in FIGS. 4 to 9 is a circuit generation unit corresponding to the address XX of the circuit-determining RAM103 shown in FIG.

Hereinafter, the circuit-determining RAMAddXX region and the circuit generation XX of the write Adress shown in FIG. 10 in FIGS. 4 to 9 are also simply referred to as an address XX.

In addition, as shown in FIGS. 4 to 9, connection nets are formed between the RAMAddXX regions for circuit determination.

As shown in FIG. 4 and FIG. 5, when a failure continuation state occurs in the field programmable gate array, the selectors 402 originally present in the final output of the failure circuit 401 causing the failure are replaced with the selectors 402 originally present. For the control gate 403, a latch FF501 inactivated with respect to the other input of the control gate 403 is inserted. (Figure 10, writing order 0, 1).

The latch FF 501 is an FF provided in the defective circuit 401 from the beginning for circuit switching, separately from the FF forming the look-up table and the logic circuit by the S-RAM. As shown in FIG. 1O, in the writing order 0, the failure continues before the correction.

In addition, as shown in FIG. 10, in the write order 1, the additional information is overwritten on the current data, and the inactivated latch FF501 is added to the address 2B. As a result, as shown in FIG. 6, the inactivated latch FF501 is connected to the control gate 403 in a region corresponding to the address 2B of the circuit determination RAM103. .

Thereafter, as shown in FIG. 6, based on the input circuit determination data, the FPGA modifies the correction circuit 61 and the switching circuit 6 connected to the input of the deactivated latch FF501. 0 2 and a switching point information circuit 603 are generated.

Therefore, in this case, the circuit determination data input to the FPGA includes the correction circuit 61, the switching circuit 62 connected to the input of the inactivated latch FF501, and the switching point information circuit 6. 0 3 is generated.

That is, as shown in FIG. 10, first, the address information is switched to the address 1A, and the point information circuit 603 is generated (write order 2).

The area of the address 1A where the switching point information circuit 603 is generated is an area of the unused circuit generation unit.

Next, a switching circuit 602 is generated at address 2A (write order 3). The area of address 2A where the switching circuit 602 is generated is an unused area.

Next, the address 1A is connected to the address 2A (write order 4). The address 1A and the address 2A are connected, for example, by forming a wiring in an unwired area of the connection net shown in FIG.

Next, a correction circuit 601 is generated at the address 2C (write order 5). The area of the address 2C where the correction circuit 600 is generated is an unused area of the circuit generation unit.

Next, the address 1B is connected to the address 2C (write order 6). The address 1B and the address 2C are connected to each other by a wiring formed in an unwired area of the connection net shown in FIG. 6, for example. Next, the address 2C and the address 2B are connected (write order 7). The address 2C and the address 2B are connected by, for example, a wiring formed in an unwired area of the connection net shown in FIG.

Then, as shown in FIG. 7, the switching circuit 602 inputs switching point information from the switching point information circuit 603.

This switching point information is input by a user who is monitoring the operation of the FPGA.

This switching point information indicates, for example, the timing at which the operation of the malfunctioning circuit 401 and the operation of the correction circuit 601 that are periodically operating coincide with each other.

For example, as an example of the switching point information, if the switching circuit 602 counts at a constant period, the value of the defective circuit 401 and the correction circuit 601 is determined by any value of the count. Information indicating whether the operations match can be given.

Then, the switching circuit 602 outputs the coincidence signal to the deactivated latch FF501 at the timing indicated by the switching point information.

The switching circuit 602 outputs this coincidence signal to the inactivated latch FF501, so that when the operation of the defective circuit 401 coincides with the operation of the correction circuit 601, The operation switches from the defective circuit 401 to the correction circuit 601.

That is, as shown in FIG. 10, address 2A and address 2B are connected (write order 8). The address 2A and the address 2B are connected by forming a wiring in a non-wiring area.

Then, as shown in FIGS. 8 and 9, the control gate 403 is released, and as shown in FIG. 10, at the address 2B, the control gate 403, which is an AND for a selector, is opened. Perform Pu IIUp (write order 9), and then activate the deactivated latch FF501. The Pul I Up of the control gate 403 rewrites the data to the address 2B again.

Then, as shown in FIG. 9, when the switching condition is satisfied, the switching circuit 602 latches the in-line signal so that the operation is switched from the defective circuit 401 to the correction circuit 601. Output to FF501 (Fig.10, Write for circuit correction end). That is, switching is performed at a predetermined switching timing. If these series of operations are not performed by writing the circuit determination data output to the circuit determination RAM in the FPGA in the order of addresses, the operations will not switch properly. In order to write the data for circuit determination into the RAM for circuit determination in the address order, an apparatus or method such as a tool for performing a series of operations is required.

In the present embodiment, the address management unit 100 determines a circuit determination address of circuit determination data for generating circuits such as the correction circuit 600 and the switching circuit 600.

Then, in the present embodiment, the address management unit 100, together with the determined circuit determining address, stores circuit determining data for generating circuits such as the correction circuit 61 and the switching circuit 62. The data is output to the RAM 103 for circuit determination in the FPGA as data with addresses in a sequence.

For this reason, in the present embodiment, the user does not need to manage the address of the unused area in the circuit determination RAM 103.

Further, in this embodiment, an additional circuit / correction circuit is generated in an unused area of the circuit determination RAM 103, so that the operation of the FPGA is maintained even when a circuit is added or corrected. Can be.

Therefore, the present embodiment is effective when applied to a case where a function is added or a defect is corrected while the operation is continued in an exchange device or the like in which system stoppage is not recognized.

In addition, according to the present embodiment, since the circuit determining address and the circuit determining data are input serially, compared with the parallel case, the address management unit 1000 and the FPGA 101 can be connected to each other. P (The second embodiment of the field programmable gate array rewriting system)

Next, a second embodiment of the field programmable gate array rewriting system of the present invention will be described with reference to FIGS. 11 and 12. FIG. FIG. 11 is an overall schematic diagram of a second embodiment of the field programmable gate array rewriting system of the present invention. FIG. 12 is a field programmable gate array rewriting system of the present invention. 9 is a timing chart showing an example of a write timing according to the second embodiment. This embodiment is different from the first embodiment of the above-described field programmable gate rewriting system in that a circuit determining address and a circuit determining address output from the address managing unit to the circuit determining RAM are different. The point is that the data interface is a parallel twin. Other structures and operations of the present embodiment are the same as those of the above-described first embodiment, and therefore, the points different from the above-described first embodiment will be mainly described below.

As shown in FIG. 11, the system for rewriting the field programmable gate according to the present embodiment includes an address management unit 110 and a field programmable gate array 1101.

The field programmable gate array 1101 is composed of an address decoder 1102, a circuit determination RAM 1103, a connection net 1104, and a circuit generation section 1108, 110. 9, 1 1 1 0, 1 1 1 1 1, 1 1 1 2, 1 1 1 3, 1 1 1 4, 1 1 1 5. In the present embodiment, the number of circuit generators is not limited to the number shown in FIG. 11, but may be another number.

The circuit determination RAM 110 stores the circuit determination data 111.

Further, the circuit determination RAM 1103 has a used area 1106 and an unused area 1107.

In the used area 1106 and the unused area 1107 of the circuit determination RAM 111, the area for storing the circuit determination data is specified by the address.

In addition, the connection net 1104 is formed by wiring that connects the circuit generation units to each other.

In addition, the connection nets 111, 104 have circuit generators 111, 111, 111, 112, 113, 111, 114, and 111, as use areas. Is formed.

As shown in FIG. 11, the address management unit 11010 outputs a circuit determination address (FPGA ADDRESS) and circuit determination data (FPGADATA) in parallel twin.

The address for circuit determination output from the address management unit 110 is input to the address decoder 110.

The circuit determination data output from the address management unit 110 is used for circuit determination. Input to RA I 103.

The address decoder 111 stores the circuit determination data in the circuit determination RAM 110 based on the input circuit determination address.

In an FPGA that can be rewritten in an operation-continued state, the address decoder 1102 writes an additional circuit, a correction circuit, and the like to the circuit-determining RAM 1103. Must be given to FPGA 111 so that they can be distinguished and written.

The present embodiment is an embodiment in which a circuit determining address and circuit determining data are output to the field programmable gate array 111 in parallel twin.

Here, the parallel twin means that two signal lines, a signal line for a circuit determination address and a signal line for a circuit determination data, are provided between the address management unit 1101 and the FPGA 1101. Means to exist.

However, the present invention is not limited to such a case. If necessary, one or more of the signal line of the circuit determining address and the signal line of the circuit determining data may be any number of two or more. You may do it. That is, in the present invention, the circuit determining address and the circuit determining data may be output to the field programmable gate array 111 in parallel.

The output of the circuit determination address and the circuit determination data to the field programmable gate array in parallel twin is performed by the FPGA write interface 206 shown in FIG.

As shown in FIG. 12, in the present embodiment, the FPGA write interface 206 is used to write the circuit determination address 122 3 and the circuit determination data 122 4 to the FPGA 110 1. All are performed in synchronization with the write clock 122.

The FPGA write interface 206 inputs the write start enable signal 1201 to the FPGA 110, and then sets the circuit determination address to the FPGA 110. 1 '2 0 3 and data for circuit determination 1 204 are output.

When the circuit determining address and the circuit determining data are input to the FPGA 1101 in parallel as in the present embodiment, the FPGA write interface 206 receives the first write clock 122 At the rising edge, the address for circuit determination 1 203 Outputs “!” Bit with circuit decision data 1 204 to FPGA 110 1.

Also, FPGA write intuff:!: 206 is the first write clock 1

If all bits of the circuit decision address 1 203 and the circuit decision data 1 204 cannot be output to the FPGA 111 at the rising edge of 202, At the rising edge, the remaining first circuit decision address 1203 and circuit decision data 1204 bits are output to the FPGA1101.

Then, when the FPGA write interface 206 finishes outputting the final circuit determination address 1203 and the circuit determination data 1204 to the FPGA 1101, the write clock 1201 is stopped. To complete writing.

Note that, for example, in this embodiment, the operation of rewriting the defective circuit of the FPGA to the correction circuit is the same as the operation described with reference to FIGS. 4 to 10 in the first embodiment.

As described above, also in the second embodiment of the field programmable gate array rewriting system, the same effect as in the first embodiment can be obtained.

Further, in the present embodiment, since the interface between the circuit determination address and the circuit determination data output from the address management unit 110 to the circuit determination RAM 1103 is parallel, it is serial. Compared to the case where parallel is used, rewrite completion time is shorter in the case of parallel because there are more bits that can be input at one rising edge of the clock than in the case of serial. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention is effective when rewriting a circuit such as adding a function or correcting a defect to an FPGA while continuing operation in a switching device or the like in which a system stop is not recognized.

Claims

The scope of the claims

1. According to a circuit determination address indicating a storage area of the circuit determination information in a circuit determination information storage unit that stores circuit determination information that is information of a circuit to be generated, the circuit determination information. A field programmable gate array including a storage destination determining means for storing the information in the circuit determining information storing means,

Storage means for storing the circuit determination information,

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and A field programmable gate array rewriting system, comprising: address management means having information and additional means for outputting the circuit determination address.

2. The address management means is:

2. The rewriting system for a field-programmable gate array according to claim 1, further comprising control means for controlling timing at which said circuit determining information and said circuit determining address are output from said adding means.

3. The field programmable gate array according to claim 1, wherein the circuit determining information storage means stores the circuit determining information while the operation of the field programmable gate array is continued. Rewriting system.

4. The circuit determination information is:

2. The field programmable gate array rewriting system according to claim 1, including information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.

5. The address management means is:

A writing means for inputting the circuit determining information and the circuit determining address output from the adding means and outputting the circuit determining information and the circuit determining address in parallel to the field programmable gate array; Claim 1 Field programmable gate array rewriting system.

6. The address management means is:

The circuit determining information and the circuit determining address output from the adding means are input, and the circuit determining information and the circuit determining address are multiplexed and serially output to the field programmable gate array. 2. The rewriting system for a field programmable gate array according to claim 1, further comprising a writing unit that performs the writing.

7. The address storage means,

The field programmable gate array according to claim 1, wherein the information of the circuit determining address added to the circuit determining information by the adding means is stored as information of a used address. Rewriting system.

8. In the circuit determining information storing means for storing circuit determining information which is information of a circuit to be generated, the circuit determining information according to a circuit determining address indicating a storage area of the circuit determining information. An address management device connected to a field programmable gate array including a storage destination determining means for storing the information in the circuit determining information storing means,

Storage means for storing the circuit determination information,

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and An address output device for outputting information and the circuit determination address.

9. The address management device according to claim 8, further comprising control means for controlling a timing at which the circuit determination information and the circuit determination address are output from the adding means.

10. The circuit determination information includes:

9. The address management device according to claim 8, wherein the address management device includes information for adding a switching circuit and a correction circuit for relieving a defect of the field programmable gate array.

11. Input the circuit determining information and the circuit determining address output from the adding means,

9. The address management device according to claim 8, further comprising a writing unit that outputs the circuit determination information and the circuit determination address to the field programmable gate array in parallel.

1 2. Input the circuit determining information and the circuit determining address output from the adding means,

9. The address management apparatus according to claim 8, further comprising a writing unit that multiplexes the circuit determination information and the circuit determination address and serially outputs the multiplexed information to the field programmable gate array.

1 3. The address storage means,

9. The address management device according to claim 8, wherein the information of the circuit determination address added to the circuit determination information by the adding unit is stored as information of a used address.

14. A storage step of storing circuit determination information for determining a circuit to be generated in the field programmable gate array in storage means;

An address storage step of storing information of an address not used in the circuit determination information storage means of the field programmable gate array in the address storage means;

The information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and An additional step of outputting information and the circuit determining address;

Rewriting a field programmable gate array including a circuit determining information storage step for storing the circuit determining information in the circuit determining information storage means according to a circuit determining address indicating a storage area of the circuit determining information. Method

15. The method for rewriting a field programmable gate array according to claim 14, further comprising a control step of controlling timing at which said circuit determining information and said circuit determining address are output from said adding step.

16. The field programmable gate array according to claim 14, wherein the circuit determination information is stored in the circuit determination information storage means while the operation of the field programmable gate array is continued. Rewriting method.

1 7. The circuit determination information is:

15. The method for rewriting a field programmable gate array according to claim 14, further comprising information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.

18. The writing method according to claim 14, further comprising a writing step of parallelizing the circuit determination information and the circuit determination address output in the adding step and outputting the information to the field programmable gate array. How to rewrite the described field programmable gate array.

19. A writing step for multiplexing the circuit determining information and the circuit determining address output in the adding step and serially outputting the multiplexed information to the field programmable gater. How to rewrite the field programmable gate array described in the section.

20. A used address storing step of storing information of the circuit determining address added to the circuit determining information in the adding step as information of a used address in the address storing means. The method for rewriting a field-programmable gate array according to claim 14, comprising: