WO2018131065A1

WO2018131065A1 - Reconfigurable device and electronic device using same

Info

Publication number: WO2018131065A1
Application number: PCT/JP2017/000430
Authority: WO
Inventors: 健一新保; 鳥羽　忠信; 巧上薗
Original assignee: 株式会社日立製作所
Priority date: 2017-01-10
Filing date: 2017-01-10
Publication date: 2018-07-19

Abstract

This reconfigurable device is provided with: a CRAM which stores configuration data; and a plurality of circuit blocks in which respective functions are set on the basis of the configuration data stored in the CRAM. The reconfigurable device is provided with: a rewrite control unit which partially rewrites the configuration data stored in the CRAM; a read control unit which reads the configuration data stored in the CRAM; a conversion unit which converts the configuration data, which has been read by the read control unit, to circuit configuration data required at the time of configuration; and a write control unit which provides, as write data, the circuit configuration data, formed by the conversion of the conversion unit, to a config-ROM coupled to the reconfigurable device.

Description

Reconfigurable device and electronic apparatus using the same

The present invention relates to a reconfigurable device and an electronic apparatus using the same, and particularly to a partially reconfigurable device and an electronic apparatus using the same.

An FPGA (Field Programmable Gate Array) is known as a reconfigurable device. The FPGA is configured, for example, as one semiconductor device, and functions are set based on a configuration memory (hereinafter also referred to as CRAM) and configuration data (hereinafter also referred to as configuration data) stored in the CRAM. A user logic part is provided.

The CRAM is configured by a volatile memory such as SRAM, and the configuration data is stored in an electrically rewritable nonvolatile memory (hereinafter also simply referred to as a nonvolatile memory) coupled to the outside of the FPGA. For example, when the FPGA is started up such as when the power is turned on, the configuration data stored in the nonvolatile memory is read out and written into the CRAM. Thereby, the circuit block which comprises the user logic part in FPGA is comprised so that the predetermined function defined by the configuration data may be achieved. Writing circuit configuration data called configuration data (configuration data) to the CRAM in the FPGA is called configuration.

Since the CRAM is composed of a volatile memory, the configuration data stored in the CRAM is erased when, for example, a power shutdown or reset operation is performed. Therefore, it is required to execute the configuration again when the power is turned on again or reset is released. Some FPGAs have a function called dynamic partial reconfiguration (partial reconfiguration). By using this dynamic partial reconfiguration function, the configuration data stored in the CRAM can be partially changed without stopping the operation of the FPGA, and the functions of the circuit blocks in the FPGA are partially changed. It becomes possible to change to. Changing the function of the FPGA partly by dynamic partial reconfiguration may be referred to as update processing in this specification.

FPGA is used in a wide range of applications such as automobiles and IoT devices. In recent automobiles, IoT devices, and the like, the use of FPGAs having a function of dynamic partial reconfiguration is expanding in order to cope with changes in user requirements and defect correction after shipment. By using an FPGA having a function of dynamic partial reconfiguration, for example, remotely, via a network, without changing the FPGA, a partial function change corresponding to a user's demand change or defect correction is performed. Is possible.

Patent Document 1 describes a configuration in which circuit configuration data to be changed is obtained from a network by using a dynamic partial reconfiguration function, and the logic of the FPGA is partially rewritten.

JP 2010-117968 A

Patent Document 1 describes an FPGA coupled to a server device via a network. It is possible to partially change the logic circuit in the FPGA directly via the network. In Patent Document 1, when a partial change is made via a network, configuration data stored in a programmable ROM coupled to an FPGA is not updated. For this reason, when the FPGA is restarted after partially changing the logic circuit in the FPGA via the network, the logic circuit in the FPGA stores the initial configuration data stored in the programmable ROM (via the network). It is set based on the configuration data before the change). Therefore, in order to bring the logic circuit in the FPGA into a desired state, a re-update process is performed in which the configuration data for change is prepared again in the server device and the logic circuit in the FPGA is partially changed via the network. Man-hours) is required.

As a result, the re-update process for bringing the logic circuit in the FPGA into a desired state at the time of restart increases, and it becomes difficult to restart quickly.

An object of the present invention is to provide a reconfigurable device capable of suppressing an increase in re-update processing and an electronic apparatus using the reconfigurable device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

The reconfigurable device includes a first memory that stores configuration data, and a plurality of circuit blocks in which respective functions are set based on the configuration data stored in the first memory. Here, the reconfigurable device includes a rewrite control unit that partially rewrites configuration data stored in the first memory, a read control unit that reads configuration data stored in the first memory, and read control. The configuration data read by the unit is converted into circuit configuration data required at the time of configuration, and the circuit configuration data formed by the conversion by the conversion unit is coupled to the reconfigurable device. A write controller for supplying the second memory as write data is provided.

The first memory is composed of a volatile memory, and the second memory is composed of an electrically rewritable nonvolatile memory. The configuration data stored in the first memory is read, and the circuit configuration data is written in the second memory. In other words, the partially rewritten configuration data is saved in an electrically rewritable nonvolatile memory, and the configuration is performed by the saved data at the time of restart. As a result, the re-update process at the time of activation can be suppressed, and quick activation can be realized.

Among the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.

It is possible to provide a reconfigurable device capable of suppressing an increase in re-update processing and an electronic apparatus using the same.

1 is a block diagram illustrating a configuration of a reconfigurable device according to Embodiment 1 and an electronic apparatus using the same. It is a figure which shows typically the configuration data stored in the configuration ROM. 6 is a diagram schematically showing a configuration of a configuration ROM according to a second modification of the first embodiment. FIG. It is a block diagram which shows the structure of the reconfigurable device concerning Embodiment 2, and the electronic device using the same. FIG. 6 is a diagram schematically showing a configuration of a config ROM according to the second embodiment. It is a block diagram which shows the structure of the reconfigurable device concerning Embodiment 3, and the electronic apparatus using the same.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

(Embodiment 1)
<Configuration of electronic device>
FIG. 1 is a block diagram illustrating a configuration of a reconfigurable device and an electronic apparatus using the device according to the first embodiment. In the figure, APS indicates an electronic device. The electronic device APS includes a plurality of blocks in order to realize a function desired by the user, but only blocks necessary for the description are illustrated in FIG. 1 and other blocks are omitted. In the figure, reference numeral 1 denotes an FPGA constituting the electronic device APS, and reference numeral 5 denotes an electrically rewritable nonvolatile memory (nonvolatile memory) constituting the electronic device APS. Reference numeral 100 denotes a server device, and reference numeral 13 denotes a network connecting the server device 100 and the FPGA 1. The server device 100 and the network 13 may be regarded as the electronic device APS.

Since the configuration data is stored in the nonvolatile memory 5, the nonvolatile memory 5 is also referred to as a configuration ROM (Read Only Memory) 5 in this specification.

The server device 100 stores partial update data supplied to the FPGA 1 during dynamic partial reconfiguration. For example, circuit configuration data for achieving a function according to a user request and / or circuit configuration data according to a defect correction is created and stored in the server device 100. In FIG. 1, examples of partial update data stored in the server apparatus 100 are shown as 2A # 1 to 2A # n, 2B # 1 to 2B # n, and 2C # 1 to 2C # n. The partial update data stored in the server device 100 is provided to the FPGA 1 via the network 13.

Partial update data 2A # 1 to 2A # n, 2B # 1 to 2B # n, and 2C # 1 to 2C # n are partial update data of circuit blocks 2A, 2B, and 2C described later. Here, the notation method of the partial update data used in the following description will be described. The two characters before the sign # specify the circuit block, and the combination of the sign # and the subsequent number indicates the function. For example, taking the partial update data 2A # 1 as an example, this partial update data means that the circuit block 2A is specified and the function after reconfiguration is set to # 1. The same applies to other partial update data.

In FIG. 1, for each of the circuit blocks 2A, 2B, and 2C, n pieces of partial update data for changing the function after reconfiguration to # 1 to #n are stored in the server device 100.

Next, the configuration of the FPGA 1 that is a reconfigurable device will be described.

<Configuration of reconfigurable device (FPGA)>
The FPGA 1 includes a CRAM (configuration memory) 3 and a user logic unit whose functions are set based on configuration data written in the CRAM (first memory) 3. Here, the user logic unit in FIG. 1 includes a user circuit unit 2 and a common circuit unit 4, and functions in the respective circuit units are set based on configuration data written in the CRAM 3. Here, with respect to the user circuit unit 2, it is possible to change the function of the user circuit unit 2 by partially rewriting the configuration data corresponding to the user circuit unit 2. That is, the user circuit unit 2 is a rewritable area in which the function can be partially changed.

The user circuit unit 2 includes a plurality of circuit blocks. In the figure, as a representative, three circuit blocks 2A to 2C are shown. The functions of the circuit blocks 2A to 2C are determined by writing circuit configuration data corresponding to the three circuit blocks 2A to 2C to the CRAM 3.

The FPGA according to the first embodiment has a function capable of dynamically performing partial reconfiguration when the electronic device APS is operating. That is, the functions of the circuit blocks 2A to 2C can be changed by rewriting circuit configuration data corresponding to the circuit blocks 2A to 2C without stopping the FPGA 1 during operation. For example, when the function of the circuit block 2A is changed, circuit configuration data representing the changed function is created as the circuit configuration data corresponding to the circuit block 2A, and the CRAM 3 is partially rewritten. Thereby, the function of the circuit block 2A is changed. The same applies to other circuit blocks.

On the other hand, the common circuit unit 4 is a non-rewrite area in which the function is not changed by using, for example, a function of dynamic partial reconfiguration.

In order to schematically show that the functions of both the user circuit unit 2 and the common circuit unit 4 are set by the configuration data stored in the CRAM 3, in FIG. 1, the user circuit unit 2 and the common circuit unit are changed from the CRAM 3. 4, the setting signal DEF is drawn.

The common circuit unit 4 includes a frame data extraction unit 41, a CRAM read / write control unit 42, an external interface unit 43, a checksum generation unit 44, a reconfiguration data generation unit 45, a configuration ROM read / write control unit 46, a memory interface unit 47, A selector 48, a configuration data write unit 49, and a timer unit 50 are provided.

The external interface unit 43 is connected between the network 13 and the CRAM read / write control unit 42, and performs an interface between the network 13 and the CRAM read / write control unit 42. At the time of dynamic partial reconfiguration, the server apparatus 100 supplies circuit configuration data for the circuit block to be reconfigured as partial update data to the FPGA 1 via the network 13. The external interface unit 43 receives the supplied partial update data (circuit configuration data) and supplies the received partial update data to the CRAM read / write control unit 42.

The CRAM read / write control unit 42 is connected to the CRAM 3, the frame data extraction unit 41, and the timer unit 50. The CRAM read / write control unit is a circuit integrally configured so as to be able to realize a plurality of functions. That is, the circuit can be regarded as one block as shown by a solid line in FIG. 1, but a plurality of functions can be realized. In this specification, in order to facilitate understanding, functions used in the following description among a plurality of functions to be realized are represented by broken-line blocks in the CRAM read / write control unit 42 indicated by solid lines for convenience, and CRAM read A control unit (reading control unit) 42R and a CRAM write control unit (rewriting control unit) 42W are provided. The CRAM read control unit 42R is a control unit that reads data stored in the CRAM 3, and the CRAM write control unit 42W is a control unit that writes data to the CRAM 3.

The CRAM write control unit 42W supplies the partial update data supplied from the external interface unit 43 to the CRAM 3 as rewrite data CW, and executes writing. Thereby, the partial update data received by the external interface unit 43 is written into the CRAM 3 by the CRAM write control unit 42W. Although not particularly limited, the received partial update data (circuit configuration data) includes specific information for specifying a circuit block corresponding to the partial update data (circuit configuration data). Therefore, the CRAM write control unit 42W rewrites only the part specified by the specific information in the configuration data stored in the CRAM 3 with the supplied partial update data.

When the supplied partial update data has been written, the CRAM write control unit 42W issues a partial write completion notification signal CCE.

When the frame data extraction unit 41 receives the notification signal CCE, the frame data extraction unit 41 issues a CRAM read request signal CCR for requesting reading to the CRAM read control unit 42R.

When receiving the CRAM read request signal CCR, the CRAM read control unit 42R sequentially reads all the configuration data stored in the CRAM 3 as read data CR. That is, the CRAM 3 sequentially reads both the data of the portion rewritten by the partial update data and the data of the portion not rewritten as the read data CR. In other words, the configuration data read by the CRAM read control unit 42R includes the data that has been rewritten by the CRAM write control unit 42W and the data that has not been rewritten. The CRAM read control unit 42R supplies the read data CR as read data ACO to the frame data extraction unit 41.

Config data consists of multiple frames. The frame data extraction unit 41 sequentially divides and extracts frame data from the configuration data supplied as read data ACO. The extracted frame data is supplied to the reconstruction data generation unit 45. The reconfiguration data generation unit 45 adds control command information described later as header information to the supplied frame data, and adds read / write end command information indicating the end of reading or writing of configuration data as footer information. , And supplied to the checksum generation unit 44. Read / write end command information added as footer information is information indicating the end of configuration data when reading or writing configuration data.

Further, the reconfiguration data generation unit 45 converts the format of the supplied frame data into circuit configuration data according to the type of the configuration ROM 5 coupled to the FPGA 1. The circuit configuration data obtained by the conversion is supplied to the configuration ROM read / write control unit 46. Bit swap information, header information, and footer information necessary for this format conversion are determined by the type of the configuration ROM 5 and can be grasped in advance. Therefore, these pieces of information used for format conversion can be set in the reconstruction data generation unit 45 in advance. Of course, a register (not shown) may be provided in the FPGA 1, information used for format conversion may be stored in the register, and this register may be referred to when format conversion is performed. The information used for this format conversion is the control command information described above.

The checksum generation unit (check information generation unit) 44 calculates a checksum for each supplied frame data based on the frame data, and accumulates the calculated checksum, for example, to obtain a final checksum value (check information). Ask for. That is, every time frame data is supplied, the checksum value is updated, and the final checksum value is obtained by accumulation. When the CRAM read control unit 42R finishes reading the configuration data stored in the CRAM 3, the checksum value obtained by the checksum generation unit 44 becomes the final checksum value.

Since control command information and read / write end command information are added in the reconfiguration data generation unit 45, the final checksum value includes header information and footer information necessary for configuration, and includes partial reconfiguration. The checksum of the frame data related to the configured circuit block and the checksum of the frame data related to the circuit block not reconfigured are reflected. Therefore, the checksum generation unit 44 calculates a checksum value based on all the frame data after partial reconstruction.

The final checksum value calculated by the checksum generation unit 44 is added to the end of the data supplied from the reconfiguration data generation unit 45 to the configuration ROM read / write control unit 46, and the configuration ROM read / write control unit 46. Supplied to. The function of the checksum generation unit 44 may be included in the reconfiguration data generation unit 45.

The circuit configuration data is data necessary for determining the function of the circuit block as described above, and is data required when the CRAM 3 is configured. The configuration data read by the CRAM read control unit 42R is converted into circuit configuration data in a format corresponding to the type of the configuration ROM 5 by the frame data extraction unit 41 and the reconfiguration data generation unit 45. Therefore, the frame data extraction unit 41 and the reconfiguration data generation unit 45 can be regarded as constituting a conversion unit that converts the read configuration data into circuit configuration data required at the time of configuration. .

The configuration ROM read / write control unit (write control unit) 46 supplies circuit configuration data obtained by format conversion to the configuration ROM 5 as write data via the memory interface unit 47 and the selector 48, and writes to the configuration ROM 5. I do. At this time, the configuration ROM read / write control unit 46 deletes the circuit configuration data portion except the header information and the footer information in the configuration data stored in the configuration ROM 5, and uses the circuit configuration data obtained by the format conversion. Write a new one. The header information described above is, for example, information for specifying the generation time of the conventional configuration data or the type of the FPGA 1.

Also, the configuration ROM read / write control unit 46 rewrites the checksum portion in the configuration data stored in the configuration ROM 5 with the final checksum value supplied.

The selector 48 and the configuration data write unit 49 are arranged in the common circuit unit 4, but their functions are not set by the configuration data stored in the CRAM 3, but have the following functions. That is, when the power supply voltage Vd is input to the FPGA 1 or when the FPGA 1 is reset by the reset signal RST and released from the reset state, the selector 48 is connected between the configuration ROM 5 and the configuration data write unit 49. A data path is formed. Otherwise, a data path is formed between the memory interface unit 47 and the config ROM 5.

Thus, when the power supply voltage Vd is first turned on, when the power supply voltage Vd is turned on again after being shut off, or when the reset state is released, the configuration ROM 5 receives the configuration data via the data path of the selector 48. The light unit 49 is coupled. On the other hand, when the power supply voltage Vd is continuously supplied to the FPGA 1 and is not reset by the reset signal RST, that is, in the normal operation state, the memory interface unit 47 uses the configuration ROM 5 via the data path of the selector 48. Will be combined.

In the first embodiment, the CRAM 3 is configured by a volatile memory such as SRAM, and the config ROM is configured by an electrically rewritable nonvolatile memory such as a flash memory. Therefore, for example, when the power supply voltage Vd is not supplied, the configuration data stored in the CRAM 3 is erased or indefinite. Similarly, the CRAM 3 is in the erased state or indefinite state before the power supply voltage Vd is first supplied. When the reset state is entered, the CRAM 3 is in an initial state (erased state) or indefinite state.

When the power supply voltage Vd is turned on (returned on) or the reset state is released, the configuration data write unit (configuration write control unit) 49 receives configuration data from the configuration ROM 5 via the data path of the selector 48. And the read configuration data is written into the CRAM 3. As a result, when the power supply voltage Vd is turned on for the first time, when the power supply voltage Vd is turned on again, and when the reset is released, the configuration data stored in the configuration ROM 5 is written into the CRAM 3 and Each function will be set.

In the normal operation in which the power supply voltage Vd is continuously supplied, the memory interface unit 47 and the configuration ROM 5 are coupled via the data path of the selector 48. Therefore, as described above, the configuration ROM read / write control unit 46 The circuit configuration data and the checksum value are supplied as write data to the configuration ROM 5 through the data path of the memory interface unit 47 and the selector 48, and the data stored in the configuration ROM 5 is rewritten.

Further, during normal operation, for example, the circuit blocks 2A to 2C in the user circuit unit 2 access the configuration ROM read / write control unit 47, thereby allowing the memory interface unit 47 and the selector 48 to pass through the data path. The configuration ROM 5 can be accessed, and the configuration ROM 5 coupled to the FPGA 1 can be used for storing data or / and programs.

The timer unit (time management unit) 50 is not particularly limited, but is activated in response to a CRAM read request signal CCR issued by the frame data extraction unit 41 in the first embodiment. When the timer unit 50 is activated, the timer unit 50 generates an activation signal at a preset period. This activation signal is supplied to the CRAM read control unit 42R, and the CRAM read control unit 42R operates periodically in response to the activation signal. The timer unit 50 will be described in <Modification 1> and will not be described here any further.

<Operation of FPGA 1 and Electronic Device APS>
FIG. 2 is a diagram schematically showing configuration data stored in the configuration ROM 5. The configuration data shown in FIG. 2 indicates a state (initial state 5A) before the power supply voltage Vd is first turned on (power is supplied to the FPGA 1). The configuration data includes header information, user circuit unit data related to the user circuit unit 2, common circuit unit data related to the common circuit unit 4, footer information, and checksum value. On the other hand, the config ROM 5 has a predetermined address area, and the predetermined address area is divided into five address areas in the first embodiment. That is, the address area of the config ROM 5 is divided into a header area AD1, a user area AD2, a common area AD3, a footer area AD4, and a check area AD5, as shown on the left side of FIG. Here, the header information is stored in the header area AD1, the user circuit section data is stored in the user area AD2, the common circuit section data is stored in the common area AD3, the footer information is stored in the footer area AD4, and the checksum value is stored in the check area AD5. ing. The footer information stored in the footer area AD4 is a control command included in the configuration data and corresponds to an end command when writing the configuration data.

The user circuit section data has circuit configuration data corresponding to each of the circuit blocks 2A, 2B, and 2C arranged in the user circuit section 2. Similarly, the common circuit unit data is not shown in FIG. 2, but the frame data extraction unit 41, the CRAM read / write control unit 42, the external interface unit 43, the checksum generation unit 44, and the reconfiguration shown in FIG. Circuit configuration data corresponding to the data generation unit 45, the configuration ROM read / write control unit 46, the memory interface unit 47, and the timer unit 50 is included.

In FIG. 2, circuit configuration data in which each function of the circuit blocks 2A to 2C is # 0 is stored in the user area AD2. The check area AD5 stores a checksum value calculated from the user circuit portion data and the common circuit portion data.

When the configuration ROM 5 having the configuration data shown in FIG. 2 is coupled to the FPGA 1 and the power supply voltage Vd is turned on for the first time, the FPGA 1 is initialized according to the configuration data stored in the configuration ROM 5. That is, when the power supply voltage Vd is turned on, the selector 48 forms a data path between the configuration data write unit 49 and the configuration ROM 5. Thereby, the configuration data write unit 49 reads the configuration data from the configuration ROM 5 and writes it to the CRAM 3. By this writing, each of the circuit blocks 2A to 2C in the user circuit unit 2 is configured to achieve the function # 0. The common circuit unit 4 includes a frame data extraction unit 41, a CRAM read / write control unit 42, an external interface unit 43, a checksum generation unit 44, a reconfiguration data generation unit 45, a configuration ROM read / write control unit 46, and a memory interface unit. 47 and timer unit 50 are configured to be achieved.

The configuration is started by starting the writing of the configuration data in the initial state 5A to the CRAM 3, and the configuration is completed when the writing of the configuration data in the initial state 5A is completed. Although not particularly limited, the configuration data write unit 49 calculates the checksum based on the user circuit unit data and the common circuit unit data supplied from the configuration ROM 5, and the checksum value supplied from the check area AD5 of the configuration ROM 5 And check the normality of the configuration data.

When the configuration is completed, the selector 48 forms a data path between the memory interface unit 47 and the configuration ROM. As a result, the configuration ROM 5 can be accessed from the configuration ROM read / write control unit 46 via the memory interface unit 47. For example, as described above, the configuration ROM 5 can be accessed from a circuit block in the user circuit unit 2. As will be described later, the circuit configuration data stored in the CRAM 3 can be saved in the configuration ROM 5.

When the configuration based on the initial state 5A shown in FIG. 2 is completed, as shown in FIG. 1, each of the circuit blocks 2A to 2C achieves function # 0 as shown in (). It is configured as follows. In the present specification, the three circuit blocks 2A to 2C are described as an example, but the number is an example, and the present invention is not limited to this.

In the first embodiment, the user circuit unit 2 dynamically performs partial reconfiguration by partially changing the configuration data stored in the CRAM 3 without stopping the operation of the FPGA 1 during operation. It is possible. The common circuit unit 4 is not rewritten during the operation.

<< Dynamic Partial Reconfiguration Operation >>
Here, as shown in FIG. 1, a case where partial update data for dynamic partial reconfiguration is stored in the server apparatus 100 and the partial update data is managed by the server apparatus 100 will be described. When performing dynamic partial reconfiguration, the server apparatus 100 selects partial update data corresponding to a circuit block to be partially reconfigured, and supplies it to the FPGA 1 via the network 13. However, the present invention is not limited to this. For example, the update data may be supplied to the FPGA 1 without going through the network.

In the operation of the dynamic partial reconfiguration, the circuit blocks 2A and 2C are changed from the initial state 5A shown in FIG. 2, and the circuit block 2B will be described as an example in which the initial state 5A is maintained. In this case, the function of the circuit block 2A is changed from # 0 to # 1, and the function of the circuit block 2C is changed from # 0 to # 3.

In server apparatus 100, partial update data 2A # 1 for changing the function of circuit block 2A to # 1 and partial update data 2C # 3 for changing the function of circuit block 2C to # 3 are selected, and the selected partial update is performed.

Data 2A #

1 and 2C # 3 are supplied to the FPGA 1 via the network 13.

The external interface unit 43 supplies the supplied partial update data 2A # 1, 2C # 3 to the CRAM read / write control unit 42. The CRAM write control unit 42W that constitutes the CRAM read / write control unit 42 uses the partial update data 2A # 1 and 2C # 3 as circuit configuration data, and is stored in the CRAM 3 based on the specific information included therein. Of the configuration data, only the part specified by the specific information is rewritten with the supplied partial update data (rewrite data CW)

2A #

1, 2C # 3. Since the CRAM 3 is composed of a volatile memory, the partial update data 2A # 1 and 2C # 3 may be overwritten instead of rewriting.

When the rewriting with the partial update data is completed, the CRAM write control unit 42W issues a completion notification CCE. In response to this completion notification CCE, the frame data extraction unit 41 issues a CRAM read request signal CCR. The CRAM read control unit 42R starts reading from the CRAM 3 in response to the CRAM read request signal CCR. That is, the CRAM read control unit 42R sequentially reads the configuration data stored in the CRAM 3 as the read data CR. The read data CR is supplied as read data ACO from the CRAM read control unit 42R to the frame data extraction unit 41, and the frame data extracted by the frame data extraction unit 41 is supplied to the reconstruction data generation unit 45.

The reconfiguration data generation unit 45 converts the frame data sequentially supplied from the frame data extraction unit 61 according to the type of the configuration ROM 5, generates circuit configuration data, adds header information and footer information, This is supplied to the checksum generation unit 44. The checksum generation unit 44 calculates the checksum based on the data supplied from the reconfiguration data generation unit 45 until the reading of the configuration data stored in the CRAM 3 is completed, and sequentially accumulates (updates) Find the final checksum value. The final checksum value obtained is added to the end of the data supplied from the reconfiguration data generation unit 45 and supplied to the configuration ROM read / write control unit 46.

At this time, since the FPGA 1 is normally operating, the selector 48 forms a data path between the memory interface unit 47 and the configuration ROM 5. Therefore, the configuration ROM read / write control unit 46 supplies the supplied circuit configuration data as write data to the configuration ROM 5 via the memory interface unit 47 and the selector 48, and sequentially sets the user area AD2 and the common area AD3. ,rewrite. In this manner, reading of the configuration data stored in the CRAM 3, rewriting of the configuration ROM 5 to the user area AD2 and the common area AD3, and updating of the checksum value are repeatedly executed in parallel.

When the reading of the configuration data stored in the CRAM 3 is completed, the checksum generation unit 44 supplies the checksum value updated by the time when the reading is completed to the configuration ROM read / write control unit 46 as the final update value. . The configuration ROM read / write control unit 46 supplies the final update value of the supplied checksum as a checksum value to the check area AD5 of the configuration ROM 5 via the memory interface unit 47 and the selector 48, and the check area AD5. Rewrite the value of.

That is, in FIG. 2, the user area AD2 and the common area AD3 of the configuration ROM 5 are rewritten by the circuit configuration data generated by the conversion by the reconfiguration data generation unit 45, and the check area AD5 is calculated by the checksum generation unit 44. The final checksum value is overwritten. In this case, the header information and footer information stored in the header area AD1 and the footer area AD4 are maintained without being rewritten.

With the above operation, the configuration data stored in the CRAM 3 by the dynamic partial reconfiguration is saved in the configuration ROM 5. In this case, the checksum value saved in the configuration ROM 5 is also a checksum value corresponding to the configuration data after dynamic partial reconfiguration.

Here, an example is shown in which the checksum value is calculated for the data saved in the config ROM 5 by the save operation and stored in the config ROM 5, but the present invention is not limited to this. For example, instead of the checksum, data for error correction code such as CRC (Cyclic Redundancy Check) may be calculated and stored in the configuration ROM 5.

The data saved in the configuration ROM 5 by the save operation described above is the circuit configuration data for the common circuit unit 4 (common circuit unit data in FIG. 2) and the circuit configuration for the user circuit unit 2 including the partially reconfigured circuit block. Contains data. Here, when attention is paid to the circuit configuration data for the user circuit unit 2, in the user circuit unit data shown in FIG. 2, the circuit block 2A in which the function is changed to # 1 is saved in the circuit block 2A. In the block 2C, the circuit configuration data whose function is changed to # 3 is saved, and in the remaining circuit blocks (for example, 2B), the circuit configuration data in the initial state is saved.

If the configuration data of the CRAM 3 after dynamic partial reconfiguration is not saved in the configuration ROM 5, the initial state 5A shown in FIG. 2 is stored in the configuration ROM 5. Therefore, for example, when the power supply voltage Vd is cut off and then turned on again, the CRAM 3 is configured by the configuration data in the initial state 5A stored in the configuration ROM 5. In order to return to the state immediately before the power supply voltage Vd is cut off, the partial update data 2A # 1 and 2C # 3 are prepared again in the server device 100, and the partial update data 2A # is transmitted from the server device 100 via the network 13. 1 and 2C # 3 are supplied to the FPGA 1, and dynamic partial reconfiguration is required so that the CRAM 3 is configured by the partial update data. That is, re-update processing (man-hours) is required.

On the other hand, in the first embodiment, when the power supply voltage Vd is turned on again, the selector 48 forms a data path between the configuration data write unit 49 and the configuration ROM 5 and is stored in the configuration ROM 5. The saved data is supplied to the configuration data write unit 49 as configuration data. As a result, the saved configuration data is written into the CRAM 3, and the configuration is performed using the saved configuration data. As a result, when restarting, the state does not return to the initial state 5A, and it is possible to return to the state immediately before the power supply voltage Vd is cut off without performing the re-update process. That is, in the above-described example, the circuit blocks 2A and 2C return to the dynamic partial reconfiguration state (functions # 1 and # 3) without performing the re-update process, and the circuit block 2B is in the initial state ( The function returns to # 0). Since it is not necessary to perform the re-update process, it is possible to quickly restart.

<Modification 1>
1, when the frame data extraction unit 41 issues a CRAM read request signal CCR, the timer unit 50 periodically generates an activation signal based on the period set in the timer unit 50. After the above save operation is performed, the timer unit 50 generates an activation signal even if dynamic partial reconfiguration is not performed.

The CRAM read control unit 42R starts operation in synchronization with the start signal of the timer unit 50. As a result, the configuration data stored in the CRAM 3 is read out and sequentially converted into circuit configuration data by the conversion unit configured by the frame data extraction unit 41 and the reconfiguration data generation unit 45, and the checksum generation unit 44. As a result, the checksum value is sequentially updated. The converted circuit configuration data and the final checksum value are supplied as write data to the configuration ROM 5 by the configuration ROM read / write control unit 46 via the memory interface unit 47 and the selector 48 and stored in the configuration ROM 5. The circuit configuration data and the checksum value are rewritten.

That is, in the first modification, the configuration data periodically stored in the CRAM 3 is saved in the configuration ROM 3 in synchronization with the start signal formed by the timer unit 50.

The config ROM 5 is configured by a flash memory as described above. For example, the stored data may be undesirably changed due to the influence of radiation or the like. According to the first modification, the configuration data stored in the CRAM 3 is supplied to the configuration ROM 3 and rewritten periodically even if dynamic partial reconfiguration is not performed. That is, the evacuation operation is performed periodically. Thereby, even if the data in the configuration memory ROM 5 changes undesirably, it is possible to store appropriate configuration data in the configuration ROM 5. As a result, even if the re-update process is not executed, it is possible to reliably return to the state before the restart at the time of restart.

<Modification 2>
FIG. 3 is a diagram schematically showing a configuration of the config ROM 5 according to the second modification of the first embodiment. In the second modification, the address area of the config ROM 5 is divided into a plurality of address areas. In FIG. 3, it is divided into three address areas 5-1, 5-2 and REG.

Here, the address area (second area) 5-1 stores the configuration data (predetermined configuration data) in the initial state 5A shown in FIG. In the address area 5-2 (first area), circuit configuration data and a checksum value supplied from the memory interface unit 47 during the above-described saving operation are stored. That is, the configuration data is saved in the address area 5-2. Each time the save operation is executed, the address area 5-2 is rewritten with the circuit configuration data and the checksum value stored in the CRAM 3. In the address area REG, for example, a history of executing the save operation is stored.

When the restart occurs, the circuit configuration data and the checksum value stored in the address area 5-2 of the configuration ROM 5 are supplied to the configuration data write unit 49 via the selector 48. Although not particularly limited, the configuration data write unit 49 calculates a checksum value from the supplied circuit configuration data, and compares it with the checksum value supplied from the address area 5-2.

As a result of this comparison, if the checksum values match, the configuration data write unit 49 writes the supplied circuit configuration data to the CRAM 3 as configuration data. In other words, the configuration is performed by the data stored in the address area 5-2. On the other hand, if the checksum values do not match, the configuration data write unit 49 writes the data in the initial state 5A stored in the address area 5-1 of the configuration ROM 5 to the CRAM 3 as configuration data. That is, the configuration is performed in the initial state 5A stored in the address area 5-1.

This makes it possible to prevent the user circuit unit 2 and / or the common circuit unit 4 from becoming inoperable after restarting. In this case, by grasping the history stored in the address area REG, it is possible to grasp the circuit block reconfigured by the dynamic partial reconfiguration and the function after the change until immediately before the restart. .

If the data used for error correction is stored in the address area 5-2 instead of the checksum, the initial state 5A stored in the address area 5-1 is used when correction is impossible. You only need to execute the configuration.

Here, an example is shown in which the configuration data write unit 49 calculates the checksum value based on the circuit configuration data from the address area 5-2 and performs comparison, but the configuration is not limited to this. For example, a processor may be provided inside or outside of the FPGA 1, and the checksum may be calculated and compared by this processor.

(Embodiment 2)
FIG. 4 is a block diagram showing a configuration of a reconfigurable device according to the second embodiment and an electronic apparatus using the reconfigurable device. 4 is similar to FIG. 1, and the user circuit unit 2, the CRAM 3, the network 13, and the server device 100 are the same as those in FIG. Similarly, in the common circuit unit 6, the frame data extraction unit 61, the checksum generation unit 64, and the reconfiguration data generation unit 65 are the same as the frame data extraction unit 41, the checksum generation unit 44, and the reconfiguration data generation shown in FIG. Since it is the same as the unit 45, the description is omitted.

The external interface unit 63 is similar to the external interface unit 43 of FIG. The external interface unit 43 shown in FIG. 1 is connected between the network 13 and the CRAM read / write control unit 42, but the external interface unit 63 is also connected between the processor 68 and the CRAM read / write control unit 62. It is connected. The external interface unit 63 is also connected to a config ROM read / write control unit 66. The external interface unit 63 supplies update data from the network 13 or an instruction from the processor 68 to the CRAM read / write control unit 62 or the configuration ROM read / write control unit 66. In accordance with this, the configuration ROM read / write control unit 66 is changed from the configuration ROM read / write control unit 46 of FIG.

The CRAM read / write control unit 62 is similar to the CRAM read / write control unit 42 of FIG. 1, but the CRAM read / write control unit 62 is further coupled to the memory interface unit 67. In accordance with this, the memory interface unit 67 is changed from the memory interface unit 47 shown in FIG.

Also in the second embodiment, as in the first embodiment, the server apparatus 100 also includes a plurality of partial update data 2A # 1 to 2A # n, 2B # 1 to 2B # n, 2C # 1 to 2C # n. Is stored.

In the second embodiment, the configuration ROM 7 stores (registers) configuration data 7B at the time of shipment, configuration data in the initial state 7A, and a plurality of update data. FIG. 5 is a diagram schematically showing the configuration of the config ROM according to the second embodiment. The address area of the config ROM 7 is divided into three address areas. That is, an address area for storing the configuration data 7B at the time of shipment (hereinafter also referred to as an initial state area), an address area for storing the initial state 7A (hereinafter also referred to as an entire update area or a fourth area), and a partial reconfiguration An address area for storing partial update data (hereinafter also referred to as a partial update area or a third area) is provided. In FIG. 5, the initial state area is arranged on the lowermost side, and stores the configuration data 7B at the time of shipment. The entire update area is arranged above the initial state area, and the initial state 7A is stored here. Further, a partial update area for storing partial update data is arranged above the entire update area. In the example of FIG. 5, a plurality of partial update data 2A # 1,

2A #

2,

2B #

1,

2B #

2,

2C #

1, 2C # 2 are stored in the partial update area.

The initial state 7A stored in the entire update area includes header information, user circuit portion data, common circuit portion data, footer information, and a checksum, similar to the initial state 5A shown in FIG. Similarly to the initial state 7A, the configuration data 7B at the time of shipment also includes header information, user circuit unit data, common circuit unit data, footer information, and a checksum. Unlike the initial state 7A, the configuration data 7B at the time of shipment is created, for example, when the FPGA 1 is shipped, and is stored in the initial state area. The data stored in the entire update area is updated by the save operation, but the data in the initial state area is not updated.

When the power supply voltage Vd is input to the FPGA 1, the CRAM 3 is configured based on the initial state 7A, and the function defined by the initial state 7A is achieved by the FPGA 1.

In the second embodiment, the dynamic partial reconfiguration can be realized by two kinds of methods. That is, in the first partial reconfiguration method, as in the first embodiment, the server apparatus 100 selects partial update data to be subjected to dynamic partial reconfiguration and supplies it to the FPGA 1 via the network 13. Is the method. In this case, the external interface unit 63 supplies the supplied partial update data to the CRAM read / write control unit 62, and the configuration data in the CRAM 3 is partially rewritten, whereby dynamic partial reconfiguration is performed.

The second partial reconfiguration method is a method in which configuration data in the CRAM 3 is partially changed by partial update data stored in the partial update area of the configuration ROM 7. In this case, the processor 67 forms selection information for selecting desired partial update data, and the formed selection information is sent to the memory interface unit 67 via the external interface unit 63 and the configuration ROM read / write control unit 66. Given. The memory interface unit 67 selects partial update data (for example,

2A #

1, 2B # 2) corresponding to the selection information from the partial update data stored in the partial update area of the configuration ROM 7, and selects the selected partial update data 2A. # 1 and # 2B2 are supplied to the CRAM read / write control unit 62. The CRAM read / write control unit 62 rewrites the part corresponding to the partial update data 2A # 1, 2B # 2 in the configuration data stored in the CRAM 3 with the partial update data 2A # 1, 2B # 2.

As described in the first embodiment, the function of the user circuit unit 2 can be changed by changing the configuration data stored in the CRAM 3. When the initial state 7A is the state shown in FIG. 2, when the dynamic partial reconfiguration is performed by the second method described above, the function of the circuit blocks 2A and 2B is changed from # 0 to # 1 and # 2. Will be.

The configuration data in the CRAM 3 changed by the first partial reconstruction method and the second partial reconstruction method described above is supplied to the entire update area in the configuration ROM 7 in the same manner as described in the first embodiment. The user circuit unit data, common circuit unit data, and checksum stored in the entire update area are rewritten and saved. At the time of restart, the circuit configuration data saved in the entire update area is written as configuration data into the CRAM 3 and configuration is performed. Therefore, it is possible to return to the state immediately before the restart without performing the re-update process, and a quick restart is possible.

In the second embodiment, dynamic partial reconfiguration can be performed using partial update data stored in the configuration ROM 7 even if the FPGA is not coupled to the network 13. Further, when coupled to a network, dynamic partial reconfiguration using the latest partial update data is possible.

When the FPGA 1 is coupled to the network 13, the partial update data stored in the server device 100 is transferred to the configuration ROM 7 via the external interface unit 63, the configuration ROM read / write control unit 66 and the memory interface unit 67. The partial update area may be written. Thereby, the partial update data stored in the config ROM 7 can be increased.

Further, FIG. 4 shows the case where the processor 68 is provided outside the FPGA 1, but the processor 68 may be built in the FPGA 1. In FIG. 4, the power supply voltage Vd, the reset signal RST, the selector 48, and the configuration data write unit 49 shown in FIG. 1 are omitted in order to avoid complication of the drawing.

In the second embodiment, when the configuration associated with the restart and the configuration associated with the second partial reconfiguration method are regarded as a kind of configuration, the entire reconfiguration (restart) is performed. The circuit configuration data stored in the entire update area of the configuration ROM 7 is used at the time of configuration. When performing partial reconfiguration, the circuit configuration data stored in the partial update area is used at the time of configuration. It can be understood that In view of this, the CRAM 3 is configured by configuration data corresponding to the circuit configuration data stored in the entire update area or configuration data corresponding to the circuit configuration data stored in the partial update area. Become.

When configuration is executed based on the circuit configuration data stored in the entire update area, the checksum value is checked as described in <Modification 2> of the first embodiment, and the checksum value is checked. If they do not match, the configuration is executed using the configuration data 7B at the time of shipment stored in the initial state area. Similarly, when the configuration is executed based on the circuit configuration data stored in the partial update area, a check using the checksum value is performed as described in <Modification 2> of the first embodiment. If the checksum values do not match, the configuration is executed using the shipping configuration data 7B stored in the initial state area. This makes it possible to ensure that the FPGA 1 operates.

(Embodiment 3)
FIG. 6 is a block diagram showing a configuration of a reconfigurable device according to the third embodiment and an electronic apparatus using the reconfigurable device. In the third embodiment, the electronic device APS includes a plurality of FPGAs and a configuration ROM 5. In the figure, a plurality of FPGAs 1-0 to 1-n are connected to the network 13 in series. The server device 100 and the network 13 are the same as those in FIG.

Since the FPGA 1-0 to FPGA 1-n have the same configuration, the FPGA 1-0 will be described as a representative here. The FPGA 1-0 includes a user circuit unit 2, a CRAM 3, and a common circuit unit 8 as in FIG. Here, the user circuit unit 2 and the CRAM 3 are the same as those in FIG.

The common circuit unit 8 includes an external interface unit 83, a CRAM read / write control unit 82, a frame data extraction unit 81, a checksum generation unit 84, a partial reconfiguration data generation unit 85, and a configuration ROM read / write control unit 86. Here, the CRAM read / write control unit 82, the frame data extraction unit 81, the checksum generation unit 84, the partial reconfiguration data generation unit 85, and the configuration ROM read / write control unit 86 are the CRAM read / write control unit 42 shown in FIG. Since it is the same as the frame data extraction unit 41, the checksum generation unit 44, the partial reconfiguration data generation unit 45, and the configuration ROM read / write control unit 46, description thereof will be omitted.

In the third embodiment, the output of the configuration ROM read / write control 86 is supplied to the external interface unit (interface unit) 83. The external interface unit 83 supplies the partial update data supplied to the terminal 83a to the CRAM read / write control unit 82 during dynamic partial reconfiguration. Thereby, as described in the first embodiment, a part of the configuration data stored in the CRAM 3 is rewritten by the partial update data supplied to the terminal 83a, and the function of the FPGA 1-0 is partially changed. Is done.

In the save operation, the external interface unit 83 outputs the circuit configuration data and the checksum value output from the configuration ROM read / write control unit 86 from the terminal 83b. Therefore, during the save operation, the circuit configuration data and the checksum value output from the configuration ROM read / write control unit 86 are output to the outside of the FPGA 1-0. On the other hand, at the time of start-up (including the time of restart), the external interface unit 83 supplies external data supplied to the terminal 83b to the CRAM read / write control unit 82 and the terminal 83a. The CRAM read / write control unit 82 writes the supplied external data to the CRAM 3 and executes configuration.

The terminal 83a of the FPGA 1-0 (second reconfigurable device) is connected to the network 13, and the terminal 83b is connected to the terminal 83a of the subsequent FPGA 1-1 (first reconfigurable device). The terminal 83b of the rear stage FPGA 1-1 is connected to a terminal 83a of the rear stage FPGA 1-2 (not shown). In the same manner, the terminal 83b is connected to the terminal 83a of the subsequent FPGA. The terminal 83b of the final stage FPGA 1-n is connected to the config ROM 5.

Thus, when dynamic partial reconfiguration is performed in the first-stage FPGA 1-0, the save operation is performed as in the first embodiment. In the third embodiment, the circuit configuration data and the checksum value generated by the save operation are supplied to the subsequent FPGA 1-1. In the subsequent FPGA 1-1, the CRAM read / write control unit 82 writes to the CRAM 3 based on the supplied circuit configuration data, and the configuration is executed. Also in the FPGA 1-1, when the writing to the CRAM 3 is completed, the save operation is executed, and the circuit configuration data and the checksum value generated by the save operation are supplied to the subsequent FPGA 1-2 (not shown). become. In this way, the CRAMs 3 in the FPGAs 1-1 to 1-n are sequentially configured, and the FPGAs 1-1 to 1-n are in a state where the FPGA 1-0 is copied. That is, the configuration data stored in the CRAM 3 in the FPGA at the predetermined stage is directly written into the CRAM 3 in the FPGA at the subsequent stage.

Further, the circuit configuration data and the checksum value output from the FPGA-n at the final stage are supplied to the configuration ROM 5 as in the first embodiment, and the configuration ROM 5 is rewritten.

At the time of restart, the circuit configuration data and checksum value saved in the configuration ROM 5 are transferred to the CRAM 3 by the CRAM read / write control unit 82 in the FPGA 1-n via the external interface 83 in the FPGA 1-n at the final stage. Written and CRAM 3 in FGPA1-n is configured. Also. Since the circuit configuration data and the checksum value are output from the terminal 83a of the external interface unit 83 in the final-stage FPGA 1-n to the terminal 83b of the previous-stage FPGA, the supplied circuit-configuration data is also transferred to the previous-stage FPGA. Configuration will be executed based on this. That is, at the time of start-up (restart-up), the configuration data stored in the config ROM 5 is supplied from the subsequent stage to the previous stage, and the configuration of the CRAM 3 is executed in each FPGA. In other words, the latest configuration data before activation (reactivation) is supplied from the adjacently connected FPGA at the time of activation (reactivation), whereby the CRAM 3 in the FPGA is configured. Become. Therefore, it is possible to acquire a plurality of FPGAs configured with the latest configuration data without performing re-update processing. Since the re-update process is not required, the restart can be performed quickly.

Although an example has been described in which the external interface unit 83 supplies the circuit configuration data supplied to the terminal 83b to the terminal 83a at the time of restart, the circuit configuration generated by the configuration ROM read / write control unit 86 in the save operation after the restart The data may be supplied from the external interface unit 83 to the terminal b3b of the FPGA connected adjacently via the terminal 83a.

In FIG. 6, the power supply voltage Vdd and the reset signal RST are omitted in order to avoid the complexity of the drawing.

Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, Embodiments 1 to 3 may be combined with each other.

1, 1-0 to 1-n FPGA
2 User circuit section 3

Configuration memory

4, 6, 8 Common circuit section 5, 7 Config ROM
13 Network 100 Server device APS Electronic device

Claims

A reconfigurable device comprising: a first memory that stores configuration data; and a plurality of circuit blocks in which respective functions are set based on the configuration data stored in the first memory,
The reconfigurable device is:
A rewrite control unit for partially rewriting configuration data stored in the first memory;
A read control unit for reading configuration data stored in the first memory;
A conversion unit that converts the configuration data read by the read control unit into circuit configuration data required at the time of configuration;
A write control unit for supplying circuit configuration data formed by the conversion by the conversion unit as write data to a second memory coupled to the reconfigurable device;
A reconfigurable device comprising:
The reconfigurable device of claim 1, wherein
The reconfigurable device, wherein the configuration data read by the read control unit includes data of a portion rewritten by the rewrite control unit and data of a portion not rewritten.
The reconfigurable device of claim 2, wherein
The reconfigurable device includes a check information generation unit that generates check information based on configuration data read by the read control unit,
The reconfigurable device, wherein the write data supplied from the write control unit to the second memory includes the circuit configuration data and check information generated by the check information generation unit.
The reconfigurable device according to any one of claims 1 to 3,
The reconfigurable device includes a time management unit that generates a periodic activation signal;
In synchronization with the activation signal generated by the time management unit, the read control unit reads configuration data from the first memory, the conversion unit converts configuration data into circuit configuration data, and the write control unit A reconfigurable device that supplies converted circuit configuration data to the second memory as write data.
The reconfigurable device of claim 2, wherein
In the configuration, the reconfigurable device is supplied with configuration data including circuit information data stored in the second memory, and writes the supplied configuration data to the first memory. A reconfigurable device comprising a write controller.
The reconfigurable device of claim 5, wherein
The reconfigurable device, wherein the first memory includes a volatile memory to which configuration data is written, and the second memory includes an electrically rewritable nonvolatile memory.
An electronic device comprising an electrically rewritable nonvolatile memory and a first reconfigurable device coupled to the electrically rewritable nonvolatile memory,
The first reconfigurable device is
Volatile memory for storing configuration data;
A plurality of circuit blocks each function is set based on the configuration data stored in the volatile memory;
A rewrite control unit for partially rewriting configuration data stored in the volatile memory;
A read control unit for reading configuration data stored in the volatile memory;
A conversion unit that converts the configuration data read by the read control unit into circuit configuration data required at the time of configuration;
A write control unit for supplying circuit configuration data formed by the conversion by the conversion unit as write data to the electrically rewritable nonvolatile memory;
An electronic device comprising:
The electronic device according to claim 7.
The configuration data read by the read control unit includes electronic data that has been rewritten by the rewrite control unit and data that has not been rewritten.
The electronic device according to claim 8.
The first reconfigurable device includes a check information generation unit that generates check information based on configuration data read by the read control unit, and the electrically rewritable nonvolatile memory from the write control unit The write data supplied to the memory includes the circuit configuration data and the check information generated by the check information generation unit,
The electrically rewritable nonvolatile memory includes a first area for storing write data supplied from the write control unit, and a second area for storing predetermined configuration data.
In the configuration, the first reconfigurable device reads write data from the first area of the electrically rewritable nonvolatile memory, and check information obtained from circuit configuration data included in the read write data An electronic device that writes configuration data stored in a second area of the electrically rewritable non-volatile memory to the volatile memory when the check information does not match the check information included in the read write data.
The electronic device according to claim 8.
The electrically rewritable nonvolatile memory includes a third area for storing circuit configuration data corresponding to the circuit block, and a fourth area for storing write data supplied from the write control unit,
When the first reconfigurable device is configured, the configuration data corresponding to the circuit configuration data stored in the third area or the configuration data corresponding to the write data stored in the fourth area To the volatile memory,
Electronic equipment.
The electronic device according to claim 8.
The electronic device is
A second reconfigurable device coupled to the first reconfigurable device;
The second reconfigurable device is
Volatile memory for storing configuration data;
A plurality of circuit blocks each function is set based on the configuration data stored in the volatile memory;
A rewrite control unit for partially rewriting configuration data stored in the volatile memory;
A read control unit for reading configuration data stored in the second volatile memory;
A conversion unit that converts the configuration data read by the read control unit into circuit configuration data required at the time of configuration;
An interface unit that outputs circuit configuration data formed by the conversion by the conversion unit as data to be written to the volatile memory of the first reconfigurable device;
An electronic device comprising: