CN117312233B

CN117312233B - Field programmable gate array chip, construction method thereof and accelerator equipment

Info

Publication number: CN117312233B
Application number: CN202311599266.8A
Authority: CN
Inventors: 张德闪; 刘伟; 李仁刚; 卢圣才
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2024-02-23
Anticipated expiration: 2043-11-28
Also published as: CN117312233A

Abstract

The application discloses a field programmable gate array chip, a construction method thereof and accelerator equipment, and relates to the technical field of computers; the static platform component layer includes a first functional component that is related to a characteristic of the accelerator device and that has no update requirements; the first functional component is loaded from a flash memory or read-only memory chip of the accelerator device; the dynamic platform component layer comprises a second functional component which is dynamically added or updated and is related to the characteristics of the accelerator equipment, and a second processing module which is dynamically added and shared by a plurality of application programs; the second functional component and the second processing module are configured from the host; the application logic module layer comprises a first processing module which is dynamically added and related to a single application program; the first processing module is configured from the host. The field programmable gate array chip has the advantage that the flexibility of the field programmable gate array chip is improved.

Description

Field programmable gate array chip, construction method thereof and accelerator equipment

Technical Field

The present disclosure relates to the field of computer technology, and more particularly, to a field programmable gate array chip, a method for constructing the same, and an accelerator device.

Background

With the excellent characteristics of low latency, low power consumption, FPGA (field programmable gate array ) devices began to appear in data centers as accelerators for applications, such as video codec accelerators, image format conversion accelerators, and the like. However, since the development mode of the FPGA is completely different from the development mode of the conventional general-purpose processor CPU (Central Processing Unit ) oriented to the instruction set, the FPGA combines and interconnects logic resources in the FPGA chip by programming to achieve the required functions, and compared with the CPU, the FPGA has greater development difficulty and difficult debugging. In addition, cloud applications carried by the data center are dynamically changed in types and numbers, and the FPGA accelerator is required to have different application acceleration functions as required so as to realize multiplexing of resources.

In order to reduce the difficulty of developing an application accelerator based on the FPGA and promote the deployment of the FPGA accelerator in a data center, the FPGA accelerator architecture is divided into two parts, wherein one part comprises components related to platform characteristics, such as a memory controller, a PCIe module and the like, and the components are called Shell; the other part is related to the accelerated application program and comprises an application related processing module called roller. In the Shell-rotor architecture, a large number of different Shell-rotor interfaces exist due to the change of the platform requirements of the FPGA accelerator or the addition of a third-party FPGA project, which causes a great burden on the management of the FPGA accelerator equipment by a cloud data center. Therefore, in the related art, the flexibility of the accelerator device is poor, and the requirement of changing the own platform requirement or adding a third party FPGA engineering cannot be met.

Therefore, how to improve the flexibility of the accelerator apparatus is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a field programmable gate array chip, a construction method thereof and accelerator equipment, which meet the requirements of self platform requirement change or third party FPGA engineering addition and improve the flexibility of the accelerator equipment.

In order to achieve the above objective, the present application provides a field programmable gate array chip applied to an accelerator device, where the accelerator device is connected to a host, and the field programmable gate array chip includes an application logic module layer, a dynamic platform component layer, and a static platform component layer that are sequentially connected;

the static platform component layer includes a first functional component related to a characteristic of the accelerator device and having no update requirements; the first functional component is loaded from a flash memory or read-only memory chip of the accelerator device;

the dynamic platform component layer comprises a second functional component which is dynamically added or updated and is related to the characteristics of the accelerator equipment, and a second processing module which is dynamically added and shared by a plurality of application programs; the second functional component and the second processing module are configured from the host;

The application logic module layer comprises a first processing module which is dynamically added and related to a single application program; the first processing module is configured from the host.

The first functional component comprises any one or a combination of any two of a memory controller, a physical layer communication module and an input/output processing module.

The static platform assembly layer is connected with the physical interface through the physical layer communication module, and the static platform assembly layer is connected with the input/output interface through the input/output processing module.

The static platform assembly layer further comprises a static platform management module, and the static platform management module is used for communicating with the dynamic platform assembly layer to acquire information of a second functional assembly and a second processing module contained in the dynamic platform assembly layer and control information of a forwarding host end.

The dynamic platform component layer comprises a shared library and a platform functional component library, the shared library comprises a second processing module shared by a plurality of dynamically added application programs, and the platform functional component library comprises a dynamically added or updated second functional component related to the characteristics of the accelerator equipment.

The second processing module comprises any one or a combination of any two of a video decoding module, an encryption and decryption module and a compression module.

Wherein the second functional component comprises a direct memory access component.

The dynamic platform assembly layer further comprises a dynamic platform management module, and the dynamic platform management module is used for communicating with the static platform assembly layer to report information of a second functional assembly and a second processing module contained in the dynamic platform assembly layer and forward information sent to the application program logic module layer by the static platform assembly layer.

The dynamic platform assembly layer is connected with the application program logic module layer through an application interface;

the dynamic platform assembly layer is connected with the static platform assembly layer through a platform interface.

Wherein the application interface and the platform interface adopt different interface protocols.

The platform interface comprises a control channel and a data channel, wherein the control channel is used for realizing a register read-write function.

The application interface comprises any one or a combination of any two of a register read-write interface, a memory read-write interface, an interrupt interface, an abnormal error report interface and a reset interface.

And the second functional component and the second processing module contained in the dynamic platform component layer are used as equipment characteristics of the accelerator equipment and are connected in series in a linked list mode.

Wherein the device feature comprises a feature header for describing identification information of the device feature and a control status register portion comprising all control register lists and status register lists associated with the device feature.

Wherein the feature header includes any one or a combination of any of a type field, a feature version number, a linked list end flag, an offset of a feature header of a next device feature, an interface version number, an identifier;

the type field is used for describing that the equipment characteristic belongs to a functional component or a processing module; if the equipment features belong to the functional components, the interface version number is used for describing the version number of the platform interface compatible with the equipment features, and if the equipment features belong to the processing module, the interface version number is used for describing the version number of the application interface compatible with the equipment features; the linked list end mark is used for describing whether the equipment characteristic is the last equipment characteristic of the linked list; the offset of the feature header of the next device feature is used to describe the offset of the feature header of the next device feature from the feature header of the current device feature; the identifier is used to describe an identification of the device feature.

Wherein the control status register portion has a length less than or equal to an offset of a feature header of the next device feature.

In order to achieve the above object, the present application provides a method for constructing a field programmable gate array chip, which is applied to an accelerator device, where the accelerator device is connected to a host, and the method includes:

determining a first functional component related to the characteristics of the accelerator device and no update requirement exists, a second functional component related to the characteristics of the accelerator device and needing to be dynamically added or updated, a first processing module related to a single application program and needing to be dynamically added, and a second processing module shared by a plurality of application programs and needing to be dynamically added;

loading the first functional component from a flash memory or read-only memory chip of the accelerator device to a static platform component layer, configuring the second functional component and the second processing module from the host to a dynamic platform component layer, and configuring the first processing module from the host to an application logic module layer;

creating an application interface between the application logic module layer and the dynamic platform component layer and a platform interface between the dynamic platform component layer and the static platform component layer.

Wherein loading the first functional component from a flash memory or a read-only memory chip of the accelerator device to a static platform component layer, configuring the second functional component and the second processing module from the host to a dynamic platform component layer, and configuring the first processing module from the host to an application logic module layer, further comprises:

and taking a second functional component and a second processing module contained in the dynamic platform component layer as equipment characteristics of the accelerator equipment, and connecting the second functional component and the second processing module in series in a linked list mode.

Wherein the device features include a feature header and a control status register portion;

the feature header is used for describing identification information of the device feature, the feature header comprises any one or a combination of a type field, a feature version number, a linked list end mark, an offset of the feature header of the next device feature, an interface version number and an identifier, and the type field is used for describing that the device feature belongs to a functional component or a processing module; if the equipment features belong to the functional components, the interface version number is used for describing the version number of the platform interface compatible with the equipment features, and if the equipment features belong to the processing module, the interface version number is used for describing the version number of the application interface compatible with the equipment features; the linked list end mark is used for describing whether the equipment characteristic is the last equipment characteristic of the linked list; the offset of the feature header of the next device feature is used to describe the offset of the feature header of the next device feature from the feature header of the current device feature; the identifier is used for describing the identification of the device characteristics;

The control status register portion includes all of a list of control registers and a list of status registers associated with the device feature.

To achieve the above object, the present application provides a construction apparatus for a field programmable gate array chip, including:

the system comprises a determining unit, a first processing unit and a second processing unit, wherein the determining unit is used for determining a first functional component related to platform characteristics and not requiring updating, a second functional component related to platform characteristics which needs to be dynamically added or updated, a fixed first processing module related to acceleration application and a second processing module related to acceleration application which needs to be dynamically added;

a configuration unit, configured to load the first functional component from a flash memory or a read-only memory chip of the accelerator device to a static platform component layer, configure the second functional component and the second processing module from the host to a dynamic platform component layer, and configure the first processing module from the host to an application logic module layer;

and the creation unit is used for creating an application interface between the application program logic module layer and the dynamic platform assembly layer and a platform interface between the dynamic platform assembly layer and the static platform assembly layer.

Wherein, still include:

and the linked list series unit is used for taking the second functional component and the second processing module contained in the dynamic platform component layer as the equipment characteristics of the accelerator equipment and carrying out series connection in a linked list mode.

To achieve the above object, the present application provides an accelerator apparatus comprising:

the field programmable gate array chip comprises the field programmable gate array chip;

a memory for storing a computer program;

and the processor is used for realizing the steps of the method for constructing the field programmable gate array chip when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for constructing a field programmable gate array chip as described above.

According to the technical scheme, the field programmable gate array chip is applied to accelerator equipment, the accelerator equipment is connected with a host, and the field programmable gate array chip comprises an application program logic module layer, a dynamic platform assembly layer and a static platform assembly layer which are sequentially connected; the static platform component layer includes a first functional component related to a characteristic of the accelerator device and having no update requirements; the first functional component is loaded from a flash memory or read-only memory chip of the accelerator device; the dynamic platform component layer comprises a second functional component which is dynamically added or updated and is related to the characteristics of the accelerator equipment, and a second processing module which is dynamically added and shared by a plurality of application programs; the second functional component and the second processing module are configured from the host; the application logic module layer comprises a first processing module which is dynamically added and related to a single application program; the first processing module is configured from the host.

The application adds a dynamic platform assembly layer between an application program logic module layer and a static platform assembly layer of the field programmable gate array chip, wherein the dynamic platform assembly layer comprises a function assembly which is dynamically added or updated and is related to the characteristics of the accelerator equipment. Namely, on one hand, a constant area which is only related to the characteristics of the accelerator equipment, namely a static platform assembly layer is maintained so as to avoid restarting of a server caused by updating, and on the other hand, a dynamic platform assembly layer is maintained, so that the functional characteristics of the FPGA accelerator platform can be expanded according to the requirement of the accelerator equipment to change or add a third-party FPGA project, the requirement of the self platform for changing or adding the third-party FPGA project is met, and the flexibility of the field programmable logic gate array chip is improved. The application also discloses a construction method and a construction device of the field programmable gate array chip, accelerator equipment and a computer readable storage medium, and the technical effects can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

FIG. 1 is a schematic diagram of a field programmable gate array chip of the related art;

FIG. 2 is a block diagram of a field programmable gate array chip, according to an example embodiment;

FIG. 3 is a block diagram of another field programmable gate array chip shown in accordance with an exemplary embodiment;

FIG. 4 is a block diagram illustrating one device feature according to an example embodiment;

FIG. 5 is a block diagram illustrating another device feature in accordance with an exemplary embodiment;

FIG. 6 is a flowchart illustrating a method of constructing a field programmable gate array chip, according to an example embodiment;

FIG. 7 is a block diagram of an apparatus for constructing a field programmable gate array chip, according to an example embodiment;

fig. 8 is a block diagram of an accelerator apparatus according to an exemplary embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. In addition, in the embodiments of the present application, "first," "second," and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence.

In the related art, to reduce the difficulty of developing an application accelerator based on an FPGA and to advance the deployment of the FPGA accelerator in a data center, as shown in fig. 1, a field programmable gate array chip architecture is divided into two parts, wherein one part includes components related to platform characteristics, such as a memory controller, other input/output interfaces and controllers, a DMA (direct memory access ) module, a physical layer communication module, and the like, which are called Shell (platform characteristic components), and the platform characteristic components are connected with external memory devices, other input/output devices, and physical interfaces; the other part is related to the accelerated application program and comprises an application related processing module called roller (application logic). In the Shell-rotor architecture, a large number of different Shell-rotor interfaces exist due to the change of the platform requirements of the FPGA accelerator or the addition of a third-party FPGA project, which causes a great burden on the management of the FPGA accelerator equipment by a cloud data center. Based on the Shell-rotor architecture, a developer only needs to follow an interface between the Shell and the rotor to develop a rotor part related to an application program, and does not need to pay attention to the Shell part, so that development workload is reduced. In another aspect, based on the reconfiguration technology of the FPGA, the Role portion may download different application configuration files at runtime to implement different functions and accelerate different applications.

However, the above architecture is feasible on the premise that the interface between the Shell and the Role is kept constant, and the interface between the Shell and the Role includes a memory access interface, a control interface, an interrupt interface, and the like. Therefore, if in the future the cloud data center wants to upgrade the DMA module in the Shell section or add new functional components resulting in a change of the interface between Shell and Role, the cloud data center must maintain both new and old versions of Shell simultaneously in order to ensure that the Role based on the previous Shell is available. In addition, third-party FPGA engineering for realizing basic functions, such as encryption and decryption modules, compression modules and the like, are increasingly used in the development process of FPGA acceleration application. The developer wants to include the third party FPGA engineering in Shell to reduce the development effort of the rule. But different developers' requirements for basic functional modules necessarily result in more different versions of Shell. When the Shell contained in the FPGA accelerator does not match the function Role that it is desired to use, the Shell that matches the Role needs to be downloaded and the server may need to be restarted to validate the new Shell, but restarting the server in the cloud data center is costly and sometimes unacceptable. Therefore, in the related art, the flexibility of the accelerator device is poor, and the interface requirement of the self platform requirement change or the addition of the third party FPGA engineering cannot be met.

Thus, the present application adds a dynamic platform assembly layer between the application logic module layer and the static platform assembly layer of the field programmable gate array chip, including dynamically added or updated functional assemblies related to the characteristics of the accelerator device. Namely, on one hand, a constant area which is only related to the characteristics of the accelerator equipment, namely a static platform assembly layer is maintained so as to avoid restarting of a server caused by updating, and on the other hand, a dynamic platform assembly layer is maintained, so that the functional characteristics of the FPGA accelerator platform can be expanded according to the requirement of the accelerator equipment to change or add a third-party FPGA project, the requirement of the accelerator equipment on changing or adding the third-party FPGA project is met, and the flexibility of the accelerator equipment is improved.

The field programmable gate array chip meets the requirements of self platform requirement change or third party FPGA engineering addition, and improves the flexibility of accelerator equipment.

Referring to fig. 2, a block diagram of a field programmable gate array chip is shown according to an exemplary embodiment, and is applied to an accelerator device, which is connected to a host, and includes a field programmable gate array chip including an application logic module layer 300, a dynamic platform component layer 200, and a static platform component layer 100, which are sequentially connected, as shown in fig. 2;

The static platform component layer 100 includes a first functional component that is related to the characteristics of the accelerator device and that has no update requirements; the first functional component is loaded from a flash memory or read-only memory chip of the accelerator device;

the dynamic platform component layer 200 comprises a second functional component which is dynamically added or updated and is related to the characteristics of the accelerator device, and a second processing module which is dynamically added and shared by a plurality of application programs; the second functional component and the second processing module are configured from the host;

the application logic module layer 300 includes a dynamically added first processing module associated with a single application; the first processing module is configured from the host.

In particular implementations, the accelerator device, in use, is connected to a host, the accelerator device comprising a field programmable gate array chip comprising an application logic module layer 300, a dynamic platform assembly layer 200, and a static platform assembly layer 100 connected in sequence.

In this embodiment, the static platform component layer 100 is consistent with the Shell meaning in the traditional Shell-rotor architecture, but the requirements are more strict, and the "platform" herein may be understood as the accelerator device itself, where the static platform component layer 100 not only includes functional components related to the characteristics of the accelerator device, such as a memory controller, a physical layer communication module, an input/output processing module, and the like, but also requires that it has no possibility of updating in the future to avoid updating the static platform component. The physical layer communication modules may include PCIe (peripheral component interconnect express, a high speed serial computer expansion bus standard) channel module, DDR (Double Data Rate) channel module, the platform physical characteristics of the FPGA accelerator have determined their PCIe physical communication characteristics, so the PCIe modules are placed at the static platform component layer. However, the DMA module, even though independent of the application logic, may have a possibility of replacement in the future and therefore may not be placed in the static platform component layer.

The first functional component is located in a Flash (Flash) or Read-Only Memory (ROM) chip of the accelerator device, and after the accelerator device is powered up, the first functional component in the Flash or ROM Memory is loaded into a static platform component layer of the FPGA chip.

As a possible implementation manner, the static platform component layer is connected to a physical interface through the physical layer communication module, and the static platform component layer is connected to an input/output interface through the input/output processing module. In a specific implementation, the static platform component layer may be connected to a memory device, and connected to an input/output interface through an input/output processing module, and then connected to the input/output device, and connected to a physical interface through a physical layer communication module, for example, connected to a PCIe interface through a PCIe module.

As a preferred implementation manner, the static platform assembly layer further includes a static platform management module, and the static platform management module is configured to communicate with the dynamic platform assembly layer to obtain information of the second functional assembly and the second processing module included in the dynamic platform assembly layer, and control information of the forwarding host end. In a specific implementation, a static platform management module is additionally arranged in the static platform assembly layer and is used for communicating with the dynamic platform assembly layer, knowing information of the second functional assembly and the second processing module contained in the dynamic platform assembly layer, and forwarding control information from a host side.

In this embodiment, the application logic module layer 300 is consistent with the Role meaning in the conventional Shell-Role architecture, but the requirements are somewhat relaxed, and still only the processing modules related to the acceleration application are included, but not all the processing modules required for the acceleration application are required, where some functional modules shared by multiple applications can be placed in the dynamic platform component layer, that is, the application logic module layer 300 includes processing modules related to a single application. After the static platform assembly layer is loaded, the host end configures the first processing module to an application logic module layer of the FPGA chip through a PCIe channel according to the type of the required application program so as to realize different application functions.

In this embodiment, the dynamic platform assembly layer 200 is located between the static platform assembly layer 100 and the application logic module layer 300, and is also an area that can be dynamically configured at runtime, as is the case with the Role. After the static platform assembly layer is loaded, the second processing module and the second functional assembly are configured to the dynamic platform assembly layer of the FPGA chip through a PCIe channel by the host side.

As a possible implementation, the dynamic platform component layer includes a shared library including a second processing module shared by a plurality of dynamically added applications and a platform function component library including a dynamically added or updated second function component related to a characteristic of the accelerator device. In a specific implementation, the dynamic platform component layer comprises a shared library and a platform function component library, wherein the shared library comprises a processing module shared by a plurality of dynamically added application programs, such as a video decoding module, an encryption and decryption module, a compression module and the like, so as to meet the requirements of application program logic on third-party FPGA engineering. The platform functionality component library includes dynamically added or updated functionality components, such as direct memory access components, etc., that are related to the characteristics of the accelerator device to satisfy additional required functionality of the platform.

As a preferred implementation manner, the dynamic platform component layer further includes a dynamic platform management module, where the dynamic platform management module is configured to communicate with the static platform component layer to report information of the second functional component and the second processing module included in the dynamic platform component layer, and forward information sent by the static platform component layer to the application logic module layer. In a specific implementation, a dynamic platform management module is additionally arranged in the dynamic platform assembly layer and is responsible for communicating with a static platform management module contained in the static platform assembly layer, reporting information of a shared library and a platform function assembly library contained in the current dynamic platform assembly layer, and forwarding information from the static platform assembly layer to the application program logic module layer.

As a possible implementation manner, the dynamic platform component layer is connected with the application program logic module layer through an application interface; the dynamic platform assembly layer is connected with the static platform assembly layer through a platform interface, and the application interface and the platform interface adopt different interface protocols. In a specific implementation, the dynamic platform component layer divides corresponding responsibilities by defining clear interfaces, which respectively use different interface protocols, namely a platform interface and an application interface, with the static platform component layer and the application logic module layer.

As a possible implementation manner, the platform interface includes a control channel and a data channel, where the control channel is used to implement a register read-write function. As a possible implementation manner, the application interface includes any one or a combination of any several of a register read-write interface, a memory read-write interface, an interrupt interface, an abnormal error report interface and a reset interface. In a specific implementation, the platform interface includes a control channel and a data channel, wherein the control channel only needs a register read-write function and does not involve burst read-write, so that a standard bus protocol AXI4 Lite is selected. The application interface comprises a register read-write interface, a memory read-write interface, an interrupt interface, an abnormal error report interface, a reset interface and the like.

The dynamic platform component layer may be considered an adapter between the static platform component layer and the application logic module layer. Under the architecture, if the FPGA accelerator platform provider needs to update or add platform functions, only corresponding modification or addition is needed on the dynamic platform component layer, and the compatibility problem with the application program logic module is not caused. From the application point of view, if the application development needs the platform to have a certain basic functional characteristics, only the dynamic platform component layer area needs to be updated to contain the required basic functional characteristics, and the static platform component layer does not need to be replaced. Thus, such an architecture can satisfy various requirements of platforms and applications by dynamically configuring the dynamic platform component layer.

For example, as shown in fig. 3, a block diagram of a specific field programmable gate array chip is shown, where the field programmable gate array chip includes an application logic module layer, a dynamic platform component layer, and a static platform component layer, the application logic module layer includes a plurality of processing modules, the dynamic platform component layer includes a dynamic platform management module, a shared library, and a platform function component library, the static platform component layer includes a static platform management module, a memory controller, other input/output interfaces and controllers, and a physical layer communication module, the application logic module layer and the dynamic platform component layer are connected through a communication interface, the dynamic platform component layer and the static platform component layer are connected through a platform interface, and the static platform component layer is connected with a memory device, other input/output devices, and a physical interface.

The embodiment of the application adds a dynamic platform assembly layer between an application program logic module layer and a static platform assembly layer of the field programmable gate array chip, wherein the dynamic platform assembly layer comprises dynamically added or updated functional assemblies related to the characteristics of the accelerator equipment. Namely, on one hand, a constant area which is only related to the characteristics of the accelerator equipment, namely a static platform assembly layer is maintained so as to avoid restarting of a server caused by updating, and on the other hand, a dynamic platform assembly layer is maintained, so that the functional characteristics of the FPGA accelerator platform can be expanded according to the requirement of the accelerator equipment to change or add a third-party FPGA project, the requirement of the accelerator equipment on changing or adding the third-party FPGA project is met, and the flexibility of the accelerator equipment is improved.

Based on the foregoing embodiment, as a preferred implementation manner, the second functional component and the second processing module included in the dynamic platform component layer are used as device features of the accelerator device and are connected in series in a linked list manner.

It will be appreciated that, after adding a reconfigurable area, i.e., a dynamic platform component layer, because the shared libraries and platform function component libraries contained by different dynamic platform component layers are widely different, it is desirable to provide a mechanism for flexibly reporting the information of the shared libraries and platform function component libraries contained by the dynamic platform component layer. In this embodiment, the processing modules in the shared library and the functional components in the platform functional component library are both regarded as features (features) of the FPGA accelerator device, and are connected in series in the form of a linked list.

As a possible implementation, the device feature comprises a feature header for describing identification information of the device feature and a control status register section comprising all control register lists and status register lists associated with the device feature.

In implementations, the device Feature includes two parts of content, one of which is a Feature Header (Feature Header) and the other of which is a control status register portion (Feature Specific Control and Status Registers). The specific structure diagram of the device feature is shown in fig. 4, and the feature header may be 24 bytes, and the identification information for describing the feature specifically includes a type field, a feature version number, a linked list end flag, an offset of the feature header of the next device feature, an interface version number, and an identifier.

The Type field (Type) is used to describe that a device feature belongs to a functional component or a processing module, 0 indicates that the device feature belongs to a processing module in the shared library, and 1 indicates that the device feature belongs to a functional component in the platform functional components.

The Feature Minor version number (Feature Minor) and the Feature Major version number (Feature Major) together constitute a Feature version number of the device Feature.

The End of List flag (End of List) is used to describe whether a device feature is the last device feature of the List, 0 indicates that the End of the List has not been reached, and other device features, 1 indicates that the End of the List has been reached, and the current device feature is the last device feature.

The offset of the feature header of the next device feature (Next DFH Byte Offset) is used to describe the offset of the feature header of the next device feature from the feature header of the current device feature, i.e., the position of the header of the next feature = the position of the current feature header + Next DFH Byte Offset.

The interface version number (Interface Version) is used to identify which version of the interface the current device feature is compatible with. If the device features belong to the functional component, the interface version number is used for describing the version number of the platform interface compatible with the device features, and if the device features belong to the processing module, the interface version number is used for describing the version number of the application interface compatible with the device features.

The identifier is used to describe the identification of the device feature, and may be a globally unique identifier GUID (Globally Unique Identifier), which is 16 bytes in total, and is formed by combining guid_l (globally unique identifier low byte) and guid_h (globally unique identifier Gao Zijie), and is an identification number of the current feature to identify the function of the current feature.

The control status register portion includes all control register lists and status register lists associated with the device feature, the length of the control status register portion being less than or equal to the offset of the feature header of the next device feature.

For example, assuming that an FPGA accelerator is used to accelerate an application related to video acceleration processing, a developer desires the FPGA accelerator platform to have a video decoding module capable of processing the video encoding standard H265 to reduce development effort, while the developer also desires the FPGA accelerator platform to have a DMA module. In response to the above need, a dynamic platform component layer may be created that includes an H265 video decoding module and a DMA module. Assuming that the GUID of the H256 video decoding module is 8EBB414596B2BF07133a44369E5D37B4, the module control status register total size is 0x100, the major version number is 1, and the minor version number is 2; the GUID of the DMA module is C323443B8052A9D0766E4F43 CCCD073, the total size of a module control status register is 0x200, the major version number is 3, and the minor version number is 4; the platform interface is 0x123, and the application interface is 0x456; the dynamic platform component contains the characteristic information format content as shown in fig. 5.

The embodiment of the application discloses a construction method of a field programmable gate array chip, which meets the requirements of accelerator equipment platform requirement change or third-party FPGA engineering addition and improves the flexibility of accelerator equipment.

Referring to fig. 6, a flowchart of a method for constructing a field programmable gate array chip according to an exemplary embodiment is shown, and includes:

s101: determining a first functional component related to the characteristics of the accelerator device and no update requirement exists, a second functional component related to the characteristics of the accelerator device and needing to be dynamically added or updated, a first processing module related to a single application program and needing to be dynamically added, and a second processing module shared by a plurality of application programs and needing to be dynamically added;

s102: loading the first functional component from a flash memory or read-only memory chip of the accelerator device to a static platform component layer, configuring the second functional component and the second processing module from the host to a dynamic platform component layer, and configuring the first processing module from the host to an application logic module layer;

the aim of this embodiment is to build a field programmable gate array chip. In building a field programmable gate array chip, an application logic module layer, a dynamic platform component layer and a static platform component layer need to be built.

First, a first functional component related to the characteristics of the accelerator device and for which there is no update requirement is determined, and after the accelerator device is powered up, the first functional component in Flash or ROM memory is loaded to the static platform component layer of the FPGA chip. And secondly, determining a second functional component which is related to the characteristics of the accelerator equipment and needs to be dynamically added or updated, and a second processing module which is shared by a plurality of application programs which need to be dynamically added, wherein after the static platform component layer is loaded, the second processing module and the second functional component are configured to the dynamic platform component layer of the FPGA chip by a host side through a PCIe channel. And finally, determining a first processing module related to a single application program which needs to be dynamically added, and after the static platform assembly layer is loaded, configuring the first processing module to an application program logic module layer of the FPGA chip by a host end according to the type of the required application program through a PCIe channel so as to realize different application functions.

In this embodiment, the static platform component layer is consistent with the Shell meaning in the traditional Shell-rotor architecture, but is more strictly required, where "platform" is understood as the accelerator device itself, and the static platform component layer not only includes functional components related to the characteristics of the accelerator device, such as a memory controller, a physical layer communication module, an input/output processing module, and the like, but also requires that it has no possibility of updating the static platform component in the future, so as to avoid updating the static platform component. The physical layer communication module may comprise a PCIe module whose PCIe physical communication characteristics have been determined by the platform physical characteristics of the FPGA accelerator, so the PCIe module is placed at the static platform component layer. However, the DMA module, even though independent of the application logic, may have a possibility of replacement in the future and therefore may not be placed in the static platform component layer.

In this embodiment, the application logic module layer is consistent with the Role meaning in the traditional Shell-Role architecture, but the requirements are somewhat relaxed, and still only the processing modules related to the acceleration application are contained, but not all the processing modules required by the acceleration application are contained, wherein some functional modules shared by multiple applications can be placed in the dynamic platform component layer, that is, the application logic module layer includes the processing modules related to a single application.

In this embodiment, the dynamic platform assembly layer is located between the static platform assembly layer and the application logic module layer, and is also an area that can be dynamically configured at runtime, as is the case with the roller.

S103: creating an application interface between the application logic module layer and the dynamic platform component layer and a platform interface between the dynamic platform component layer and the static platform component layer.

In a specific implementation, the dynamic platform component layer divides corresponding responsibilities by defining clear interfaces, which respectively use different interface protocols, namely a platform interface and an application interface, with the static platform component layer and the application logic module layer.

On the basis of the above embodiment, as a preferred implementation manner, loading the first functional component from the flash memory or the read-only memory chip of the accelerator device to the static platform component layer, configuring the second functional component and the second processing module from the host to the dynamic platform component layer, and configuring the first processing module from the host to the application logic module layer further includes: and taking a second functional component and a second processing module contained in the dynamic platform component layer as equipment characteristics of the accelerator equipment, and connecting the second functional component and the second processing module in series in a linked list mode.

As a possible implementation, the device features include a feature header and a control status register portion; the feature header is used for describing identification information of the device feature, the feature header comprises any one or a combination of a type field, a feature version number, a linked list end mark, an offset of the feature header of the next device feature, an interface version number and an identifier, and the type field is used for describing that the device feature belongs to a functional component or a processing module; if the equipment features belong to the functional components, the interface version number is used for describing the version number of the platform interface compatible with the equipment features, and if the equipment features belong to the processing module, the interface version number is used for describing the version number of the application interface compatible with the equipment features; the linked list end mark is used for describing whether the equipment characteristic is the last equipment characteristic of the linked list; the offset of the feature header of the next device feature is used to describe the offset of the feature header of the next device feature from the feature header of the current device feature; the identifier is used for describing the identification of the device characteristics; the control status register portion includes all of a list of control registers and a list of status registers associated with the device feature.

The identifier is used to describe the identification of the device feature, which may be a globally unique identifier GUID (Globally Unique Identifier), and is 16 bytes in total, and is formed by combining guid_l and guid_h, and is an identification number of the current feature, so as to identify the function of the current feature.

The following describes a device for constructing a field programmable gate array chip according to an embodiment of the present application, and the device for constructing a field programmable gate array chip described below and the method for constructing a field programmable gate array chip described above may be referred to each other.

Referring to fig. 7, a construction apparatus of a field programmable gate array chip according to an exemplary embodiment is shown, as shown in fig. 7, including:

a determining unit 701, configured to determine a first functional component related to a platform characteristic and no update requirement exists, a second functional component related to the platform characteristic that needs to be dynamically added or updated, a fixed first processing module related to an acceleration application, and a second processing module related to the acceleration application that needs to be dynamically added;

a configuration unit 702, configured to load the first functional component from a flash memory or a read-only memory chip of the accelerator device to a static platform component layer, configure the second functional component and the second processing module from the host to a dynamic platform component layer, and configure the first processing module from the host to an application logic module layer;

A creating unit 703, configured to create an application interface between the application logic module layer and the dynamic platform component layer, and a platform interface between the dynamic platform component layer and the static platform component layer.

On the basis of the above embodiment, as a preferred implementation manner, the method further includes:

and the linked list series connection unit is used for taking the functional components and the processing modules contained in the dynamic platform component layer as the equipment characteristics of the accelerator equipment and connecting the functional components and the processing modules in series in a linked list mode.

The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.

Based on the hardware implementation of the program modules, and in order to implement the method of the embodiments of the present application, the embodiments of the present application further provide an accelerator apparatus, fig. 8 is a structural diagram of an accelerator apparatus shown in fig. 8 according to an exemplary embodiment, where the accelerator apparatus includes:

the field programmable gate array chip 1 provided in the above embodiment can perform information interaction with other devices such as network devices;

and the processor 2 is used for executing the construction method of the field programmable gate array chip provided by one or more of the technical schemes when running the computer program. And the computer program is stored on the memory 3.

Of course, the accelerator device may also comprise a communication interface for information interaction with other devices, such as network devices, etc., and in actual use the various components of the accelerator device are coupled together via the bus system 4. It will be appreciated that the bus system 4 is used to enable connected communications between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. But for clarity of illustration the various buses are labeled as bus system 4 in fig. 5.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the accelerator apparatus. Examples of such data include: any computer program for operating on an accelerator device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 3 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the embodiments of the present application may be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 2 or by instructions in the form of software. The processor 2 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium in the memory 3 and the processor 2 reads the program in the memory 3 to perform the steps of the method described above in connection with its hardware.

The processor 2 implements corresponding flows in the methods of the embodiments of the present application when executing the program, and for brevity, will not be described in detail herein.

In an exemplary embodiment, the present application also provides a storage medium, i.e. a computer storage medium, in particular a computer readable storage medium, for example comprising a memory 3 storing a computer program executable by the processor 2 for performing the steps of the method described above. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, CD-ROM, etc.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing an accelerator device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The field programmable gate array chip is characterized by being applied to accelerator equipment, wherein the accelerator equipment is connected with a host, and the field programmable gate array chip comprises an application program logic module layer, a dynamic platform assembly layer and a static platform assembly layer which are sequentially connected;

the static platform component layer includes a first functional component related to a characteristic of the accelerator device and having no update requirements; the first functional component is loaded from a flash memory or read-only memory chip of the accelerator device; the first functional component comprises any one or a combination of a plurality of memory controllers, physical layer communication modules and input/output processing modules;

the dynamic platform component layer comprises a second functional component which is dynamically added or updated and is related to the characteristics of the accelerator equipment, and a second processing module which is dynamically added and shared by a plurality of application programs; the second functional component and the second processing module are configured from the host; the second functional component comprises a direct memory access component;

2. The field programmable gate array chip of claim 1, wherein the static platform assembly layer is connected to a physical interface through the physical layer communication module, and the static platform assembly layer is connected to an input/output interface through the input/output processing module.

3. The field programmable gate array chip of claim 1, wherein the static platform component layer further comprises a static platform management module, and the static platform management module is configured to communicate with the dynamic platform component layer to obtain information of the second functional component and the second processing module included in the dynamic platform component layer, and control information of a forwarding host side.

4. The field programmable gate array chip of claim 1, wherein the dynamic platform component layer comprises a shared library comprising a second processing module shared by a plurality of dynamically added applications and a platform functional component library comprising a dynamically added or updated second functional component related to a characteristic of the accelerator device.

5. The field programmable gate array chip of claim 4, wherein the second processing module comprises any one or a combination of any of a video decoding module, an encryption and decryption module, and a compression module.

6. The field programmable gate array chip of claim 1, wherein the dynamic platform assembly layer further comprises a dynamic platform management module, the dynamic platform management module configured to communicate with the static platform assembly layer to report information of the second functional assembly and the second processing module contained in the dynamic platform assembly layer, and forward information sent by the static platform assembly layer to the application logic module layer.

7. The field programmable gate array chip of claim 1, wherein said dynamic platform assembly layer is coupled to said application logic module layer via an application interface;

8. The field programmable gate array chip of claim 7, wherein the application interface and the platform interface employ different interface protocols.

9. The field programmable gate array chip of claim 7, wherein the platform interface comprises a control channel and a data channel, the control channel being configured to implement a register read-write function.

10. The field programmable gate array chip of claim 7, wherein the application interface comprises any one or a combination of a register read-write interface, a memory read-write interface, an interrupt interface, an exception error reporting interface, a reset interface.

11. The field programmable gate array chip of claim 1, wherein the second functional component and the second processing module included in the dynamic platform component layer are connected in series as device features of the accelerator device in the form of a linked list.

12. The field programmable gate array chip of claim 11, wherein the device feature comprises a feature header for describing identification information of the device feature and a control status register portion comprising all of a control register list and a status register list associated with the device feature.

13. The field programmable gate array chip of claim 12, wherein the feature header includes any one or a combination of a type field, a feature version number, a linked list end flag, an offset of a feature header of a next device feature, an interface version number, an identifier;

14. The field programmable gate array chip of claim 13, wherein a length of the control status register portion is less than or equal to an offset of a feature header of the next device feature.

15. A method for constructing a field programmable gate array chip, the method being applied to an accelerator device, the accelerator device being connected to a host, the method comprising:

Determining a first functional component related to the characteristics of the accelerator device and no update requirement exists, a second functional component related to the characteristics of the accelerator device and needing to be dynamically added or updated, a first processing module related to a single application program and needing to be dynamically added, and a second processing module shared by a plurality of application programs and needing to be dynamically added; the first functional component comprises any one or a combination of any two of a memory controller, a physical layer communication module and an input/output processing module, and the second functional component comprises a direct memory access component;

16. The method according to claim 15, wherein loading the first functional component from a flash memory or a read only memory chip of the accelerator device to a static platform component layer, configuring the second functional component and the second processing module from the host to a dynamic platform component layer, and configuring the first processing module from the host to an application logic module layer, further comprises:

17. The method of claim 16, wherein the device features include a feature header and a control status register portion;

18. A construction apparatus for a field programmable gate array chip, applied to an accelerator device, the accelerator device being connected to a host, the apparatus comprising:

the system comprises a determining unit, a first processing unit and a second processing unit, wherein the determining unit is used for determining a first functional component related to platform characteristics and not requiring updating, a second functional component related to platform characteristics which needs to be dynamically added or updated, a fixed first processing module related to acceleration application and a second processing module related to acceleration application which needs to be dynamically added; the first functional component comprises any one or a combination of any two of a memory controller, a physical layer communication module and an input/output processing module, and the second functional component comprises a direct memory access component;

19. An accelerator apparatus, comprising:

a field programmable gate array chip comprising any one of claims 1 to 14;

a memory for storing a computer program;

a processor for implementing the steps of the method of constructing a field programmable gate array chip according to any one of claims 15 to 17 when executing said computer program.

20. A computer-readable storage medium, on which a computer program is stored, which when being executed by a processor implements the steps of the method of constructing a field programmable gate array chip as claimed in any one of claims 15 to 17.