KR20220061828A - Computing system including accelerator and operation method thereof - Google Patents

Abstract

According to an embodiment of the present disclosure, a method of operating an accelerator comprises the steps of: performing a cache flush operation in response to a first interrupt; performing an update section jump operation to jump the program counter to the update section; performing a program update operation to write a binary file compiled in a host to a memory module connected to the accelerator, after the update section jump operation; and performing a start section jump operation to jump a program counter to the start section, in response to the second interrupt, after the program update operation.

Description

COMPUTING SYSTEM INCLUDING ACCELERATOR AND OPERATION METHOD THEREOF

The present disclosure relates to a computing system, and more particularly, to a computing system including an accelerator and an operating method thereof.

The computing system may include a deep learning accelerator in the form of a PCIe card. A host included in the computing system may use an operating system program, and the accelerator may execute the accelerator program without the operating system program. The host can compile the accelerator program and send it to the accelerator. The accelerator program update is required during the processor operation of the accelerator.

SUMMARY OF THE INVENTION An object of the present disclosure is to provide a computing system including an accelerator capable of performing program update while the accelerator is in operation, and a method of operating the same.

A method of operating an accelerator according to an embodiment of the present disclosure includes performing a cache flush operation in response to a first interrupt, performing an update section jump operation to jump a program counter to an update section after performing the cache flush operation; After the update section jump operation, the host performs a program update operation to write the compiled binary file to a memory module associated with the accelerator, and after the program update operation, in response to a second interrupt, jumps the program counter to the start section and performing the starting section jump action to do so.

In one embodiment, the accelerator communicates with the host via a Peripheral Component Interconnect express (PCI-express) interface.

In an embodiment, the method of operating the accelerator further includes receiving a first interrupt from the host before the cache flush operation, and receiving a second interrupt from the host after the program update operation.

In one embodiment, the binary file includes an update section and a section for general programs including a start section by a linker script.

In one embodiment, the binary file is generated by compiling the accelerator program by the host.

In an embodiment, performing the program update operation includes reading a binary file from a host by a DMA engine included in the accelerator, and writing the binary file into a memory module by the DMA engine do.

In one embodiment, writing the binary file to the memory module includes sending a write command and an address to the memory module via a command/address line, and sending the binary file to the memory module via a data line. .

In an embodiment, performing the cache flush operation includes writing data corresponding to a dirty state stored in a cache memory device included in the accelerator into the memory module.

In one embodiment, the first and second interrupts indicate memory mapped I/O register (MMIO) write operations by the host.

In one embodiment, the accelerator is a field-programmable gate array (FPGA), a massively parallel processor array (MPPA), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a neural processing unit (NPU), a tensor (TPU) Processing Unit) and MPSoC (Multi-Processor System-on-Chip).

In an embodiment, the method of operating the accelerator further includes waiting while the program update operation is performed while the program counter runs in an infinite loop.

A computing device according to an embodiment of the present disclosure generates a binary file including an update section and a start section by performing a compile operation on an accelerator program, a host configured to transmit first and second interrupts, and a first interrupt in response to jump the program counter to the update section, and in response to a second interrupt, an accelerator configured to jump the program counter to the start section, wherein the first interrupt indicates an accelerator program update start, and the second interrupt is an accelerator program Indicates the end of the update.

In one embodiment, the computing system further includes a memory module coupled to the accelerator and configured to store a binary file executed in the accelerator.

In one embodiment, the accelerator includes a DMA engine configured to read a binary file from a host and write the binary file to a memory module.

In one embodiment, the accelerator further includes a processor configured to execute a binary file, and a cache memory device configured to store data used by the processor and, in response to the first interrupt, flush data corresponding to the dirty condition to the memory module. include

In one embodiment, the accelerator further comprises a reconstruction logic circuit configured to perform a machine learning algorithm, such as a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), or the like.

The computing system according to an embodiment of the present disclosure may perform a program update operation during an accelerator operation. Accordingly, a computing system including an improved accelerator and a method of operating the same are provided.

1 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.
FIG. 2 is a block diagram showing the accelerator of FIG. 1 .
3 is a diagram illustrating a binary file of an accelerator program according to an embodiment of the present disclosure.
4 is a flowchart illustrating an operation of the accelerator of FIG. 1 .
FIG. 5 is a diagram for explaining a program update operation of the accelerator of FIG. 1 .
6 is a flowchart illustrating an operation of the computing system of FIG. 1 .
7 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.
8 is a block diagram illustrating a data center to which a computing system according to an embodiment of the present disclosure is applied.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that those of ordinary skill in the art can easily practice the present disclosure.

Hereinafter, units, modules, layers, or functional blocks shown in the drawings used in the detailed description may be implemented in the form of software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a microelectromechanical system (MEMS), a passive element, or a combination thereof. .

In addition, unless otherwise defined, all terms including technical or scientific meanings used herein have the meanings understood by those skilled in the art to which this disclosure belongs. In general, terms defined in the dictionary are interpreted to have the same meaning as the contextual meaning in the related technical field, and unless clearly defined in the text, they are not interpreted to have an ideal or excessively formal meaning.

1 is a block diagram illustrating a computing system according to an embodiment of the present disclosure. Referring to FIG. 1 , a computing system 100 may include a host 110 , an accelerator 120 , and a memory module 130 . The computing system 100 may be various types of systems that process data and write data to the memory module 130 or process data read from the memory module 130 .

In one embodiment, the computing system 100 is a personal computer (PC), data server, cloud system, artificial intelligence server, network-attached storage (NAS), Internet of Things (IoT) device, or portable It may be implemented as an electronic device. In addition, when the computing system 100 is a portable electronic device, the computing system 100 may include a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, It may be a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, and the like.

The host 110 may control the overall operation of the computing system 100 . For example, the host 110 may control the accelerator 120 by providing commands and data. In an embodiment, the host 110 may offload the processing operation to be performed to the accelerator 120 . The host 110 may transmit a command and data to the accelerator 120 so that the accelerator 120 performs a specific computation operation without directly performing the specific arithmetic operation.

The accelerator 120 may correspond to various types of coprocessors. In one embodiment, the accelerator 120 is a field-programmable gate array (FPGA), a massively parallel processorarray (MPPA), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a neural processing unit (NPU), a TPU (TPU). It may be various types of accelerators, such as a Tensor Processing Unit) and a Multi-Processor System-on-Chip (MPSoC). For example, the accelerator 120 may be an accelerator that performs a deep learning operation.

The memory module 130 may write data or read data according to the control of the accelerator 120 . For example, the memory module 130 may write data or provide read data to the accelerator 120 in response to a command and an address provided from the accelerator 120 .

In an embodiment, the computing system 100 may include the accelerator 120 and the memory module 130 in the form of a card inserted on a board (or main board). For example, an add-in type card including one or more accelerators and one or more memory modules may be mounted in an expansion slot on a board. For example, a card mounted in the expansion slot may include one accelerator and one or more memory modules. As a variant embodiment, the card may include one accelerator and multiple memory modules. Alternatively, the card may include a plurality of accelerators and a plurality of memory modules.

The host 110 and the accelerator 120 may communicate with each other via a bus. In an embodiment, the bus may support communication between components connected to the bus (BUS) through various types of protocols, such as peripheral component interconnect (PCI), PCI Express (PCIe), BlueLink, and Quick Path Interconnect (QPI). there is.

In one embodiment, if the bus supports communication according to the PCI protocol, the card may correspond to a PCI card, and if the card includes an accelerator, the card may be referred to as a graphics card or an accelerator card.

In one embodiment, the memory module 130 includes DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory) ), such as DRAM. However, embodiments of the present disclosure are not limited thereto, and as an example, the memory module 130 may include flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and ReRAM. (Resistive RAM) may be implemented as a non-volatile memory.

In an embodiment, the host 110 may update a program (ie, an accelerator program) to be processed by the processor of the accelerator 120 . The host 110 may update the accelerator program by performing an initialization operation on the accelerator 120 . That is, when updating the accelerator program, the host 110 may record the updated accelerator program in a nonvolatile memory (eg, a flash memory or a secure digital card (SD card)) of the accelerator 120 .

However, the host 110 according to an embodiment of the present disclosure may update the accelerator program while the accelerator 120 is operating without an initialization operation for the accelerator 120 . For example, the host 110 may compile an updated accelerator program. The host 110 may provide the compiled accelerator program to the accelerator 120 . The accelerator 120 may update a program under the control of the host 110 . The update operation of the accelerator 120 according to an embodiment of the present disclosure will be described in more detail with reference to the following drawings.

FIG. 2 is a block diagram showing the accelerator of FIG. 1 . 1 and 2 , the accelerator 120 includes a processor 121 , a cache memory device 122 , a ROM 123 , a direct memory access engine (DMA engine) 124 , a host interface circuit 125 , It may include a reconfiguration logic circuit 126 , and a memory controller 127 . The accelerator 120 may perform a deep learning operation. In an embodiment, the accelerator 120 may be configured to drive various deep neural networks (DNNs), such as YOLO, ResNet, ResNeXt, DenseNet, and Graph Convolutional Network (GCN).

The processor 121 may control overall operations of the accelerator 120 . The cache memory device 120 may store data or provide stored data to the processor 121 in response to signals received from the processor 121 . The cache memory device 122 may have a faster access speed than the memory module 130 . That is, since some of the data stored in the memory module 130 is stored in the cache memory device 122 , the access speed according to the request of the processor 121 may be improved. In an embodiment, the cache memory device 122 may be a static random access memory (SRAM) device, but the scope of the present disclosure is not limited thereto.

The ROM 123 may store various information required for the accelerator 120 to operate in the form of firmware. The DMA engine 124 may be a hardware device that controls a direct memory access (DMA) operation between the host 110 and the memory module 130 without the intervention of the processor 121 .

For example, the accelerator 120 may operate in a DMA mode in order to improve data transfer speed. The DMA mode refers to an operation mode in which data is transferred under the control of the DMA engine 124 without or without intervention of the processor 121 or the core included in the accelerator 120 . That is, since no control or processing from the processor or core is required while data is being transferred, the data transfer speed can be improved.

In an embodiment, the DMA engine 124 may control or manage data transfer between the host 110 and the memory module 130 . For example, the DMA engine 124 may read a binary file (ie, a new accelerator program) compiled from the host 110 and write the binary file to the memory module 130 . The DMA engine 124 may transmit a write command and an address to the memory module 130 through a command/address line. The DMA engine 124 may transmit data (or a binary file) to the memory module 130 through a data line.

The accelerator 120 may communicate with the host 110 through the host interface circuit 125 . As described above, the host interface circuit 125 may be a PCIe interface. However, the scope of the present disclosure is not limited thereto, and the host interface 133 includes a Universal Serial Bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), an Advanced Technology Attachment (ATA), Serial-ATA, Parallel- It may include at least one of various interfaces such as ATA, small computer small interface (SCSI), enhanced small disk interface (ESD), integrated drive electronics (IDE), Firewire, and universal flash storage (UFS). .

The reconfiguration logic circuit 126 may be configured to assist the operation of the host 110 by performing some of the operations performed by the host 110 . For example, the reconfiguration logic circuit 126 may be a field-programmable gate array (FPGA). However, the present disclosure is not limited thereto, and the reconfiguration logic circuit 126 may be a programmable logic device (PLD) or a complex PLD (CPLD).

In an embodiment, the reconstruction logic circuit 126 may perform a machine learning algorithm, such as a convolutional neural network (CNN), a recurrent neural network (RNN), or the like. For example, the reconstruction logic circuit 126 may be configured to perform video transcoding, and may be configured to perform CNN under the control of the host 110 or the processor 121 .

For example, the reconstruction logic circuit 126 may perform inline processing, pre-processing, pre-filtering, cryptography, compression, protocol bridging, etc. . The reconstruction logic circuit 126 may perform one or more of a sorting operation, a searching operation, a logic operation, and a arithmetic operation.

For example, the logic operation may represent an operation performed by various logic gates, such as an AND gate, an OR gate, an XOR gate, a NOR gate, and a NAND gate, or an operation operation combining two or more of these operations. The arithmetic operation performed by the reconfiguration logic circuit 126 is not limited to the example described above, and may be any operation corresponding to some of the operations performed by the host 200 .

The accelerator 120 may communicate with the memory module 130 through the memory controller 127 . The memory controller 127 may control the memory module 130 . For example, the memory controller 127 may transmit an address ADDR, a command CMD, and a control signal CTRL for controlling the memory module 130 to the memory module 130 , and the memory module 130 . and data DATA may be transmitted/received through the data line DQ. For example, the memory controller 127 may transmit a command and an address to the memory module 130 through a command/address line.

3 is a diagram illustrating a binary file of an accelerator program according to an embodiment of the present disclosure. Referring to FIG. 3 , the binary file BF of the accelerator program may be an Executable And Linking Format (ELF). The binary file BF may be loaded into the memory module 130 . The binary file BF may be disposed in the first address A1 to the fourth address A4 of the memory module 130 .

The binary file BF according to an embodiment of the present disclosure may further include an update section P3 in addition to the general program sections P1 and P2. That is, the binary file may include sections P1 and P2 for general programs and a section P3 for updates. The sections P1 and P2 for the general program are disposed within the first address A1 to the third address A3 of the memory module 130 , and the section P3 for the updater is the third address of the memory module 130 . It may be disposed within the fourth address (A4) from (A3).

The general program sections P1 and P2 may include a .start section, a .startup section, a .text section, a .rodata section, a .data section, and a .bss section. For example, the area where the actual instruction (or code) is loaded points to the .text section, the area where variables (or data) are stored points to the .rodata section or .data section, and the uninitialized data area points to the .bss section can point to The area of code that is executed before the program's main function can point to either a .start section or a .startup section.

In one embodiment, the .start section is disposed within the first address A1 to the second address A2, and the remaining sections (.startup section, .text section, .rodata section, .data section, .bss section, etc.) ) may be disposed within the second address A2 to the third address A3 .

A linker script and a source program may be set so that the .update section is placed from a predetermined address (eg, the third address A3). For example, when a specific function or variable is declared in the code, the section name can be given as an attribute and the section can be set to be placed at a specific address in the linker script. That is, when an update function is declared in the code, the name of the .update section may be given as an attribute, and the .update section may be set to be placed at the third address in the linker script.

4 is a flowchart illustrating an operation of the accelerator of FIG. 1 . FIG. 5 is a diagram for explaining a program update operation of the accelerator of FIG. 1 . 1 and 4 , in step S110 , the accelerator 120 may perform a cache flush operation in response to the first interrupt, and the program counter PC may jump to an update section (.update section). . In an embodiment, the accelerator 120 may receive a first interrupt from the host 110 . For example, the first interrupt may be a signal indicating the start of the accelerator program update.

The accelerator 120 may perform a cache flush operation in response to the first interrupt provided from the host 110 . For example, the accelerator 120 may flush data stored in the cache memory device 122 to the memory module 130 by an interrupt routine caused by the first interrupt.

The accelerator 120 jumps the program counter PC to an interrupt service routine (ISR) in which the code is located in the .update section, and may wait in an infinite loop. As shown in FIG. 5 , the program counter PC located in the general program sections P2 may jump to the third address A3 where the .update section P3 is located.

The accelerator 120 may not perform another operation to update a new program. The accelerator 120 may jump the program counter PC to the .update section and wait until the new program is updated. Due to this, while the program is being updated, the program counter PC may not access the sections P1 and P2 for general programs.

In step S120 , the accelerator 120 may update a new program. In an embodiment, the accelerator 120 may receive a new program from the host 110 . For example, the host 110 may directly write a new program to the memory module 130 . Alternatively, a direct memory access (DMA) engine included in the accelerator 120 may record a new program in the memory module 130 .

In an embodiment, when the binary file is transmitted from the host 110 to the accelerator 120 through the DMA engine 124 , the accelerator 120 may receive a third interrupt related to the binary file. The interrupt service routine resulting from the third interrupt may be placed in the update section.

In step S130 , the accelerator 120 may jump the program counter PC to the start section (.start section) in response to the second interrupt. For example, the accelerator 120 may receive the second interrupt from the host 110 . The second interrupt may be a signal indicating the end of the program update.

The accelerator 120 may jump the program counter PC to the .start section by the interrupt routine caused by the second interrupt. 5 , the program counter PC located in the .update section P3 may jump to the first address A1 in which the .start section P1 is located. Thereafter, the accelerator 120 may execute the updated program.

As described above, the accelerator 120 may add an .update section to keep the program counter in the .update section while the program is being updated. For this reason, while the accelerator operation is being performed, the accelerator 120 may update a new program.

6 is a flowchart illustrating an operation of the computing system of FIG. 1 . 1 and 6 , in step S210 , the host 110 may perform a program compilation operation. For example, the host 110 may compile an updated or new accelerator program. The host 110 may compile an accelerator program to generate a binary file.

In step S220 , the host 110 may transmit a first interrupt to the accelerator 120 . The host 110 may notify the accelerator 120 to prepare for the program update through the first interrupt. For example, the first interrupt may be a command transmitted from the host 110 to the accelerator 120 . Alternatively, the first interrupt may indicate a write operation of the host 110 to a memory mapped I/O register (MMIO) of the accelerator 120 .

In step S230 , the accelerator 120 may perform a flush operation in response to the first interrupt and jump the program counter PC to the .update section. For example, the accelerator 120 may flush data corresponding to the dirty state stored in the cache memory device 122 to the memory module 130 . The accelerator 120 may jump the program counter PC to the third address A3 where the .update section is disposed.

In step S240 , the host 110 may transmit the updated program to the accelerator 120 . For example, the host 110 may directly transmit the compiled binary file to the accelerator 120 . Alternatively, the DMA engine 124 included in the accelerator 120 may read a binary file from the host 110 and write it to the memory module 130 .

In step S250 , the accelerator 120 may update the received new program. For example, the accelerator 120 may write a new program to the memory module 130 . The processor 121 may wait in an infinite loop in the .update section. The DMA engine 124 included in the accelerator 120 may write the received binary file to the memory module 130 .

In step S260 , the host 110 may transmit a second interrupt to the accelerator 120 . The host 110 may notify the end of the program update of the accelerator 120 through the second interrupt. For example, the second interrupt may be a command transmitted from the host 110 to the accelerator 120 . Alternatively, the second interrupt may indicate a memory mapped I/O register (MMIO) write operation by the host 110 of the accelerator 120 .

In step S270 , the accelerator 120 may jump the program counter PC to the .start section. For example, the accelerator 120 may jump the program counter PC to the first address A1 in which the .start section is disposed. Thereafter, the accelerator 120 may start a new program initialization.

As described above, when the accelerator program update is performed, the computing system 100 may jump the program counter PC of the accelerator to a different .update section from the space where the program is updated. Accordingly, the computing system 100 may update a new program through the DMA engine 124 without newly programming the ROM or flash memory of the accelerator.

7 is a block diagram illustrating a computing system according to an embodiment of the present disclosure. Referring to FIG. 7 , the computing system 1000 includes a processor 1100 , a memory device 1200 , an accelerator 1300 , a chipset 1400 , a GPU 1500 , an input/output device 1600 , and a storage device 1700 . includes The processor 1100 may control overall operations of the computing system 1000 . The processor 1100 may perform various operations performed by the computing system 1000 .

The memory device 1200 may communicate through a double data rate (DDR) interface. For example, the processor 1100 may use the memory device 1200 as an operating memory, a buffer memory, or a cache memory of the computing system 1000 .

The accelerator 1300 may be connected to the chipset 1400 . The accelerator 1300 may be the accelerator 120 described with reference to FIGS. 1 to 6 . The chipset 1400 is electrically connected to the processor 1100 , and may control hardware of the computing system 1000 according to the control of the processor 1100 . For example, the chipset 1400 may be connected to each of the GPU 1500 , the input/output device 1600 , and the storage device 1700 through major buses, and may serve as a bridge for the major buses.

The GPU 1500 may perform a series of arithmetic operations for outputting image data of the computing system 1000 . For example, the GPU 1500 may be mounted in the processor 1100 in a system-on-chip form.

The input/output device 1600 includes various devices that input data or commands to the computing system 1000 or output data to the outside. For example, the input/output device 1600 includes user input devices such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, a piezoelectric element, and an LCD ( Liquid Crystal Display), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, and user output devices such as an LED, a speaker, and a motor may be included.

The storage device 1700 may be used as a storage medium of the computing system 1000 . The storage device 1600 may include mass storage media such as a hard disk drive, an SSD, a memory card, a memory stick, and the like.

8 is a block diagram illustrating a data center to which a computing system according to an embodiment of the present disclosure is applied. Referring to FIG. 8 , the data center 2000 may include a plurality of computing nodes 2100 to 2400 (or servers). The plurality of computing nodes 2100 to 2400 may communicate with each other through the network NT. In an embodiment, the network NT may be a storage-only network such as a storage area network (SAN) or an Internet network such as TCP/IP. In an embodiment, the network NT may include at least one of various communication protocols such as Fiber Channel, iSCSI protocol, FCoE, NAS, and NVMe-oF.

Each of the plurality of computing nodes 2100 to 2400 includes processors 2110 , 2210 , 2310 , 2410 , memories 2120 , 2220 , 2320 , 2420 , accelerators 2130 , 2230 , 2330 , 2430 , and an interface. Circuits 2140 , 2240 , 2340 , and 2440 may be included, respectively.

For example, the first computing node 2100 may include a first processor 2110 , a first memory 2120 , a first accelerator 2130 , and a first interface circuit 2140 . In an embodiment, the first processor 2110 may be implemented as a single core or a multi-core. The first memory 2120 may include a memory such as DRAM, SDRAM, SRAM, 3D XPoint memory, MRAM, PRAM, FeRAM, ReRAM, 3D X-Point, and the like. The first memory 2120 may be used as a system memory, an operational memory, or a buffer memory of the first computing node 2100 . The first accelerator 2130 may be the accelerator 120 described with reference to FIGS. 1 to 6 . The first interface circuit 2140 may be a network interface controller (NIC) configured to support communication through the network NT.

In an embodiment, the first processor 2110 of the first computing node 2100 may be configured to access the first memory 2120 based on a predetermined memory interface. Alternatively, in an embodiment of a shared memory architecture, the first processor 2110 of the first computing node 2100 may access the memories of the other computing nodes 2200 , 2300 , 2400 through the network NT. (2220, 2320, 2420). The first interface circuit 2140 may include a network switch (not shown) configured to control or support access to the shared memory (ie, memories of other computing nodes) of the first processor 2110 .

In an embodiment, the first processor 2110 of the first computing node 2100 may be configured to access the first accelerator 2130 based on a predetermined interface. Alternatively, the first processor 2110 of the first computing node 2100 may be configured to access the accelerators 2230, 2330, 2430 of the other computing nodes 2200, 2300, 2400 via the network NT. . The first interface circuit 2140 may include a network switch (not shown) configured to control or support access to other accelerators of the first processor 2110 described above.

The second to fourth computing nodes 2200 to 2400 may perform operations similar to those of the above-described first computing node 2100 , and a detailed description thereof will be omitted.

In one embodiment, in the data center 2000, various applications may be executed. Various applications are configured to execute instructions for moving or copying data between the computing nodes 2100 to 2400, or instructions for combining, processing, and reproducing various information present on the computing nodes 2100 to 2400 can be configured to run In an embodiment, various applications are performed by any one of the plurality of computing nodes 2100 to 2400 included in the data center 2000, or various applications are performed between the plurality of computing nodes 2100 to 2400. It can be distributed and executed.

In one embodiment, the data center 2000 includes high-performance computing (HPC) (eg, finance, petroleum, materials science, weather forecasting, etc.), enterprise applications (eg, scale-out databases); It can be used for big data applications (eg NoSQL databases, in-memory replication, etc.).

In an embodiment, at least one of the plurality of computing nodes 2100 to 2400 may be an application server. The application server may be configured to run applications configured to perform various operations in the data center 2000 . At least one of the plurality of computing nodes 2100 to 2400 may be a storage server. The storage server may be configured to store data generated or managed in the data center 2000 .

In one embodiment, each of the plurality of computing nodes 2100 to 2400 or parts thereof included in the data center 2000 may exist in the same location or may exist in physically spaced locations, and may include wireless communication or wired communication. can communicate with each other through a network (NT) based on In an embodiment, the plurality of computing nodes 2100 to 2400 included in the data center 2000 may be implemented based on the same memory technology or different memory technologies.

Although not shown in the figure, at least some of the plurality of computing nodes 2100 to 2400 of the data center 2000 may communicate with an external client node (not shown) through a network NT or other communication interface (not shown). can communicate At least some of the plurality of computing nodes 2100 to 2400 may process a request (eg, data storage, data transmission, etc.) by itself according to a request of an external client node, or may process a request in another computing node .

In one embodiment, the number of the plurality of computing nodes 2100 to 2400 included in the data center 2000, the number of processors, the number of memories, and the number of accelerators included in each computing node are exemplary, and The scope is not limited thereto.

The above are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

100: computing system
110: host
120: accelerator
130: memory module

Claims (16)

In the method of operating an accelerator,
in response to the first interrupt, performing a cache flush operation;
performing an update section jump operation to jump a program counter to an update section after performing the cache flush operation;
performing a program update operation to write a compiled binary file to a memory module connected to the accelerator after the update section jump operation; and
after the program update operation, in response to a second interrupt, performing a start section jump operation to jump the program counter to the start section. The method of claim 1,
wherein the accelerator communicates with the host via a Peripheral Component Interconnect express (PCI-express) interface. The method of claim 1,
receiving the first interrupt from the host before the cache flush operation; and
after the program update operation, receiving the second interrupt from the host. The method of claim 1,
The binary file includes a section for a general program including the start section and the update section by a linker script. The method of claim 1,
The binary file is generated by compiling an accelerator program by the host. The method of claim 1,
The performing of the program update operation may include: reading the binary file from the host by a DMA engine included in the accelerator; and
and writing, by the DMA engine, the binary file to the memory module. 7. The method of claim 6,
Writing the binary file to the memory module comprises:
sending a write command and an address to the memory module through a command/address line; and
and transferring the binary file to the memory module via a data line. The method of claim 1,
The performing the cache flush operation includes writing data corresponding to a dirty state stored in a cache memory device included in the accelerator into the memory module. The method of claim 1,
and the first and second interrupts indicate a memory mapped I/O register (MMIO) write operation by the host. The method of claim 1,
The accelerator includes a field-programmable gate array (FPGA), a massively parallel processor array (MPPA), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a neural processing unit (NPU), a tensor processing unit (TPU), and A method comprising any one of Multi-Processor System-on-Chip (MPSoC). The method of claim 1,
while the program update operation is performed, the program counter loops in an infinite loop and waits. a host configured to perform a compile operation on the accelerator program to generate a binary file including an update section and a start section, and to transmit first and second interrupts; and
an accelerator configured to jump a program counter to the update section in response to the first interrupt and jump the program counter to the start section in response to the second interrupt;
The first interrupt indicates the start of the accelerator program update, and the second interrupt indicates the end of the accelerator program update. 13. The method of claim 12,
The computing system further comprising a memory module coupled to the accelerator and configured to store a binary file executed by the accelerator. 14. The method of claim 13,
and the accelerator is a DMA engine configured to read the binary file from the host and write the binary file to the memory module. 14. The method of claim 13,
The accelerator is:
a processor configured to execute the binary file; and
and a cache memory device configured to store data used by the processor and, in response to the first interrupt, flush data corresponding to a dirty state to the memory module. 13. The method of claim 12,
wherein the accelerator further comprises a reconstruction logic circuit configured to perform a machine learning algorithm, such as a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), or the like.

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