JP2008052389A - Programmable logic circuit update device, update method, data processor and network equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the error of new configuration data written in a memory by simple configurations. <P>SOLUTION: When new configuration data are written from a CPU 140 in a flash memory 130, a check logic circuit 114 configured as the internal circuit of an EPGA 110 reads the data, and calculates check sum data. Not only the new configuration data but also preliminarily calculated check sum data are recorded in the flash memory 130. Then, a check logic circuit 114 compares the preliminarily recorded check sum data with the check data calculated by reading the configuration data. Thus, it is possible to independently detect whether or not the new configuration data are correctly written in the flash memory 130. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for updating an internal circuit of a programmable logic circuit.

  In recent years, programmable logic circuits such as FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices) that can program internal circuits are the final products instead of ASICs (Application Specific Integrated Circuits) that are integrated circuits for specific applications. It is increasingly mounted as a key component.

  Among the programmable logic circuits described above, SRAM-type FPGAs generally download data called configuration data from a non-volatile memory at the time of startup, and configure the internal circuit based on this data ( See Patent Document 1 below). In such a programmable logic circuit, it is possible to easily modify or update the internal circuit by rewriting configuration data stored in the nonvolatile memory as needed. Hereinafter, the configuration in which the programmable logic circuit reads the configuration data to configure the internal circuit is referred to as “configuration”.

JP 2002-305438 A JP 2005-258996 A JP 2002-197900 A JP 2002-94369 A

  In a product equipped with such a programmable logic circuit, when the configuration data stored in the non-volatile memory is rewritten, if an error occurs during the writing for some reason, the FPGA is configured by the configuration after system startup. There was a problem that it would not function properly. In order to deal with such a problem, for example, after rewriting the configuration data, the CPU mounted on the product including the FPGA confirms the consistency of the configuration data after writing by a method such as a compare check. Can be considered. However, with such a method, the processing load on the CPU increases, which may affect the processing that the CPU originally executes, and may cause a reduction in processing speed, a delay in startup time, and the like. . In particular, in a system in which a plurality of FPGAs are connected to one CPU, such influence cannot be overlooked.

  In consideration of such a problem that occurs at the time of rewriting configuration data, the problem to be solved by the present invention is to detect an error in configuration data written in a memory with a simple configuration.

Based on the above problems, the programmable logic circuit update device of the present invention is configured as follows. That is,
A programmable logic circuit updating device for updating a circuit configuration of a programmable logic circuit,
A main logic circuit having a predetermined function is read based on the configuration data, and a check logic circuit for detecting an error in the configuration data stored in the memory, based on the configuration data. A programmable logic circuit to be realized;
A writing unit for writing new configuration data and error detection data determined based on the new configuration data to the memory;
If no error is detected in the new configuration data as a result of the error detection of the new configuration data by the check logic circuit, a circuit is connected to the programmable logic circuit based on the new configuration data. An update unit for updating the configuration,
The check logic circuit, when the new configuration data and the error detection data are written to the memory by the writing unit, reads the new configuration data from the memory and converts it into the configuration data. The error detection data is calculated based on the calculated error detection data, and the error detection data written to the memory by the writing unit is compared with the new configuration data written to the memory. The gist is to perform error detection.

The present invention can also be configured as a method for updating a programmable logic circuit as follows. That is, the update method of the present invention is:
An update method for updating a circuit configuration of a programmable logic circuit,
The programmable logic circuit reads configuration data stored in a predetermined memory, and based on the configuration data, detects an error in the main logic circuit having a predetermined function and the configuration data stored in the memory. The check logic circuit to perform,
A predetermined writing unit writes new configuration data and error detection data determined based on the new configuration data to the memory;
When the new configuration data and the error detection data are written to the memory by the writing unit, the check logic circuit reads the new configuration data from the memory and uses the new configuration data as the configuration data. Calculating error detection data based on the error detection data, comparing the calculated error detection data with the error detection data written to the memory, and performing error detection of the new configuration data written to the memory;
As a result, when no error is detected in the new configuration data as a result of error detection by the check logic circuit, the programmable logic circuit is updated based on the new configuration data. .

  In the programmable logic circuit updating apparatus and the updating method of the present invention, when new configuration data is written in the memory, the check logic circuit implemented in the programmable logic circuit confirms whether the configuration data is correctly written in the memory. can do. Therefore, even if the configuration of the program logic circuit is executed as the power is turned on again, it is possible to prevent the programmable logic circuit from becoming inoperable due to a write error to the memory or the like.

  Further, in the present invention, the check logic circuit for detecting configuration data errors is realized as an internal circuit of the programmable logic circuit. For this reason, error detection can be performed with a simple configuration without separately preparing new hardware.

  In the programmable logic circuit updating apparatus having the above configuration, a field programmable gate array (FPGA) can be adopted as the programmable logic circuit. In addition to the FPGA, another device that inputs the configuration data every time the power is turned on and performs the circuit configuration may be employed.

  In the above configuration, the error detection data written in the memory may be calculated and obtained in advance by the writing unit when the configuration data is written. In addition, it may be calculated in advance by another device that prepares configuration data.

In the programmable logic circuit update device configured as described above,
The check logic circuit causes the writing unit to write the new configuration data and the error detection data again when an error is detected in the new configuration data as a result of the error detection. It is good.

  With such a configuration, even if the writing of new configuration data to the memory fails, the writing process can be performed again, so that the accuracy of correctly writing the configuration data can be improved. .

In the programmable logic circuit update device configured as described above,
The error detection data is any of checksum data, CRC data, and parity data calculated from the new configuration data, or data obtained by combining two or more of these data can do.

  With such a configuration, it is possible to easily detect an error in the configuration data written in the memory using an existing error detection method. In particular, if error detection is performed using checksum data, a check logic circuit with relatively high error detection accuracy can be realized by a simple addition circuit or comparison circuit. As a result, an increase in the circuit scale of the programmable logic circuit can be suppressed.

  Furthermore, the present invention can be configured as a data processing device that includes the above-described programmable logic circuit updating device, and in which the main logic circuit performs predetermined data processing on input data and outputs it.

  With such a data processing device, for example, it is possible to perform processing for analyzing the destination address of the input network data and counting the number of transferred packets. In addition, it is also possible to perform various image processing on the input image data and video data, or to perform processing for outputting sound based on the input audio data. It is.

The present invention can also be configured as the following network device. That is, the network device of the present invention
A network device comprising a programmable logic circuit,
A plurality of line processing cards each having the programmable logic circuit, including a plurality of line ports, and transferring a network packet input from any of the line ports to another line port according to the destination of the network packet; ,
A CPU that performs overall management of each line processing card,
The programmable logic circuit of each line processing card reads configuration data from a predetermined memory mounted on each line processing card, and connects the line processing card and the CPU based on the configuration data. An interface logic circuit and a check logic circuit for detecting an error in the configuration data stored in the memory are realized,
The CPU
Means for writing new configuration data and error detection data determined based on the new configuration data to the memory mounted on each line processing card via the interface logic circuit;
If no error is detected in the new configuration data as a result of detecting the error in the new configuration data by the check logic circuit, a circuit is connected to the programmable logic circuit based on the new configuration data. Means for updating the configuration,
The check logic circuit, when the new configuration data and the error detection data are written to the memory by the CPU, reads the new configuration data from the memory and performs an error based on the configuration data. The detection data is calculated, and the error detection data newly written in the memory is detected by comparing the calculated error detection data with the error detection data written in the memory by the CPU. This is the gist.

  The network apparatus of the present invention adopts a mode in which one CPU and a plurality of line processing cards are connected via an interface logic circuit realized by a programmable logic circuit. According to such a network apparatus of the present invention, each line processing card can independently detect an error in new configuration data written in the memory by the check logic circuit included in each line processing card. . As a result, the processing burden on the CPU is reduced, and it is possible to suppress malfunctions after restart due to configuration data write errors.

Hereinafter, in order to further clarify the operation and effect of the present invention described above, embodiments and examples of the present invention will be described in the following order.
A. Embodiment:
(A1) Configuration of programmable logic circuit update device:
(A2) Operation when updating configuration data:
B. Example:
(B1) Configuration of network switch device:
(B2) Configuration of programmable logic circuit update device:
(B3) Operation when updating configuration data:

A. Embodiment:
(A1) Configuration of programmable logic circuit update device:
FIG. 1 is an explanatory diagram showing a schematic configuration of a programmable logic circuit update device 100 as an embodiment of the present invention. As shown in the figure, the programmable logic circuit update device 100 of this embodiment includes an FPGA 110, an update control circuit 120, a flash memory 130, a CPU 140, and a RAM 150. The FPGA 110 of the present embodiment corresponds to the “programmable logic circuit” of the present application, the flash memory 130 corresponds to “memory”, and the CPU 140 and the update control circuit 120 correspond to “write unit” and “update unit”, respectively.

  The FPGA 110 is connected to the update control circuit 120 by a control signal line 122, a data signal line 124, and a request signal line 126. A flash memory 130 is connected to the update control circuit 120 via a flash interface 135. A CPU 140 is connected to the FPGA 110 and the update control circuit 120 via a CPU bus 145. A RAM 150 is connected to the CPU 140 via a memory bus 155.

  The FPGA 110 is a programmable logic circuit having a scale of several hundred thousand gates, for example, and includes a number of circuits such as an LUT (Look Up Table), a selector, and a flip-flop. The contents of the LUT are held by a volatile SRAM. Therefore, every time the power is turned on, data called configuration data is input from an external memory, thereby configuring (configuring) an internal logic circuit. In this embodiment, the main function logic circuit 112 and the check logic circuit 114 are configured as internal circuits by this configuration.

  The main function logic circuit 112 is a main logic circuit that exhibits a predetermined function in the operation state of the FPGA 110. Various functions can be applied to the functions realized by the main function logic circuit 112 according to the device including the programmable logic circuit updating device 100. For example, when the programmable logic circuit update device 100 is mounted on a network device, it is configured as a logic circuit that counts the number of packet transfers as MIB (Management Information Base) information, a logic circuit that learns a MAC address for each line, or the like. can do. Further, when mounted on video equipment or audio equipment, it can also be configured as a circuit that performs image processing and audio output. On the other hand, the check logic circuit 114 is a logic circuit that performs error detection of data after writing when the CPU 140 writes new configuration data into the flash memory 130. Details of the processing performed by the check logic circuit 114 will be described later.

  The update control circuit 120 has a function of causing the FPGA 110 to perform configuration when the programmable logic circuit update device 100 is turned on or receives an instruction from the CPU 140, and new configuration data transferred from the CPU 140 to the flash memory. And a function of relaying to 130. The update control circuit 120 can be configured by, for example, an FPGA different from the FPGA 110, a CPLD, a microcomputer, or the like.

  The update control circuit 120 instructs the FPGA 110 to perform configuration by driving the control signal line 122 when the programmable logic circuit update device 100 is powered on or receives an instruction from the CPU 140. Upon receiving this command, the FPGA 110 reads the configuration data transferred from the flash memory 130 by the update control circuit 120 through the data signal line 124, and configures internal circuits (main function logic circuit 112 and check logic circuit 114).

  The CPU 140 has a function of updating configuration data stored in the flash memory 130. This update process is performed by executing a predetermined program stored in the RAM 150. New configuration data is stored in the RAM 150 connected to the CPU 140. This new configuration data also includes data for realizing the check logic circuit 114. The CPU 140 reads this data via the memory bus 155 and writes it to the flash memory 130 via the update control circuit 120. New configuration data stored in the RAM 150 can be input from a medium such as a network, a memory card, or a CD-ROM.

(A2) Operation when updating configuration data:
FIG. 2 is a flowchart showing an operation flow when the configuration data is updated in the programmable logic circuit update device 100 of the present embodiment.

  First, the CPU 140 reads new configuration data from the RAM 150 and rewrites the configuration data in the flash memory 130 via the update control circuit 120 (step S100). At this time, the CPU 140 calculates new checksum data as error detection data by reading new configuration data from the RAM 150 and summing the values of the data. Then, this checksum data is written into the flash memory 130 together with new configuration data (step S110). In this process, checksum data calculated in advance may be read from the RAM 150 and written into the flash memory 130.

  When the rewriting of the configuration data and the checksum data is completed, the CPU 140 instructs the check logic circuit 114 in the FPGA 110 to detect an error in the new configuration data via the CPU bus 145 (step S120). Upon receiving this command, the check logic circuit 114 drives the request signal line 126 to request the update control circuit 120 to transfer new configuration data and checksum data (step S130). Upon receiving such a request, the update control circuit 120 reads the configuration data and checksum data from the flash memory 130 and transfers them to the check logic circuit 114 via the data signal line 124 (step S140). At this time, the update control circuit 120 does not drive the control signal line 122 so that the FPGA 110 does not start normal configuration.

  When the check logic circuit 114 receives new configuration data and checksum data, the check logic circuit 114 calculates checksum data from the total value of each data constituting the received configuration data, and the checksum data thus calculated and the data The checksum data input via the signal line 124 is compared (step S150). If the values are different as a result of the comparison, an error is detected. When error detection is performed in this way, the check logic circuit 114 notifies the CPU 140 of the result of error detection (step S160).

  The CPU 140 receives the error detection result, and if the result is “no error” (step S170: Yes), the CPU 140 gives an instruction to the update control circuit 120 to configure the FPGA 110 (step S180). In this way, the rewritten configuration data is read from the flash memory 130, and new logic circuits (new main function logic circuit 112 and check logic circuit 114) are configured in the FPGA 110. On the other hand, if the result of error detection is “with error” (step S170: No), the CPU 140 returns the process to step S100 again, and rewrites the configuration data again. By doing so, new configuration data is written in the flash memory 130 until there is no error in the new configuration data. Note that the timing of the configuration executed in step S180 does not have to be immediately after it is determined as “no error” in step S170. For example, it can be executed when the main function logic circuit 112 stops functioning or when the entire apparatus is restarted.

  According to the present embodiment described above, when new configuration data is written in the flash memory 130 during the operation of the FPGA 110, the check logic circuit 114 can check whether or not the data is correctly written. . Therefore, it is possible to prevent an operation failure from occurring in the FPGA 110 in the configuration performed at the next power-on or the like due to a configuration data write error.

  In this embodiment, the error detection of the configuration data written in the flash memory 130 is performed by the check logic circuit 114 configured as an internal circuit of the FPGA 110. Therefore, the apparatus can be configured at low cost without separately preparing hardware dedicated to error detection. In particular, in this embodiment, the check logic circuit 114 is realized by a relatively simple addition circuit or comparison circuit because the check sum data is used to check whether the configuration data has been correctly written. Can do. Accordingly, an increase in the circuit scale of the FPGA 110 can be suppressed, so that an increase in cost associated with adding a check logic circuit to the FPGA 110 can be suppressed.

  In the operation at the time of rewriting the configuration data, when an error is detected in the rewritten configuration data, the CPU 140 writes new configuration data in the flash memory 130 again. This rewriting may be limited in number of times. For example, when writing fails three times in succession, a warning sound is emitted or a predetermined LED blinks or lights up to notify the administrator that writing cannot be performed normally. Also good. By doing so, it becomes possible to notify the administrator that normal writing cannot be performed due to a hardware defect or the like.

B. Example:
(B1) Configuration of network switch device:
Next, based on the above-described embodiment, more specific examples of the present invention will be described.
FIG. 3 is an explanatory diagram illustrating a schematic configuration of the network switch device 200 including the programmable logic circuit update device 540 as an embodiment. The network switch device 200 is a so-called chassis type network switch device, and includes a CPU card 300, a switch processing card 400, and a plurality of line processing cards 500 therein. In this embodiment, it is assumed that the line processing card 500 is provided with a programmable logic circuit update device 540. However, the CPU card 300 and the switch processing card 400 may be provided with a programmable logic circuit updating device.

  The CPU card 300 is a card for performing overall control of the network switch device 200. The CPU card 300 includes a CPU 310, a RAM 330, a ROM 340, and an FPGA 320 that functions as a CPU interface. Firmware is stored in the ROM 340, and the CPU 310 performs various processes by developing the firmware in the RAM 330 and executing it. As the processing to be executed, for example, update processing of circuit contents of the FPGA 520 provided in the line processing card 500, acceptance of setting operation from an external device or operation panel (not shown), maintenance management of a routing table, SNMP (Simple Network Management Protocol) ) Protocol processing, processing for enabling / disabling each line port 510 provided in the line processing card 500, setting the line speed, and the like.

  The RAM 330 of the CPU card 300 stores new configuration data for updating the circuit contents of the FPGA 520 mounted on each line processing card 500. The configuration data can be input to the RAM 330 via a medium such as a network, a memory card, or a CD-ROM, for example.

  The FPGA 320 mounted on the CPU card 300 is connected to the FPGA 420 of the switch processing card 400 and the FPGA 520 of each line processing card 500 by the CPU bus 360. As described above, each of these FPGAs functions as an interface circuit that mediates communication with the CPU 140.

  The line processing cards 500 are cards each having a function as a switching hub. The line processing card 500 includes a plurality of line ports 510, a line processing LSI 530, an FPGA 520 that functions as a CPU interface, and a programmable logic circuit update device 540. The line processing LSI 530 analyzes the MAC address of the packet input from each line port 510 and transfers the packet to the optimum line port 510. The line processing LSI 530 is connected to the switch LSI 410 of the switch processing card 400 via a broadband communication path 460. If the input packet is a packet addressed to a port that is not managed by the line processing LSI 530, the line processing LSI 530 transfers the packet to the switch processing card 400 through the communication path 460.

  The switch processing card 400 is a card for transferring a packet transferred from the line processing card 500 to another line processing card 500. The switch processing card 400 includes a switch LSI 410 and an FPGA 420 that functions as a CPU interface. A line processing LSI 530 of each line processing card 500 is connected to the switch LSI 410. When receiving a packet transfer from a certain line processing card 500, the switch LSI 410 has a function of analyzing the destination of the packet and transferring the packet to the line processing card 500 suitable for the destination.

(B2) Configuration of programmable logic circuit update device:
FIG. 4 is an explanatory diagram showing a detailed configuration of the programmable logic circuit updating device 540 included in the line processing card 500. The programmable logic circuit update device 540 includes an FPGA 520, an update control circuit 542, and a flash memory 544.

  The FPGA 520 includes a CPU interface logic circuit 522 and a check logic circuit 524 as internal circuits. The CPU interface logic circuit 522 is an interface circuit for connecting the CPU 140 of the CPU card 300 and the line processing card 500. The CPU interface logic circuit 522 includes a 512-byte built-in RAM 523 as a buffer area. The check logic circuit 524 is a circuit for detecting an error in the configuration data stored in the flash memory 544, like the check logic circuit 114 of the above-described embodiment. The check logic circuit 524 includes a register 525 for receiving various commands from the CPU 310 and storing the result of error detection. The CPU interface logic circuit 522 and the check logic circuit 524 are configured by the FPGA 520 reading configuration data stored in the flash memory 544.

  The update control circuit 542 has a function equivalent to that of the update control circuit 120 of the above-described embodiment. That is, when the power of the line processing card 500 is turned on, a function for causing the FPGA 520 to perform configuration using the control signal line 552 and new configuration data transferred from the CPU card 300 via the CPU interface logic circuit 522, A function of relaying to the flash memory 544. The update control circuit 542 of this embodiment is configured by a CPLD that is a nonvolatile programmable logic circuit.

  The CPU interface logic circuit 522 and the update control circuit 542 are connected by a local bus 551. The check logic circuit 524 and the update control circuit 542 are connected by a data signal line 553, a request signal line 554, and a response signal line 555. The update control circuit 542 and the flash memory 544 are connected by a flash interface 556.

(B3) Operation when updating configuration data:
FIG. 5 is a flowchart showing an operation flow when the configuration data is updated in the programmable logic circuit update device 540 of the present embodiment.

  First, the CPU 310 mounted on the CPU card 300 erases the configuration data before update stored in the flash memory 544 (step S200).

  Next, the CPU 310 divides the new configuration data stored in the RAM 340 on the CPU card 300 into units of 512 bytes, and transmits the divided data to the CPU interface logic circuit 522 of the line processing card 500. Upon receiving this data transfer, the CPU interface logic circuit 522 once buffers the built-in RAM 523 and sequentially writes it in the flash memory 544 (step S210). In this embodiment, it is assumed that checksum data calculated in advance from this configuration data is added to the head of the new configuration stored in the RAM 340.

  When the CPU interface logic circuit 522 determines that the writing of 512-byte data has been completed (step S220: Yes), it notifies the CPU 310 accordingly. Upon receiving this notification, the CPU 310 determines whether or not writing of all data has been completed (step S230). If not completed (step S230: No), the CPU interface logic circuit 522 transfers the next 512-byte data. Transfer to and write.

  In step S230, when the CPU 310 determines that all the data has been written (step S230: Yes), the size of the new configuration data that has been written is set in the register of the check logic circuit 524. (Step S240). Upon receiving this setting, the check logic circuit 524 drives the request signal line 554 to request the update control circuit 542 to transfer configuration data for the size set in step S240 (step S250). ). Upon receipt of this request, the update control circuit 542 drives the response signal line 555 as soon as the preparation for transferring the configuration data is completed, and notifies the check logic circuit 524 that data transfer will be started. After such notification, the update control circuit 542 reads the configuration data from the flash memory 544 and transfers new configuration data to the check logic circuit 524 via the data signal line 553 (step S260). Upon receiving this data transfer, the check logic circuit 524 executes configuration data error detection (step S270).

  As described above, checksum data calculated in advance is added to the head of new configuration data stored in the flash memory 544. Accordingly, when the check logic circuit 524 receives the transfer of the configuration data from the update control circuit 542, first, the check logic circuit 524 separates the checksum data from the configuration data and holds the value. Then, the values of the configuration data received through the data signal line 553 are added. Then, it is checked whether the checksum data calculated from the total matches the value of the stored checksum data. If these values match, the configuration data is correctly written in the flash memory 544.

  When the error detection of the rewritten configuration data is completed by the above processing, the check logic circuit 524 writes the error detection result in the register 525 (step S280), and notifies the CPU 310 that the error detection is completed.

  When the CPU 310 receives a notification that the error detection is completed from the check logic circuit 524, the CPU 310 reads the detection result recorded in the register 525 (step S290). As a result of this reading, if it is determined that there is no error in the configuration data (step S300: Yes), an instruction is given to the update control circuit 542 to cause the FPGA 520 to be configured (step S310). On the other hand, if it is determined that there is an error in the configuration data (step S300: No), the configuration data is not correctly written in the flash memory 544. Therefore, the processing is restarted from step S200. . By doing so, the above-described series of processing is repeatedly executed until new configuration data is correctly written in the flash memory 544.

  In the present embodiment, similarly to the above-described embodiment, the number of rewrites to the flash memory 544 may be limited when new configuration data cannot be written correctly. The configuration executed in step S310 can be executed when the CPU interface logic circuit 522 stops functioning or when the line processing card 500 is turned on again. If the check logic circuit 524 detects an error in step S270 and the determination result is “no error”, each line processing card 500 autonomously waits for an instruction from the CPU 310. The FPGA 520 can be configured.

  According to the embodiment described above, the plurality of line processing cards 500 included in the network switch device 200 each independently check for new configuration data. Therefore, the processing load on the CPU 310 is reduced. As a result, since the CPU 310 is released from the configuration data update process at an early stage, the CPU 310 can quickly return to a process that should be executed by itself (for example, SNMP protocol process, accepting a setting operation). .

  In the present embodiment, each line processing card 500 does not check the rewritten configuration data, but each line processing card 500 autonomously checks the rewritten configuration data. It is possible to immediately update the FPGA 520 included in the self without waiting for the check or the like. Therefore, the update of the line processing card 500 itself becomes faster, and it is possible to quickly cope with a situation where the actual operation of the network switch device 200 is hindered unless the FPGA 520 is updated immediately.

  In this embodiment, the configuration data is transferred every 512 bytes by using the built-in RAM 523 provided in the CPU interface logic circuit 522. Therefore, the CPU bus 360 is not occupied for a long time when data is rewritten. Therefore, it is possible to efficiently write to the flash memory 544 while suppressing the influence on other processes using the CPU bus 360.

  Also in this embodiment, since it is possible to check whether new configuration data has been correctly written during the operation of the FPGA 520, the FPGA 520 will operate when the power is turned on next time due to a configuration data write error. It can be prevented from becoming defective.

  As mentioned above, although embodiment and Example of this invention were described, it cannot be overemphasized that this invention is not limited to these examples, and can take a various structure in the range which does not deviate from the meaning. For example, in the above-described embodiments and examples, checksum data is used for configuration data error detection. In addition, for example, CRC data and parity data can be used. It is also possible to detect errors by combining two or more of checksum data, CRC data, parity data, and the like.

It is explanatory drawing which shows schematic structure of the programmable logic circuit update apparatus 100 as embodiment. It is a flowchart which shows the flow of operation | movement at the time of updating configuration data in embodiment. It is explanatory drawing which shows schematic structure of the network switch apparatus 200 provided with the programmable logic circuit update apparatus 540 as an Example. It is explanatory drawing which shows the detailed structure of the programmable logic circuit update apparatus 540 with which the line processing card 500 is provided. It is a flowchart which shows the flow of operation | movement at the time of updating configuration data in an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Programmable logic circuit update apparatus 110 ... FPGA
DESCRIPTION OF SYMBOLS 112 ... Main function logic circuit 114 ... Check logic circuit 120 ... Update control circuit 122 ... Control signal line 124 ... Data signal line 126 ... Request signal line 130 ... Flash memory 135 ... Flash interface 140 ... CPU
145 ... CPU bus 150 ... RAM
155 ... Memory bus 200 ... Network switch device 300 ... CPU card 310 ... CPU
320 ... FPGA
330 ... RAM
340 ... ROM
360 ... CPU bus 400 ... switch processing card 410 ... switch LSI
420 ... FPGA
460 ... Communication channel 500 ... Line processing card 510 ... Line port 520 ... FPGA
522: CPU interface logic circuit 523: Built-in RAM
524: Check logic circuit 525: Register 530: Line processing LSI
540 ... Programmable logic circuit update device 542 ... Update control circuit 544 ... Flash memory 551 ... Local bus 552 ... Control signal line 553 ... Data signal line 554 ... Request signal line 555 ... Response signal line 556 ... Flash interface

Claims (7)

A programmable logic circuit updating device for updating a circuit configuration of a programmable logic circuit,
A main logic circuit having a predetermined function is read based on the configuration data, and a check logic circuit for detecting an error in the configuration data stored in the memory, based on the configuration data. A programmable logic circuit to be realized;
A writing unit for writing new configuration data and error detection data determined based on the new configuration data to the memory;
If no error is detected in the new configuration data as a result of the error detection of the new configuration data by the check logic circuit, a circuit is connected to the programmable logic circuit based on the new configuration data. An update unit for updating the configuration,
The check logic circuit, when the new configuration data and the error detection data are written to the memory by the writing unit, reads the new configuration data from the memory and converts it into the configuration data. The error detection data is calculated based on the calculated error detection data, and the error detection data written to the memory by the writing unit is compared with the new configuration data written to the memory. Programmable logic circuit update device that performs error detection. The programmable logic circuit updating device according to claim 1,
The check logic circuit causes the writing unit to write the new configuration data and the error detection data again when an error is detected in the new configuration data as a result of the error detection. Logic circuit update device. The programmable logic circuit updating device according to claim 1 or 2,
The error detection data is any one of checksum data, CRC data, and parity data calculated from the new configuration data, or data obtained by combining two or more of these data. Programmable logic Circuit update device. The programmable logic circuit update device according to any one of claims 1 to 3,
The programmable logic circuit is a field programmable gate array. An update method for updating a circuit configuration of a programmable logic circuit,
The programmable logic circuit reads configuration data stored in a predetermined memory, and based on the configuration data, detects an error in the main logic circuit having a predetermined function and the configuration data stored in the memory. The check logic circuit to perform,
A predetermined writing unit writes new configuration data and error detection data determined based on the new configuration data to the memory;
When the new configuration data and the error detection data are written to the memory by the writing unit, the check logic circuit reads the new configuration data from the memory and uses the new configuration data as the configuration data. Calculating error detection data based on the error detection data, comparing the calculated error detection data with the error detection data written to the memory, and performing error detection of the new configuration data written to the memory;
An update method for causing the programmable logic circuit to update a circuit configuration based on the new configuration data when no error is detected in the new configuration data as a result of error detection by the check logic circuit. A data processing device comprising the programmable logic circuit updating device according to any one of claims 1 to 4,
The data processing device, wherein the main logic circuit performs predetermined data processing on input data and outputs the processed data. A network device comprising a programmable logic circuit,
A plurality of line processing cards each having the programmable logic circuit, including a plurality of line ports, and transferring a network packet input from any of the line ports to another line port according to the destination of the network packet; ,
A CPU that performs overall management of each line processing card,
The programmable logic circuit of each line processing card reads configuration data from a predetermined memory mounted on each line processing card, and connects the line processing card and the CPU based on the configuration data. An interface logic circuit and a check logic circuit for detecting an error in the configuration data stored in the memory are realized,
The CPU
Means for writing new configuration data and error detection data determined based on the new configuration data to the memory mounted on each line processing card via the interface logic circuit;
If no error is detected in the new configuration data as a result of detecting the error in the new configuration data by the check logic circuit, a circuit is connected to the programmable logic circuit based on the new configuration data. Means for updating the configuration,
The check logic circuit, when the new configuration data and the error detection data are written to the memory by the CPU, reads the new configuration data from the memory and performs an error based on the configuration data. The detection data is calculated, and the error detection data newly written in the memory is detected by comparing the calculated error detection data with the error detection data written in the memory by the CPU. Network device.

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