CN113923173B - Quick starting recovery method for data surface of network switching equipment - Google Patents
Quick starting recovery method for data surface of network switching equipment Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000011084 recovery Methods 0.000 title claims description 16
- 230000005540 biological transmission Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000013479 data entry Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005059 dormancy Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/557—Error correction, e.g. fault recovery or fault tolerance
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Abstract
The application discloses a method for quickly starting and recovering a data surface of network switching equipment, which comprises the steps of powering on or resetting the network switching equipment, sending pre-stored configuration data to a switching chip in the network switching equipment through fpga, so that the switching chip loads the configuration data into a register and a table entry in the switching chip, starting the data surface, starting a control surface, and starting the data surface before the control surface by adopting a mode of separating the control surface from the data surface and starting the data surface in parallel. Before the data surface is started, the data surface can finish data forwarding of two layers or three layers, and the quick and stable starting and recovering of the data surface of the network switching equipment are realized under the condition of low power consumption.
Description
Technical Field
The application belongs to the technical field of computers, and particularly relates to a method for quickly starting a data plane of network switching equipment.
Background
Under the application scene that the requirements on high reliability and fast fault recovery of equipment are strict, the network switching equipment needs to have the capability of fast starting and recovering the forwarding of the data surface under the condition of not being damaged physically, and the network switching equipment needs to be capable of fast starting and recovering the forwarding of the data surface when the network switching equipment fails due to electromagnetic interference or network attack so as to timely transmit important information to the proprietary network where the network switching equipment is located.
At present, the rapid starting and fault recovering technologies of network switching equipment at home and abroad mainly have three technical schemes:
(1) Standby technology: when the system is shut down, the cpu registers, the related registers of the network chip, and other information to be saved are first saved in ram (random access memory ) by the system. And then power is turned off to all devices except ram. When the system is started next time, the system is quickly restored to a state before shutdown according to the information stored in the ram. This technique can restore the system within one second, but still needs to supply power to necessary devices such as ram, and the power consumption is high.
(2) Dormancy technology: when the system is started, bootloader is started, related hardware equipment of the dormant system is initialized, then snapshot images are copied from flash memory to ram, and the system is started quickly without normal starting flow. The technology can not only accelerate the starting speed, but also overcome the defect of high power consumption of the standby technology. However, the method of creating a fast image by creating a fast image from the cpu register, the network chip register, and ram information after the operating system and the application program are started is a major technical difficulty. Some basic technologies have been developed but are still immature.
(3) Routine start-up and fault recovery optimization: the system boot is generally divided into firmware, kernel, and application boot. Optimization is performed for the more time-consuming part. At present, many aspects of rc script optimization, kernel compression algorithm optimization, file system optimization and the like are studied. When a fault occurs, the method can also be used for realizing quick recovery, and the starting of the traditional switching equipment generally needs to wait for the completion of the starting of the control plane and can recover the forwarding capacity of the data plane after the forwarding table is re-regenerated, so that the data plane forwarding capacity is slowly recovered.
Therefore, a low-power-consumption method for quickly and stably starting and recovering the data plane of the network switching device is needed.
Disclosure of Invention
The application aims to provide a method for quickly starting and recovering a data surface of network switching equipment, which realizes quick and stable starting and recovering of the data surface of the network switching equipment under the condition of low power consumption.
In one aspect, the present application provides a method for quickly starting and recovering a data plane of a network switching device, where the method includes:
s1, powering on or resetting the network switching equipment;
s2, sending the pre-stored configuration data to a switching chip in the network switching equipment through fpga, so that the switching chip loads the configuration data into a register and an entry in the switching chip.
Further, the configuration data is specifically the configuration data required by the exchange chip to forward the data, the configuration data is pre-stored in the flash memory, and the configuration data specifically comprises inherent configuration firmware and dynamic configuration firmware.
Further, the inherent configuration firmware is specifically firmware meeting the basic function configuration of the exchange chip, and the dynamic configuration firmware is specifically firmware of dynamic expansion configuration in the system operation process.
Further, the step S2 specifically includes the following sub-steps:
s21, reading the configuration data to a configuration buffer area inside the fpga through the fpga;
s22, sequentially detecting whether each configuration in the dynamic configuration firmware is an ending mark through fpga, if so, ending the loading of the dynamic configuration firmware, executing step S24, and if not, executing step S23;
s23, judging whether the corresponding configuration is effective, if so, sending the corresponding configuration to the exchange chip, and if not, discarding the current corresponding configuration;
s24, the inherent configuration firmware is sent to the exchange chip through fpga.
Further characterized in that said configuration data is constituted in particular by values of registers.
Further, each piece of configuration data specifically includes a control bit, a node number, an intra-node offset, and a value of the configuration data, where the control bit specifically is control information describing the configuration data, a register of the switch chip is divided into various areas, each area is a node, the node number specifically is a node address corresponding to the configuration register, the intra-node offset specifically is an offset address in the node, the intra-node offset and the node number together form a globally unique address of the register, and the value of the configuration data is a value of a register or an entry of the switch chip addressed according to the control bit, the node number, and the node offset.
Further, between the step S1 and the step S2, further includes:
a1, after the network switching equipment is powered on or reset, sending a data transmission recovery instruction to the fpga through a bottom data plane quick recovery component, so that the fpga sends pre-stored configuration data to a switching chip in the network switching equipment.
Further, the control plane is started at the same time of starting the data plane.
Further, the control surface is started, and the method specifically comprises the following sub-steps:
b1, starting a boot loader;
b2, starting a real-time operating system;
b3, starting a root file system;
and B4, operating a protocol module.
Compared with the prior art, the application has the following beneficial effects:
(1) The application transmits the pre-stored configuration data to the exchange chip in the network exchange equipment through fpga by powering on or resetting the network exchange equipment, so that the exchange chip loads the configuration data to a register and a table entry in the exchange chip, and starts the control surface while starting the data surface, and the data surface can be started before the control surface by adopting a mode of separating the control surface from the data surface and starting the control surface in parallel. Before the data surface is started, the data surface can finish data forwarding of two layers or three layers, and the quick and stable starting and recovering of the data surface of the network switching equipment are realized under the condition of low power consumption.
(2) The configuration of the exchange chip is stored in the flash memory in the form of firmware. When the equipment is in fault restart, the prior fpga reads the configuration into the configuration buffer zone arranged in the equipment, and the internal time sequence of the fpga is far faster than that of the peripheral equipment, so that the loading speed of the firmware configuration can be increased.
Drawings
Fig. 1 is a schematic flow chart of a method for quickly starting and recovering a data plane of a network switching device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The application provides a method for quickly starting and recovering network switching equipment, as shown in fig. 1, which is a flow diagram of the method for quickly starting and recovering the data surface of the network switching equipment, and comprises the following steps:
and step S1, powering on or resetting the network switching equipment.
And S2, sending the pre-stored configuration data to a switching chip in the network switching equipment through fpga, so that the switching chip loads the configuration data into a register and an entry in the switching chip.
In the embodiment of the present application, between the step S1 and the step S2, the method further includes:
a1, after the network switching equipment is powered on or reset, sending a data transmission recovery instruction to the fpga through a bottom data plane quick recovery component, so that the fpga sends pre-stored configuration data to a switching chip in the network switching equipment.
In a specific application scenario, a data surface recovery is required when a problem occurs in a hardware power-on reset or system operation process, after a bottom data surface fast recovery firmware component sends a data transmission recovery instruction to fpga or sends a data surface transmission fast recovery signal to fpga in a hardware mode, then fpga takes out configuration data from a flash memory chip, and sends the configuration data to the exchange chip through a special configuration channel of the exchange chip, fpga (Field Programmable Gate Array, field programmable logic gate array), wherein fpga devices belong to a semi-custom circuit in an application-specific integrated circuit, are programmable logic arrays, and can effectively solve the problem that the number of original device gate circuits is small.
In the embodiment of the application, the configuration data is specifically the configuration data required by the forwarding data of the exchange chip, the configuration data is pre-stored in the flash memory, the configuration data specifically comprises inherent configuration firmware and dynamic configuration firmware, and the configuration data specifically consists of the values of the registers.
The inherent configuration firmware is specifically the firmware meeting the basic function configuration of the exchange chip, and the dynamic configuration firmware is specifically the firmware of dynamic expansion configuration in the system operation process.
In a specific application scenario, the data plane is started after the system is powered on or reset. The configuration data forwarded by the two layers and the three layers required by the exchange chip is stored in the flash in the form of firmware (the configuration data firmware is divided into inherent configuration firmware and dynamic configuration firmware), wherein the inherent configuration firmware is the configuration meeting the basic function configuration of the exchange chip, such as clock, pcie, serdes, two layers, three layers and the like, and the configuration is basically unchanged once the hardware design of the equipment is determined. The dynamic configuration firmware refers to the configuration of dynamic expansion in the running process of the system, and the area division of the flash can be simply divided into an inherent configuration firmware area and a dynamic configuration firmware area.
In the embodiment of the present application, the step S2 specifically includes the following sub-steps:
s21, reading the configuration data to a configuration buffer area inside the fpga through the fpga;
s22, sequentially detecting whether each configuration in the dynamic configuration firmware is an ending mark through fpga, if so, ending the loading of the dynamic configuration firmware, executing step S24, and if not, executing step S23;
s23, judging whether the corresponding configuration is effective, if so, sending the corresponding configuration to the exchange chip, and if not, discarding the current corresponding configuration;
s24, the inherent configuration firmware is sent to the exchange chip through fpga.
In a specific application scenario, the configuration firmware sent by Fpga is in the form of entries, each configuration is in a fixed format, after the switch chip passes through the configuration path, the validity judgment in S23 means that the switch chip checks the format of the received configuration data, and if the format is inconsistent, the configuration firmware is directly discarded from the internal link of the switch chip.
When the system is powered on or reset, the fpga reads configuration data in an inherent configuration firmware area in the flash, stores the configuration data in an internal buffer area of the fpga, and then the exchange chip reads the configuration data in the inherent configuration firmware from the buffer area of the fpga through an active configuration channel (a communication bus clock between the exchange chip and the fpga is provided by the exchange chip). After the exchange chip reads the configuration data in the inherent configuration firmware through the special configuration channel, the configuration data is configured into an internal register or table entry through the logic inside the chip.
The dynamic configuration firmware is dynamically changed, the configuration data is determined by the cpu, and the cpu periodically writes some important configurations into the dynamic configuration firmware area of the flash during the operation process. The loading of the dynamic configuration firmware is accomplished by switching another dedicated configuration channel of the chip, the configuration channel is a passive channel which is used as a slave on a communication bus with the fpga, and the clock on the bus is provided by the fpga. With respect to the inherent firmware and the dynamic configuration firmware, the timing of the configuration is determined in conjunction with the timing of the cold reset of the switch chip.
That is, when the system is powered on or reset, the fpga controls the reset timing of the autonomous switching chip, and before resetting the switching chip, the fpga reads the dynamic configuration firmware from the flash to the self-allocated dynamic configuration buffer, and after waiting for the configuration of the inherent firmware to be completed, configures the dynamic configuration firmware. When the dynamic configuration firmware is configured, firstly, the configuration data read from the dynamic configuration firmware buffer area is detected, and if the configuration data is an end mark, the loading of the dynamic configuration firmware is ended. If the configuration data is not the dynamic configuration ending mark, the validity of the configuration data is detected, if the configuration data is valid, the configuration data is sent to a passive configuration channel of the autonomous switching chip, otherwise, the next configuration is continuously read from the dynamic configuration firmware area.
In the embodiment of the application, each piece of configuration data specifically comprises a control bit, a node number, an intra-node offset and a value of the configuration data, wherein the control bit specifically is control information describing the configuration data, a register of the switching chip is divided into various areas, each area is a node, the node number specifically is a node address corresponding to the configuration register, the intra-node offset specifically is an offset address in the node, the intra-node offset and the node number together form a globally unique address of the register, and the value of the configuration data is a value of a register or an entry of the switching chip addressed according to the control bit, the node number and the node offset.
In a specific application scenario, the flash memory chip stores configuration data of the exchange chip, including configuration of registers and table entries of two or three layers. Depending on the nature of the switch chip, all configuration data is composed of register values, and even table entry data is indirectly configured through registers. The format of the configuration data area is composed of data register configuration values one by one, and each configuration data is composed of four parts:
control bit: 8-bit data for describing some control information of the configuration data. Currently only three values are valid, 0 representing the present piece of data valid, 255 representing the data invalid, 230 representing the configuration end flag.
Node number: 8-bit data. The registers of the switch chip are divided into regions, each region being referred to as a node. The node number describes the node address to which the configuration register corresponds.
Intra-node offset: 16 bits of data. The offset address within the node, together with the node number, constitutes the globally unique address of the register.
Values of configuration data: the value of a register or entry of the switch chip that is addressed based on the control bit, node number, node offset is also the value of a 64-bit register.
The fpga reads the configuration data of the configuration area in the flash in sequence, determines that the configuration data is a dedicated configuration channel for sending up the exchange chip according to different values of the control field in the configuration data entry, or directly discards the configuration data (when the configuration needs to be delayed, some invalid configuration may need to be added in the flash, and the invalid configuration is only used for delay processing), and can determine whether the configuration is loaded completely according to the control bit of the configuration data.
In summary, that is, after the system is powered on or reset, the data plane is started. The configuration data forwarded by the two layers and the three layers required by the exchange chip are stored in the flash in the form of firmware (the configuration data firmware is divided into inherent configuration firmware and dynamic configuration firmware), the fpga reads the configuration data required by the exchange chip from the flash and stores the configuration data into a configuration data buffer area in the exchange chip, and the inherent configuration data is actively read by the exchange chip through an active configuration channel; while the dynamic configuration data has a passive configuration channel (fpga and exchange chip can both configure the channel rate of the configuration channel, and the interface is made into a special channel, so that when a general device is used, the general device rate is prevented from being limited, and the purpose is that the configuration data can quickly reach the exchange chip), after the exchange chip obtains the configuration data, the configuration data is loaded into its own register and table item by its internal logic
In the embodiment of the application, the data plane is started, the control plane is started at the same time, and the control plane is started, which specifically comprises the following sub-steps:
b1, starting a boot loader;
b2, starting a real-time operating system;
b3, starting a root file system;
and B4, operating a protocol module.
Specifically, the control plane is started approximately through bootloader, kernel, real-time operating system, rootfs, root file system and running protocol module. The outline of each stage of the starting process of the control plane of the network switching equipment is described as follows:
the implementation of bootloader relies heavily on the architecture of the hardware. In general, bootloader is divided into two stages, stage1 and stage2, stage1 mainly completes hardware initialization, including cpu main frequency setting, closing dcache, icache can be opened or closed, watchdog closing, initializing memory, setting stack pointer, resetting stage2 code into memory, preparing running environment for stage2 stage of bootloader, and jumping to stage2 c entry point; stage2 mainly initializes the hardware used in this stage (e.g., mmu, etc.), detects the mapping mechanism of virtual memory and physical memory, copies the kernel and root file system into memory, sets the kernel start-up parameters, and finally calls the kernel.
The kernel is mainly responsible for completing management of resources such as memory, processes, files, equipment, networks and the like, and forms an operating system with various tools.
The rootfs root file system is a method and a data structure for definitely storing files on equipment (a magnetic disk is common and a solid state disk based on nand flash) or a partition in a linux operating system; i.e. a method of organizing files on a storage device. The software mechanism responsible for managing and storing file information in an operating system is called a file management system, which is called a file system for short. The file system consists of three parts: an interface of a file system, a software set for operating and managing objects, objects and attributes. From a system perspective, a file system is a system that organizes and allocates space for file storage devices, is responsible for storing files, and protects and retrieves stored files. Specifically, it is responsible for creating files for users, storing, reading out, modifying, dumping files, controlling access to files, revoking files when users are no longer using, etc.
The protocol module is mainly used for operating the protocol required by the special network switching equipment to complete the specific function.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present application and should be understood that the scope of the application is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (6)
1. The method for quickly starting and recovering the data surface of the network switching equipment is characterized by comprising the following steps:
s1, powering on or resetting the network switching equipment;
s2, sending the pre-stored configuration data to a switching chip in the network switching equipment through fpga, so that the switching chip loads the configuration data into a register and a table entry in the switching chip;
the configuration data is specifically the configuration data required by the forwarding data of the exchange chip, the configuration data is pre-stored in the flash memory, and the configuration data specifically comprises inherent configuration firmware and dynamic configuration firmware;
the inherent configuration firmware is specifically firmware meeting the basic function configuration of the exchange chip, and the dynamic configuration firmware is specifically firmware of dynamic expansion configuration in the system operation process;
the step S2 specifically comprises the following sub-steps:
s21, reading the configuration data to a configuration buffer area inside the fpga through the fpga;
s22, sequentially detecting whether each configuration in the dynamic configuration firmware is an ending mark through fpga, if so, ending the loading of the dynamic configuration firmware, executing step S24, and if not, executing step S23;
s23, judging whether the corresponding configuration is effective, if so, sending the corresponding configuration to the exchange chip, and if not, discarding the current corresponding configuration;
the validity judgment in the step S23 means that the exchange chip checks the format of the received configuration data, and if the format is not the same, the configuration data is directly discarded from the internal link of the exchange chip;
s24, sending the inherent configuration firmware to the exchange chip through fpga;
when the system is powered on or reset, the fpga reads configuration data in an inherent configuration firmware area in the flash, the configuration data is stored in an internal buffer area of the fpga, the exchange chip reads the configuration data in the inherent configuration firmware from the buffer area of the fpga through an active configuration channel, and a communication bus clock between the exchange chip and the fpga is provided by the exchange chip;
after the exchange chip reads the configuration data in the inherent configuration firmware through the special configuration channel, the configuration data is configured into an internal register or table entry through the logic inside the chip;
loading of the dynamic configuration firmware is accomplished by switching another dedicated configuration channel of the chip, which is a passive channel that acts as a slave on the communication bus with the fpga, the clock on the bus being provided by the fpga.
2. The method for fast start-up restoration of a network switching device according to claim 1, wherein said configuration data is constituted in particular by a value of a register.
3. The method for quickly starting up and recovering network switching equipment according to claim 1, wherein each piece of configuration data specifically comprises a control bit, a node number, an intra-node offset and a value of the configuration data, the control bit specifically is control information describing the configuration data, a register of the switching chip is divided into various areas, each area is a node, the node number specifically is a node address corresponding to the configuration register, the intra-node offset specifically is an intra-node offset address, the intra-node offset and the node number together form a globally unique address of the register, and the value of the configuration data is a value of a register or an entry of the switching chip addressed according to the control bit, the node number and the node offset.
4. The method for fast start-up recovery of a data plane of a network switching device according to claim 1, further comprising, between said step S1 and said step S2:
a1, after the network switching equipment is powered on or reset, sending a data transmission recovery instruction to the fpga through a bottom data plane quick recovery component, so that the fpga sends pre-stored configuration data to a switching chip in the network switching equipment.
5. The method for quickly starting and recovering a data plane of a network switching device according to claim 1, wherein the data plane is started and a control plane is started at the same time.
6. The method for quickly starting and recovering the data plane of the network switching equipment according to claim 5, wherein the control plane is started, and the method specifically comprises the following sub-steps:
b1, starting a boot loader;
b2, starting a real-time operating system;
b3, starting a root file system;
and B4, operating a protocol module.
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