JPH10233677A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field programmable gate array FPGA in which one defective variable logic block is relieved by one standby variable logic block. SOLUTION: The integrated circuit is provided with a standby variable logic block 18 which substitutes a variable logic block 27 whose logic function is variably set. A connection relation between the variable logic block and a regular signal wiring 23 is set variably to variable connection sections 20, 21 provided to the variable logic block 27 and the connection between the regular signal wiring and the variable logic block is replaced with the connection between the regular signal wiring and the standby variable logic block. Thus, one defective variable logic block is replaced with the one standby variable logic block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a large number of logic blocks (variable logic blocks) whose logic functions can be set variably. For example, a relatively small variable logic block is regularly arranged, and a logical function and a wiring of the variable logic block are interconnected. FPGA (Field Programmable G) that allows the user to program the connection
ateArray).

[0002]

2. Description of the Related Art A semiconductor integrated circuit, such as an FPGA, which allows a user to set its logic function in a programmable manner, simulates the logic function of the logic LSI in order to verify the logic function at an early stage of development of the logic LSI. It is used when a small amount of logic LSI is realized in a very short time and at low cost, or when it is required to immediately deal with a change in logic specifications.

For example, an FPGA includes a number of variable logic blocks each having a logic core and a memory in which data for designating a logic function to be set in the logic core is set in a programmable manner. Control data supplied from outside is sequentially set in the memories of the individual variable logic blocks. The logic cores of many variable logic blocks are connected via a predetermined wiring network, and perform predetermined logic operations as a whole.

In a semiconductor integrated circuit such as an FPGA, as a redundant technique for replacing a defective logical block with a spare variable logical block when the variable logical block has a defect, for example, Japanese Patent Application Laid-Open No. 6-216557 describes the technique. There are things. According to this, the logic blocks that can be programmed by the user are arranged in a matrix, for example, spare variable logic blocks are arranged along the column direction. The data reaches the final stage by sequentially passing through variable logic blocks arranged in the column direction, for example. If there is a defect in the variable logic block, one row of the variable logic block row including the defective logic block is not used, and the connection between the variable logic block row and the first-stage input signal line and the last-stage output signal line is sequentially changed to the next variable row. Switch to a logical block sequence. That is, a variable logical block is replaced for a defective logical block on a column basis.

[0005] Japanese Patent Application Laid-Open No. 6-151599 also discloses an FP
A defect remedy technique in GA is described. Also in the technique described here, a number of variable logical blocks are arranged in a matrix, and defective logical blocks are replaced in units of columns or rows of variable logical blocks.

[0006]

According to the above-mentioned prior art, even if one variable logic block is defective, a variable logic block for one column or one row is collectively collected to remedy it. Since the blocks have to be replaced, the relief efficiency is low. Therefore, a large number of spare columns or spare rows must be prepared in order to be able to cope with a plurality of randomly generated defects. If no relief is required, a wasteful area increases.

[0007] The same applies to the signal wiring. Even if only one of the wirings in one column or one row has a defect, the variable logic block is replaced in units of columns or rows in order to repair the defect. The present inventor has found that the defect relief efficiency is low in this respect as well.

An object of the present invention is to provide a semiconductor integrated circuit in which one defective variable logic block can be repaired by one spare variable logic block.

Another object of the present invention is to provide a semiconductor integrated circuit capable of relieving the occurrence of a defect in a plurality of variable logic blocks at random while minimizing an unnecessary increase in area.

A further object of the present invention is to provide a semiconductor integrated circuit capable of minimizing a signal delay due to a circuit configuration for relieving a defect of a variable logic block.

Another object of the present invention is to provide a semiconductor integrated circuit that can be remedied by replacing only a defective part of a wiring whose connection relation is variably set, if the wiring has a defect. Is to provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

A semiconductor integrated circuit according to the present invention from the viewpoint of relieving a defect of a variable logic block includes a plurality of variable logic blocks whose logic functions are variably set as illustrated in FIGS. (27) a spare variable logic block (18) whose logic function is set to be variable and can replace the variable logic block, a plurality of normal signal wirings (23),
The connection relationship between the variable logic block and the normal signal wiring is provided variably, and the connection between the normal signal wiring and the variable logic block is changed to the normal signal wiring and the spare. A variable connection unit (20, 20) that can be replaced with a connection to a variable logic block.
21), a replacement instructing means (6) for instructing the replacement by the variable connection unit, and a variable logic which controls the setting of the connection mode for the variable connection unit and is replaced by the replacement instruction means. Control means (2, 8, 9) for controlling the setting of the logic function for the variable logic block and the spare variable logic block so that the logic function set for the block is set for the spare variable logic block to be replaced. Become.

According to the above-described semiconductor concentrator, the variable connection section provided corresponding to each variable logic block can connect the spare variable logic block to the normal signal wiring instead of the variable logic block. One defective variable logical block can be relieved by one spare variable logical block. Then, the control means can set the same logical function as the logical function to be set in the defect variable logical block in the spare variable logical block. Since the logic function setting operation is interlocked with the replacement instruction by the instruction means, the semiconductor integrated circuit is apparently no different from the semiconductor integrated circuit which has not been remedied by the replacement instruction means being programmed in the test process. It is assumed.

[0016] A wiring route variable means (24) for variably setting an interconnection relationship between the plurality of normal signal wires may be further included.

In order to connect the variable connection section to the spare variable logic block, spare signal wirings (25, 26) can be used. The spare signal lines are provided in accordance with the number of normal variable logical blocks assigned to one spare variable logical block, and the spare signal lines are shared by a plurality of variable connection portions for one spare variable logical block. Will do. At this time, the spare variable logic block can be connected to an intermediate portion of the spare signal wiring, and variable connection portions of the variable logic block can be connected to both sides thereof. According to this, the maximum signal propagation distance from the variable connection section to the spare variable logic block can be shortened.

More specifically, the variable logic blocks are arranged in a matrix. In response,
The spare variable logic block is arranged in a column direction or a row direction or a matrix direction of the variable logic block, the normal signal wiring is arranged in a matrix direction along the variable logic block, and the wiring path variable unit is provided with a normal signal wiring. An interconnection at an intersection position is defined, and the spare signal wiring is arranged in a column direction or a row direction of the variable logic block, and the variable connection portion is provided with a normal signal instead of a connection between the corresponding variable logic block and the normal signal wiring. The wiring can be connected to the nearest spare signal wiring.

A storage means such as a memory or a latch can be applied to the setting of the logical function for the variable logic block, the spare variable logic block, the variable connection section and the like. That is, the variable logical block (27) is a first logical unit (27A) in which information for designating a logical function realized by the logical core is set by the control unit.
The storage means (27B) can be used. Similarly, the spare variable logic block (18) is a logic core (18A)
And a second storage means (18B) in which information for designating a logical function realized by the logical core is set by the control means. The variable connection part (2
A switch circuit (0, 21) controls a state in which the logic core of the corresponding variable logic block is selectively connected to the normal signal wiring and a state in which the normal signal wiring is selectively connected to the spare signal wiring. 20A, 21A) and third storage means (20B, 21A) in which information for designating the switch state of the switch circuit is set by the control means.
B). At this time, the control unit stores the information to be set in the first storage unit of the variable logical block corresponding to the variable connection unit instructed to be replaced by the replacement instructing unit in the second variable of the spare variable logical block.
The logical function of the variable logical block is set in the storage means, and is set in the spare variable logical block.

In order to efficiently set data in the storage means, addresses may be assigned to the storage means for each variable logical block. That is, the control means includes an address signal generating means (8) and its decoding means (2). Decoding means (2) decodes the address signal and selects selection signals (16-1 to 16-3, 15) for selecting the first and third storage means corresponding to each variable logic block as one unit. -1 to 15-3), and when the variable logic block of the first storage means selected by the selection signal is to be replaced, the third storage means of the spare variable logic block to be replaced is also selected and paralleled. Set logical function.

The variable connection section includes a separation circuit (40-A, 40-B) for disconnecting the output of the third storage means from the signal input terminal of the switch circuit when replacement is instructed by the replacement instructing means. And a forcing circuit (39-A, 39-B) for forcing the switch state of the switch circuit into a state in which the normal signal wiring is connected to the spare signal wiring in response to the disconnection by the separating circuit. it can. Even if the output of the first storage unit is set to an intermediate level of the power supply voltage due to a defect in the first storage unit, the input of the logic core is forced to one of the power supply voltages. it can.

As shown in FIGS. 1 and 22, a semiconductor integrated circuit according to the present invention from the viewpoint of relieving a defect in a normal signal wiring includes a plurality of variable logic blocks whose logic functions can be variably set. (27 (27A, 27B)), a plurality of normal signal lines (23), and a plurality of spare signal lines (125, 126, 12) used for relief of the normal signal lines.
7, 167, 168) and a wiring capable of variably setting an interconnecting relationship between the plurality of normal signal wirings and replacing a connection between the normal signal wirings with a connection between the normal signal wiring and the spare signal wiring. A path variable unit (24) provided in correspondence with the variable logic block, variably sets a connection relationship between the variable logic block and the normal signal wiring, and establishes a connection between the normal signal wiring and the variable logic block. A variable connection section (20 (20A, 20A,
20B), 21 (21A, 21B)), replacement instructing means (6) for instructing the replacement by the variable connection part and the wiring path variable means, and connection modes for the variable connection part and the wiring path variable means. Control means (2, 8, 9) for controlling the setting and controlling the setting of the logical function for the variable logic block.

According to the above means, the normal signal wiring (23)
Of these, the defective part is the wiring route variable means (24)
Is bypassed to the spare signal wiring. The variable connection section (20, 21) replaces the connection between the defective portion of the normal signal wiring and the variable logic block with the connection between the spare signal wiring and the variable logic block. In other words, if the normal signal wiring receiving the output of the variable logic block is defective,
The variable connection section (21) guides the output to the spare signal wiring, and if the normal signal wiring on the signal input path of the variable logic block is defective, the variable connection section (20) replaces the normal signal wiring with the spare signal wiring. A signal is input from the signal wiring to the variable logic block. The wiring path changing means (24) separates a defective portion of the normal signal wiring from the signal transmission path, and joins the spare signal wiring to the normal signal wiring having no defect. Thus, the defective signal can be remedied by replacing only the portion of the regular signal wiring where the defect has occurred with the spare signal wiring. Furthermore, according to the above-described means, only the portion of the normal signal line where the defect has occurred is replaced with the spare signal line. Therefore, it is not necessary to replace the variable logic block in units of columns or rows to rescue the defect of the normal signal line, Efficient remedy for a defect in the normal signal wiring is made possible.

As shown in FIGS. 1 and 36, a semiconductor integrated circuit according to the present invention from the viewpoint of saving both the normal signal wiring and the variable logic block has a plurality of logic functions variably settable. Variable logic block (27 (27
A, 27B)) and a spare variable logic block (18) which is connected to the first spare signal wiring (25, 26) and whose logic function can be set variably and which can replace the variable logic block.
(18A, 18B)) and a plurality of regular signal wirings (23)
And a plurality of second spare signal lines (125, 126, 127, 167, 16
8) and a variable wiring path capable of variably setting an interconnecting relationship between the plurality of normal signal wires and replacing a connection between the normal signal wires with a connection between the normal signal wires and the second spare signal wires. Means (24) provided corresponding to the variable logic block, variably setting a connection relationship between the variable logic block and the normal signal wiring, and changing a connection between the normal signal wiring and the variable logic block by the variable Replacing the connection between the logic block and the second spare signal line with the connection between the normal signal line and the variable logic block via the first spare signal line; Variable connection parts (20 (20A, 20B), 21 (21
A, 21B)), replacement instructing means (6) for instructing the replacement by the variable connection part and the wiring path variable means, and setting of the connection mode for the variable connection part and the wiring path variable means. The setting of the logic function for the variable logic block and the spare variable logic block is set such that the logic function set for the variable logic block to be replaced by the instruction of the replacement instruction means is set for the spare variable logic block to be replaced. And control means (2, 8, 9) for controlling.

According to the above-described means, the variable connection unit can connect the spare variable logic block to the normal signal wiring via the first spare signal wiring instead of the defective variable logic block, thereby forming one A defective variable logical block can be remedied by one spare variable logical block. Furthermore, if the normal signal wiring receiving the output of the variable logic block is defective,
The variable connection section (21) guides the output to the second spare signal wiring. If the normal signal wiring on the signal input path of the variable logic block is defective, the variable connection section (20) replaces the normal signal wiring. A signal from the second spare signal line to the variable logic block,
Is to separate the defective portion of the normal signal wiring from the signal transmission path and merge the spare signal wiring with the normal signal wiring having no defect. Therefore, of the regular signal wiring, only the defective portion is replaced with the spare signal wiring, The defect can be remedied. As described above, both the defect of the normal signal wiring and the defect of the variable logic block can be efficiently relieved.

In particular, as illustrated in FIG. 40, the variable connection unit includes a first state in which a logic core of a corresponding variable logic block is connected to the normal signal wiring, and a state in which the normal signal wiring is connected to the first signal wiring. A second state in which the spare signal wiring is connected, a third state in which the normal signal wiring is connected to the second spare signal wiring, and a fourth state in which the first spare signal wiring is connected to the second spare signal wiring are selected. Switch circuit (20A, 2
1A). According to this,
When the variable connection section selects the fourth state, the first spare signal wiring and the second spare signal wiring are electrically connected in a state of being separated from the normal wiring and the variable logic block. Therefore, even when both the variable logic block and the normal signal wiring assigned to the signal input / output node have defects, it is possible to perform relief in parallel.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Rescue of Variable Logic Block >> First, a semiconductor integrated circuit that can be repaired by replacing a defective variable logic block with a spare variable logic block in units of variable logic blocks will be described.

FIG. 1 is an overall block diagram of an FPGA which is an example of a semiconductor integrated circuit according to the present invention. The FPGA shown in the figure has a large number of variable logic / variable connection units 1, a spare variable logic block 18, a wiring path variable circuit 24, an address decode logic circuit 2, a variable external input / output circuit 7, an address generation circuit arranged in a matrix. 8, control data writing circuit 9, fuse program circuit 6,
The regular signal line 23 and the spare signal lines 25 and 26
It is configured by being arranged on one semiconductor substrate such as single crystal silicon. The variable logic / variable connection unit 1 includes a variable logic block 27 to be described later and variable connection units 20 and 21.
And The spare signal lines 25 and 26 are an example of first spare signal lines used to rescue a variable logic block.

The variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24, and the variable external input / output circuit 7 have storage circuits for determining their respective functions in a programmable manner. The logic functions of the variable logic / variable connection unit 1 and the spare variable logic block 18 are determined according to control data written in the storage circuit. The wiring path variable circuit 24 determines the interconnection between the upper, lower, left, and right regular signal wirings 23 arranged in the matrix direction according to the control data written in the storage circuit.
Although a part of the normal signal wiring 23 is shown in FIG. 1 as a representative, a large number of the normal signal wirings 23 are actually arranged in parallel in the matrix direction. The variable external input / output circuit 7 has a large number of circuits in which an external connection electrode such as a bonding pad and a buffer circuit are paired, and the normal signal wiring 23 to which the buffer circuit is connected, and the buffer circuit Whether to function as a signal output, an input, or an input / output is determined by control data written to the storage circuit.

The control data is supplied from the control data writing circuit 9 to the following components. The control data writing circuit 9 controls the transfer of control data to the variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24, and the variable external input / output circuit 7. In FIG. 1, reference numeral 17 denotes a control data line 1.
7 Reference numeral 19 denotes a write control line. The control data line 17 and the write control line 19 are the variable logic / variable connection unit 1, the spare variable logic block 1
8, wiring path variable circuit 24, and variable external input / output circuit 7
Connected in common. Although not particularly limited, the control data is serially input from the data input terminal 12. The input of the serial data is synchronized with the clock signal supplied from the clock terminal 11. Data transfer on the control data line 17 inside the FPGA is performed in parallel on a predetermined bit basis. The serial / parallel conversion is performed by the control data writing circuit 9 in synchronization with the clock signal.

To enable the control data supplied via the control data line 17 to be sequentially written into a large number of storage circuits, the variable logic / variable connection unit 1, the wiring path variable circuit 24, and the variable external input / output Each of the storage circuits included in the circuit 7 is assigned a unique address. The address is specified by an X address signal 13 and a Y address signal 14. The address decode logic circuit 2 generates a selection signal for the storage circuit based on the X address signal 13, the Y address signal 14, and the like. FIG. 1 shows X selection signals 16-1 to 16- as such selection signals.
4, 43-1 to 43-3 and Y selection signals 15-1 to 15-15
-4, 42-1 to 42-3 are representatively shown.
X selection signals 16-1 to 16-4 and Y selection signals 15-1 to 15-1
Reference numeral 15-4 denotes a selection signal for selecting a storage circuit incorporated in each of the variable logic / variable connection unit 1 and the spare variable logic block 18. For example, when the X selection signal 16-1 and the Y selection signal 15-1 are set to the selection level, the storage circuit of the variable logic / variable connection unit 1 at the upper left of FIG. 1 is selected. X selection signals 43-1 to 43-3 and Y selection signal 42-
Reference numerals 1 to 42-3 are selection signals for selecting the storage circuits built in the wiring path variable circuit 24, respectively. Note that the selection method for the storage circuit of the variable external input / output circuit 7 is the same as that described above.

The X address signal 13 and the Y address signal 14 are output from the address generating circuit 8. There are several types of address generation modes by the address generation circuit 8. The first is an address signal generation mode (sequential selection mode) for sequentially selecting the storage circuits of the variable logic / variable connection unit 1, the wiring path variable circuit 24, and the variable external input / output circuit 7. For this purpose, the address generation circuit 8 has a built-in address counter. The sequential selection mode is F
In order to determine the overall logical function of the PGA, the variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24 and the variable external input / output circuit 7
This is used when writing control data to the storage circuit of.
Second, in the device test, the memory circuits of the variable logic / variable connection unit 1, the wiring path variable circuit 24 and the variable external input / output circuit 7 are arbitrarily selected, and a desired logic function or a desired operation is set to them. This is a random access address generation mode (random selection mode) that enables a detailed test. The address signal at that time is supplied from the data input terminal 12, although not particularly limited. Further, the address generation circuit 8 has a batch selection mode. This is an operation mode for collectively selecting the storage circuits of the variable logic / variable connection unit 1 and writing the same data to each of them in order to improve the overall test efficiency in the device test. Reference numeral 61 denotes a collective selection signal for performing the collective selection. 62
Is the random address signal at that time. The random address signal 62 is serially supplied from the data input terminal 12, although not particularly limited.

By setting control data in the storage circuit and determining the functions of the variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24, and the variable external input / output circuit 7, the FPGA Can perform a desired logical operation. The control data is FPG
A can be positioned as user program information for realizing a desired logical function. Signal inputs and outputs related to the logic operation of the variable logic / variable connection unit 1 are performed via the normal signal wiring 23. Regular signal wiring 2
1, the interconnection relationship is determined by the wiring path variable circuit 24, although only a part thereof is shown in FIG. The external interface of the normal signal wiring 23 is performed by the variable external input / output circuit 7.

The spare variable logic block 18 is a redundant variable logic block which can replace a variable logic block included in the variable logic / variable connection unit 1 when it is defective. The variable logic block included in the defective variable logic / variable connection unit 1 is replaced with the spare variable logic block 1.
The spare signal wirings 25 and 26 and the fuse program circuit 6 are provided to replace the spare signal wirings 8 and 8. The following two points are considered in the replacement. First, in setting control data by a user, it is not necessary to be conscious of whether or not replacement has been performed. Second, one spare variable logic block 18 can cope with a failure of a variable logic block included in one variable logic / variable connection unit 1.

That is, in order to enable the writing of predetermined control data to the spare variable logic block 18 used for relief, the fuse program circuit 6 sets the variable logic / variable connection unit 1 to be replaced by the spare variable logic block 18. It has a program area in which an address (address to be relieved) assigned to the storage circuit is programmed.
The variable logic block of the variable logic / variable connection unit 1 designated by the address to be repaired is specified to be replaced with the spare variable logic block 18 in the same row or the spare variable logic block 18 in the same column. Information (queue repair designation information) is also added to the address to be repaired. Further, the fuse program circuit 6 also has a setting area for relief enable information for indicating whether or not relief has been performed. In FIG. 1, reference numeral 60 denotes a programmed address to be rescued, matrix rescue designation information, and rescue enable information. The fuse program circuit 6
Can be positioned as rescue instruction information set by the manufacturer of the FPGA.

When the rescue enable information indicates rescue, the address decode logic circuit 2 compares the programmed address to be rescued with the X address signal 13 and the Y address signal 14 in parallel. If the comparison result indicates a match, the matrix rescue designation information is referred to. If the rescue is in the row direction, the selection signal 15-4 is set to the selection level. If the rescue is in the column direction, the selection signal 16-4 is set to the selection level. To At this time, the address decode logic circuit 2 selects the row direction selection signal (any of 16-1 to 16-3) and the column direction selection signal (15-1 to 15-3) designated by the X address signal 13 and the Y address signal 14. 15-3) is also set to the selection level. As a result, the same control data can be supplied to the storage circuit of the variable logic / variable connection unit 1 including the variable logic block to be rescued and the storage circuit of the spare variable logic block 18 in the same column or the same row as the storage circuit. Is done.

The variable logic / variable connection unit 1 including the variable logic block to be rescued includes a spare signal line 25 as a representative dedicated line for rescuing the variable logic block,
26, it can be connected to the spare variable logic block 18 in the same row. Although not particularly shown, a variable logic block relief dedicated line for connecting the variable logic / variable connection unit 1 including the variable logic block to be repaired to the spare variable logic block 18 in the same column is also provided. . Variable logic, including variable logic blocks to be rescued
In a state where the variable connection unit 1 is connected to the spare variable logic block 18 via the spare signal wirings 25 and 26,
The normal signal wiring 23 connected to the variable logic / variable connection unit 1 including the variable logic block to be rescued is connected to the spare variable logic block 18 with the spare signal wirings 25 and 26 as detours, whereby the variable logic / variable connection is established. The logic function of the variable logic block to be rescued included in the unit 1 is replaced with the logic function of the spare variable logic block 18. The replacement with the spare variable logic block 18 using the spare signal wirings 25 and 26 is performed by using a repair instruction signal 54 unique to each variable logic / variable connection unit 1.
Directed by The rescue instruction signal 54 can be formed by providing the fuse program circuit 6 with a fuse program link for each variable logic / variable connection unit. The fuse program link can be configured using, for example, a fuse that can be blown by a laser.

Although the basic operation mode of the FPGA is not particularly limited, it is determined by 2-bit external signals 10A and 10B. The state of 10A, 10B = 0, 0 is the normal operation mode, and the other state is the program mode. The program mode is an operation in which the control data writing circuit 9 writes control data to the storage circuits of the variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24, and the variable external input / output circuit 7. A mode, in other words, an operation mode for determining the logic function of the FPGA. The sequential selection mode is designated by 10A, 10B = 1, 0, and 10A, 10B =
The random selection mode is designated by 0, 1 and 1
The batch selection mode is designated by 0A, 10B = 1,1. The normal operation mode is realized in the FPGA according to the control data written in the storage circuits of the variable logic / variable connection unit 1, the spare variable logic block 18, the wiring path variable circuit 24, and the variable external input / output circuit 7. This is an operation mode in which a logical operation can be performed. In this operation mode, the FPGA operates as a logic LSI in which a desired logic function is set.

FIG. 2 shows a variable logic / variable connection unit 1,
One example of the spare variable logic block 18 and the wiring path variable circuit 24 is shown. The variable logic / variable connection unit 1 has a variable logic block 27, a variable connection unit 20 for input, and a variable connection unit 21 for output.

The variable logic block 27 variably implements the logic function of the logic core 27A according to the data set in the latch circuit 27B. The variable connection unit 20 includes a switch circuit 20A and a latch circuit 20B. The normal signal wiring 23 is actually a multi-bit signal line. The switch circuit 20A selects an arbitrary bit from the plural-bit normal signal wiring 23 according to the control data set in the latch circuit 20B and connects the selected bit to the logic core 27A. Switch circuit 2
When the repair instruction signal 54 is activated, 0A connects the bit of the normal signal line 23 for which the connection to the logical core 27A is instructed to the spare signal line 25 instead of the connection to the logical core 27A. Similarly, the variable connection section 21 includes a switch circuit 21A and a latch circuit 21B. The switch circuit 21A selects an arbitrary bit from the plural-bit normal signal wiring 23 according to the control data set in the latch circuit 21B, and connects the selected bit to the logic core 27A. When the rescue instruction signal 54 is activated, the switch circuit 21A connects the bit of the regular signal line 23 for which the connection to the logical core 27A is instructed to the spare signal line 26 instead of the connection to the logical core 27A. . The latch circuits 20B, 21B, 27
B constitutes the storage circuit of the variable logic / variable connection unit 1.

The spare variable logic block 18 variably implements the logic function of the logic core 18A by the data set in the latch circuit 18B. The logic core 18A has a circuit configuration that is electrically equivalent to the logic core 27A.
The spare signal wiring 25 is coupled to an input of the logic core 18A, and an output of the logic core 18A is coupled to a spare signal wiring 26. The latch circuit 18B is the spare variable logic block 18.
Is constructed.

The wiring path variable circuit 24 is constituted by a switch circuit 24A which determines the connection mode of the front, rear, left and right normal signal wirings 23 according to control data set in a latch circuit 24B as a storage circuit.

In FIG. 2, for example, selection signals 15-3,
When 16-1 is set to the selection level, the variable logic
Storage circuits 20B, 27B, 21B of variable connection unit 1
, Control data is written in parallel from the control data line 17. When the logical function of the variable logic / variable connection unit 1 is set in this way, in the logical operation, for example, the data signal from the normal signal wiring 23 is shown in FIG.
And the result of the logical operation on the input is output to the normal signal wiring 23 on the opposite side. When the variable logic / variable connection unit 1 of FIG. 2 is instructed to rescue by the spare variable logic block 18 in the same row, the selection signal 1
The selection signal 15-4 is set to the selection level together with 5-3 and 16-1. As a result, the same control data as 27B is written in the storage circuit 18B of the spare variable logic block 18, and
The spare variable logic block 18 can realize the same logic function as the variable logic block 27.

When such a repair is performed, replacement of the logical operation by the spare variable logic block 18 is instructed to the variable logic / variable connection unit 1 to be repaired. That is, the relief instruction signal 54 corresponding to the variable logic / variable connection unit 1 is activated. The variable connection units 20 and 21 receiving the activated rescue instruction signal 54 are connected to the regular signal wiring 2 for which connection to the logic core 27A is instructed.
3 is switched to the connection with the spare signal wirings 25 and 26, whereby the data signal from the normal signal wiring 23 passes through the path shown in FIG. The signal is input to the logic block 18, and the result of the logic operation on the input is output to the opposite normal signal wiring 23 via the spare signal wiring 26. When the above-described remedy is performed, in the normal operation mode, such replacement of the logic function is performed, and the rescued FPGA functions in exactly the same way as the fully-functional FPGA.

Further, the logical operation when the replacement of the logical operation by the spare variable logical block 18 is instructed and when it is not instructed will be described with reference to FIG. In FIG. 3, the normal signal wirings 23 are shown in a state where a plurality of the normal signal wirings 23 are arranged in parallel. The latch circuits 18C and 18D shown in FIG. 3 are dummy latch circuits that do not function substantially. That is, the 20B, 27B, 21B
When the same circuit configuration as the combination of the above is adopted in the spare variable logic block 18, the latch circuits corresponding to 20B and 21B are 18C and 18D, and these are circuits that are functionally unnecessary in the spare variable logic block 18. It is said.

In FIG. 3, for example, the logic functions programmed by the user are variable logic / variable connection units 1-2, 1 and 2.
-1, 1-3 logical cores 27A-2, 27A-1, 2
7A-3. Here, the signal flow is the logic core 27A-2, the variable logic / variable connection unit 1
-2, the normal signal wiring 23-1, the wiring path variable circuit 24-1, the normal signal wiring 23-2, the variable connection unit 20A in the variable logic / variable connection unit 1-1,
Logic core 27A-1, variable logic / variable connection unit 1-
1, a normal signal wiring 23-3, a wiring path variable circuit 24-2, a normal signal wiring 23-4, a wiring path variable circuit 24-3, a normal signal wiring 23-5, a variable logic / variable connection. It follows the path of the variable connection unit 20A in the unit 1-3 and the logical core 27-3. At this time,
The wiring path variable circuit 24-1 is connected to the regular signal wirings 23-1 and 2-2.
3-2, and the wiring path variable circuit 24-2 is connected to the normal signal wirings 23-3 and 23-.
4 and the wiring path variable circuit 24-
3 is programmed to connect the normal signal wirings 23-4 and 23-5.

Here, the variable logic / variable connection unit 1-
1 is defective, and a case where switching to the spare variable logic block 18-1 is performed will be described. Variable logic / variable connection unit 1
The variable connection section 20A within -1 is in an activated state according to a signal from the latch circuit 20B for retaining user logic, that is, user program information. Further, since the rescue instruction signal 54-1 gives information indicating that the variable logic / variable connection unit 1-1 has a defect, for example, "0" level, it comes in through the regular signal wiring 23-2. The transmitted signal passes through the variable connection section 20A in the variable logic / variable connection unit 1-1 and is transmitted to the redundant input spare signal wiring 25. At this time, the signal transmission from the normal signal wiring 23-2 to the variable logic / variable connection unit 1-1 is the same whether or not the switching to the spare variable logic block 18-1 is performed. Looks like.

At this time, the variable logic / variable connection units 1-4 sharing the same redundant input spare signal wiring 25
Since the connection to the spare signal wiring 25 is suppressed by the dedicated rescue instruction signal 54-4, the spare signal does not collide with the signal on the latitude line 25. As is clear from this, the spare signal wiring 25 is exclusively assigned to the relief of one variable logic unit.

The signal transmitted to the spare signal line 25 via the variable logic / variable connection unit 1-1 is transmitted to the spare variable logic block 18-1, and the spare variable logic block 18
-1 reaches the logical core 18A. Since the user program information to be written to the latch circuit 27B in the variable logic / variable connection unit 1-1 having a defect at the time of a user program is written in the latch circuit 18B in the spare variable logic block 18-1. The logic core 18A in the logic block 18-1 can realize the same logic function as the logic core 27A-1 in the variable logic / variable connection unit 1-1. Therefore, the spare variable logic block 18-
The signal transmitted to the logic core 18A in 1 is transmitted to the redundant output spare signal wiring 26 through a logical operation according to the user program information.

The variable logic / variable connection unit 1-4 which can be connected to the redundant output spare signal wiring 26 in the same manner as the redundant input spare signal wiring 25 is a variable logic / variable connection unit 1-1. It is possible to connect to the spare signal wiring 26 for the same redundant output as described above, but the connection to the spare signal wiring 26 is suppressed by the replacement instruction 54-4 for the variable logic / variable connection unit 1-4. .

The signal transmitted to the redundant output spare signal wiring 26 reaches the variable connection section 21 in the variable logic / variable connection unit 1-1. Variable logic / variable connection unit 1
The variable connection unit 21 in -1 is in the activated state according to the signal from the latch circuit 21B for retaining the user logic, that is, the user program information. Further, the relief instruction signal 54-1
Gives information that the variable logic / variable connection unit 1-1 has a defect, that is, the "0" level, so that the signal from the redundant output spare signal line 26 is the normal signal line 2
It is transmitted to 3-3. At this time, regardless of whether or not replacement with the spare variable logic block 18 is performed,
Variable logic / variable connection unit 1-1 to regular signal wiring 2
The signal output to 3-3 is the same. Regular signal wiring 23-
The signal transmitted to the variable logic / variable connection unit 1 through the wiring path variable circuit 24-2, the normal signal wiring 23-4, the wiring path variable circuit 24-3, and the normal signal wiring 23-5 in this order. Reach 3 Thus, only the variable logic / variable connection unit 1 in which a defect has occurred can be switched to the spare variable logic block 18.

As is clear from the above description, for example,
As shown in FIG. 2 (FIG. 3), only the variable logic block 27 in which a defect has occurred can be switched to the spare variable logic block 18, so that when the user program is written to the FPGA, In both cases of using the FPGA, the FPGA can be operated without any trouble. That is, even if there is no defect and the switching from the variable logical block 27 to the spare variable logical block 18 is not performed, there is a defect and the
Even when the switching is performed, the user can freely program the logic function in exactly the same way, and can perform the logic operation as programmed.
In addition, since only the variable logic block 27 having a defect is switched to the spare variable logic block 18, it is possible to cope with a plurality of randomly generated defects while minimizing an increase in wasted area.

FIG. 4 shows a detailed example of the switch circuits 20A and 21A included in the variable logic / variable connection unit 1. Here, latch circuits 20B and 21B hold user program information (control data) for the variable connection units 20 and 21 of the variable logic / variable connection unit 1. Reference numeral 28 denotes one of pass transistors (n-channel MOS transistors) constituting the switch circuit 20A of the variable connection unit 20, and a transistor (n-channel MOS transistor) for connecting the normal signal wiring 23 to the redundant input spare signal wiring 25. ). Reference numeral 29 denotes one of pass transistors constituting the switch circuit 20A, which is a pass transistor (n-channel MOS transistor) for connecting the normal signal wiring 23 to the logic core 27A. These pass transistors serve as a repair instruction signal 54 and a memory cell (latch circuit) 20 for holding user program information.
B, 21B that receives signals from B and 21B as inputs.
The switches are controlled by the outputs of 1,56-2.

FIG. 5A shows an operation mode of the switch circuit 20A of the variable connection unit 20 in FIG. When both the repair instruction signal 54 and the control data of the latch circuit 20B have the logical value "0", the pass transistor 28 is turned on, and the normal signal line 23 is connected to the spare signal line 25 for redundant input. When the rescue instruction signal 54 has the logical value "1" and the control data of the latch circuit 20B has the logical value "0", the pass transistor 29 is turned on, and the normal signal wiring 23 is connected to the logical core 27A. In other cases, the pass transistors 28 and 29 are both turned off, and the logic core 27A is disconnected from the normal signal wiring 23. In this configuration, regardless of whether the normal signal wiring 23 is connected to the spare signal wiring 25 or the logic core 27A, the number of pass transistors interposed in the signal transmission path is reduced to one.

The switch circuit 21A of the variable connection unit 21 shown in FIG. 4 includes a path transistor 31 for connecting the redundant output spare signal line 26 to the normal signal line 23 and a path for connecting the logic core 27A to the normal signal line 23. The transistor 30 includes NAND gates 57-1 and 57-2 to which a signal from the latch instruction signal 54 and a latch circuit 21B for retaining user program information (control data) are input.
The pass transistors 30 and 31 are connected to a NAND gate 57-1,
The switch is controlled by the output of 57-2. FIG. 5B shows an operation mode of the switch circuit 21A. When the rescue instruction signal 54 and the control data of the latch circuit 21B are both logical values "0", the pass transistor 31 is turned on, and the redundant output spare signal line 26 is connected to the normal signal line 23. The rescue instruction signal 54 is a logical value "
When the control data of the latch circuit 21B is "1" and the logic value is "0", the pass transistor 30 is turned on and the logic core 27A is connected to the normal signal wiring 23. In other cases, the pass transistors 31 and 30 are used. Are both turned off, and the logic core 27A is cut off from the normal signal wiring 23.

FIG. 6 shows the switching circuits 20A and 21A.
Another example is shown. 6 is provided with pass transistors 37 and 38 that are switch-controlled by control data of the latch circuits 20B and 21B in order to separate the normal signal wiring 23 from the variable logic / variable connection unit 1. 4 is that switch control is performed by an inverted signal of the repair instruction signal 54 and switch control of the pass transistors 29 and 30 is performed by the repair instruction signal 54.
Is different from

FIG. 7A shows the switching circuit 20 of FIG.
The operation mode of A is shown. When the rescue instruction signal 54 has a logical value “0” and the control data of the latch circuit 20B has a logical value “1”, both the pass transistors 28 and 37 are turned on, and the normal signal line 23 becomes the spare signal line 2 for redundant input.
5 is connected. Relief instruction signal 54 and latch circuit 20B
Are both logical values "1", the pass transistors 29 and 37 are turned on, and the normal signal wiring 23 is connected to the logical core 27A. In other cases, the pass transistor 37 is turned off and the logic core 27A
Are in a state of being separated from the normal signal wiring 23.

FIG. 7B shows the switching circuit 21 of FIG.
The operation mode of A is shown. The rescue instruction signal 54 is a logical value "
When the control data of the latch circuit 21B is "1", the pass transistors 31 and 38 are both turned on, and the spare signal line 26 for redundant output is connected to the normal signal line 23.
Connected to. Relief instruction signal 54 and latch circuit 21B
Are both logical values "1", the pass transistors 30 and 38 are turned on, and the logical core 27A is connected to the normal signal wiring 23. In other cases, the pass transistor 38 is turned off, and the variable logic / variable connection unit 1 is disconnected from the normal signal wiring 23.

Also in the configuration of FIG. 6, only the variable logic block 27 in which a defect has occurred can be switched to the spare variable logic block 18. In particular, when the transistor 37 is off, the sources of the transistors 28 and 29
The drain capacitance component is completely separated from the normal signal wiring 23. Similarly, when the transistor 38 is off,
The source / drain capacitance components of the transistors 31 and 30 are completely separated from the normal signal wiring 23. On the other hand, in the configuration of FIG. 4, the source / drain capacitance components of the transistors 28 and 29 and the source / drain capacitance components of the transistors 30 and 31 are always added to the normal signal wiring 23. 6 increases the number of transistors interposed in the signal transmission path, but when the variable logic / variable connection unit 1 is disconnected from the normal signal wiring 23, The parasitic capacitance component (source / drain capacitance component) added to the signal wiring 23 can be reduced.

FIG. 8 shows still another example of the variable logic / variable connection unit 1. The configuration of FIG.
When there is a defect in B, 27B, and 21B, the level of control data is set to a voltage such as an intermediate level with respect to the power supply voltage, thereby preventing a situation in which a through current or the like occurs in a subsequent circuit. That is, the transistor typically represented by 39-A and 39-B is the latch circuit 2
0B, 27B, and 21B are connected to the ground level (G
ND). 40-
The transistors typically represented by A and 40-B are pass transistors for selectively separating the control data output paths of the latch circuits 20B, 27B and 21B from the subsequent circuits. The transistors 40-A and 40-B are switch-controlled by a rescue instruction signal 54, and the transistors 39-A and 39-B are switch-controlled by an inverted signal of the rescue instruction signal 54.

FIG. 9A shows an operation mode of the switch circuit 20A. When both the repair instruction signal 54 and the control data of the latch circuit 20B have the logical value "0", the pass transistor 28 is turned on, and the normal signal line 23 is connected to the spare signal line 25 for redundant input. At this time, the transistor 39-A is turned on, and the transistor 4
Since 0-A is turned off, the latch circuits 20B, 2B
Output signals 58-A and 58-B of 7B and 21B are fixed to the ground level. Further, the rescue instruction signal 54 has a logical value "
When the control data of the latch circuit 20B is set to the logical value "1" at "0", the transistors 39-A and 39-B are turned on and the transistors 40-A and 40-B are turned off. The signals 58-A and 58-B from the circuits 20B, 27B and 21B can be fixed at the ground level.

FIG. 9B shows the operation of the switch circuit 21A. Relief instruction signal 54 and latch circuit 2
When both the control data of 1B are logical values “0”, the pass transistor 31 is turned on, and the redundant output spare signal line 26 is connected to the normal signal line 23. At this time, the transistor 39-B is turned on and the transistor 40-B is turned off, so that the signal 58-B is fixed to the ground level. Further, the rescue instruction signal 54 has the logical value “0” and the latch circuit 21B
When the control data of the transistor 39 has the logical value "1", the transistor 39
Since -B is turned on and 40-B is turned off, the signal 58-A is fixed to the ground level.

In the configuration shown in FIG. 8, when the logic function of the variable logic block 27 included in the variable logic / variable connection unit 1 is replaced with the spare variable logic block 18, the latch circuits 20B, 27B, 2 for holding the user program information are provided.
1B, it is possible to prevent those outputs from reaching an intermediate level and generating a through current or the like in a subsequent circuit.

FIG. 10 shows an example of the variable logic block 27. Variable logic block 27 shown in FIG.
Are configured in a so-called look-up table format. Input signals are shown as INa-INc and output signals as OUT. The latch circuit 27B has MC1 to M
C8. The logic core 27A is composed of a tree-shaped transistor network of two branches and three stages in series. That is, it has a first hierarchy including the transistor pairs PT1 to PT4, a second hierarchy including the transistor pairs PT5 and PT6, and a third hierarchy including the transistor pair PT7. The transistor pair PT1 to PT4 in the first hierarchy is MC
1 to 8 are transmitted to the subsequent stage according to INc and an inverted signal of INc. In the second hierarchy, the transistor pairs PT5 and PT6 output the output from the first hierarchy to INb and I
The signal is transmitted to the subsequent stage according to the inverted signal of Nb. The transistor pair PT7 of the third hierarchy selects the output from the second hierarchy according to INa and the inverted signal of INa. The variable logic block 27 illustrated in FIG. 10 can programmatically realize logic functions such as three-input various logic gates according to the logic values set in MC1 to MC8, for example.

FIG. 11 shows an example of the wiring path variable circuit 24. In FIG. 11, L11, L12, L2
1 and L22 are internal wirings connected to the front, rear, left and right regular signal wirings 23. Latch circuit 2 for storing control data
4B is configured by MC11 to MC16, and the switch circuit 24A is configured by transistors T1 to T6. The control data set in MC11 to MC16 controls the switches of the transistors T1 to T6. With this configuration, the wiring path variable circuit 24 includes P1 to P shown in FIG.
Any of the six connection modes can be programmably realized.

FIG. 13 shows another example of the FPGA.
The difference from FIG. 1 is a configuration for writing control data to the wiring path variable circuit 24. In the case of FIG. 13, the latch circuit of the wiring path variable circuit 24 is serially connected to the serial control data line 17S to write control data serially. In this case, the control data writing circuit 9 is instructed via the terminal 10C as to whether the data is to be serially written or written by the X and Y addresses.

FIGS. 14 to 17 show various aspects of the layout of the spare variable logic blocks in the form of layout images. 1 and FIG. 13 correspond to FIG. 14, and a spare variable logic block 18 is arranged at one end of the variable logic / variable connection unit 1 in one row and one column. In an area indicated by 51, the address decode logic circuit 2, the fuse program circuit 6, the address generation circuit 8, and the control data write circuit 9 are arranged. According to the configuration in which the spare variable logic blocks are arranged in the matrix direction, the portion can be switched to the spare variable logic block 18 even for a plurality of defects occurring in the same column or the same row.

As shown in FIG. 15, the spare variable logic block 18 may be provided only in the column direction, or may be provided only in the row direction (not shown) to configure the FPGA.
In FIG. 15, the illustration of the area indicated by 51 is omitted.

As shown in FIG. 16 and FIG. 17, the spare variable logic block 18
At the middle of the array in the matrix direction.
Thus, when the normal variable logic block is replaced with the spare variable logic block, the signal propagation distance on the redundant input spare signal wiring line 25 and the redundant output spare signal wiring line 26 can be shortened. This acts to reduce the apparent parasitic capacitance affecting the signal propagation.

FIG. 18 shows a spare variable logic block 18 suitable for arranging a spare variable logic block in the middle of an array of variable logic / variable connection units as shown in FIG. 16 or FIG. Reference numerals 25-L and 25-R denote input spare signal lines arranged on the left and right sides of the spare variable logic block 18. The input terminals of the logic core 18A and the spare signal lines 25 are provided.
−L, a pass transistor 47-1 is provided,
A pass transistor 48-1 is arranged between the input terminal of the logic core 18A and the spare signal wiring 25-R. 2
6-L and 26-R are spare signal wirings for output arranged on the left and right of the spare variable logic block 18,
A pass transistor 47-2 is arranged between the output terminal of A and the spare signal line 26-L, and a pass transistor 48-2 is arranged between the output terminal of the logic core 18A and the spare signal line 26-R. Have been. 54-L1-54-Li
Is a repair instruction signal for the variable logic / variable connection unit 1 sharing the spare signal lines 25-L and 26-L. Similarly, 54-R1 to 54-Ri are spare signal lines 25-R,
This is a rescue instruction signal for the variable logic / variable connection unit 1 sharing the 26-R. The rescue instruction signal 54-L1
To 54-Li are supplied to a NAND gate 50, and the output of the NAND gate 50 outputs the pass transistor 47-Li.
-1 and 47-2 are switch-controlled. Similarly, the repair instruction signals 54-R1 to 54-Ri are supplied to the NAND gate 49.
And the output of the NAND gate 49 switches the pass transistors 48-1 and 48-2. In this example, the relief instruction signals 54-R1 to 54-
The logical values "0" of Ri, 54-L1 to 54-Li are set as replacement instruction levels. For example, the repair instruction signal 54-L1
Is a logical value "0", the logical function of the variable logic block 27 instructed to be replaced by the
-L, 26-L, and are replaced by the logic function of the spare variable logic block 18. At this time, the spare signal wiring 25
-L, 26-L are the spare signal wirings 25-R, 26 on the opposite side.
Since -R is electrically non-conductive, the parasitic capacitance component and the wiring resistance component on the spare signal wirings 25 and 26 that affect the signal propagation required for the replacement of the logic function can be further reduced.

FIG. 19 shows a schematic device cross section of the FPGA near the variable logic / variable connection unit. In FIG. 19, a number of N-channel MOS transistors are formed in a P-type well region PWEL of an N-type semiconductor substrate SUB. This FPGA has a three-layer metal wiring structure. M1 is a first aluminum wiring layer, M2 is a second aluminum wiring layer, and M3 is a third aluminum wiring layer. Each aluminum wiring layer is electrically separated by an interlayer insulating film. As is clear from the drawing, the redundant input spare signal wiring 25 and the redundant output spare signal wiring 26 are formed using the third aluminum wiring layer M3. Therefore, it is possible to prevent a shortage of wiring resources and an increase in area due to the addition of the spare signal wirings 25 and 26 that have not been provided conventionally.

FIG. 20 shows a system configuration diagram when the above FPGA is subjected to a device test. 70 is the aforementioned F
PGA, 71 is a tester. Tester 71 is FPGA7
A program and data storage area 72 for testing the variable logic block 27 of 0, and a processor for writing test data to the FPGA 70 in accordance with the test program and taking in a result of a logical operation based on the written data to perform a device test 73.

For example, when the FPGA 70 has the configuration shown in FIG. 1, the FPGA 70 has the variable external input / output circuit 7 and the terminals 12, 11, 10A and 10B coupled to the tester 71. In the device test, the functions of the variable external input / output circuit 7 and the wiring path variable circuit 24 are set for the test. Such a function setting may be automatically performed by setting the test mode, or data may be set from the terminal 12. The address designation at this time can be performed in a random selection mode. The function setting for the variable logic / variable connection unit 1 can also be performed in the random selection mode.
Therefore, the function can be set for each of the variable logic / variable connection units 1 one by one and the verification can be sequentially performed. For example, FIG.
As shown in FIG. 1, write data (control data), a write address, and comparison data for verification are prepared for performing function setting on a variable logic / variable connection unit or the like for a test (S1). A random selection mode is set in the FPGA 70, control data is written into the first variable logic / variable connection unit 1, and a predetermined wiring path variable circuit is provided so that the result of the logic operation of the variable logic / variable connection unit can be sampled externally. 24 and the logic of the variable external input / output circuit 7 are set (S2). Then, the tester 71 reads the result of the logical operation of the variable logic / variable connection unit 1 based on the written control data, compares the result with the expected value data, and determines whether the variable logic / variable connection unit 1 has a defect. A determination is made (S3). Then, the random selection address is updated, and the last variable logic
The verification operation is repeated up to the variable connection unit 1.

Further, since the full selection mode can be set, the same logical function is set in each variable logic / variable connection unit 1, and a defective portion is initially or efficiently pointed out by a simple device test. be able to. After that, by performing a device test in the random selection mode only on a portion where no defect is found, it is possible to find a defective portion that was not found by an initial simple test.

As described above, since the FPGA 70 has the random selection mode and the batch selection mode, if these are set as desired and a device test is performed, the device test time can be reduced. In addition, since the verification can be performed for each variable logic / variable connection unit by specifying an address in the random selection mode, the FPG
The device test time of the FPGA can be reduced as compared with the configuration in which the test can be performed only after the logical function is set for the entire A. In addition, flexibility can be obtained in the test method.

The circuit 6 is programmed in the fuse program according to the result of the device test, and the logic function of the defective variable logic block 27 is replaced by the spare variable logic block 18 as described above.

<< Rescue of Normal Signal Wiring >> Next, a semiconductor integrated circuit which can be repaired by replacing defective portions of the normal signal wiring with spare signal wiring will be described.

FIG. 22 shows a second example in which the semiconductor integrated circuit according to the present invention is applied to an FPGA. FIG. 2 exclusively shows a configuration in which when a normal signal wiring has a defect, only the defective part is replaced with a spare signal wiring. The basic configuration of the FPGA shown in FIG. 22 is the same as the FPGA described with reference to FIGS. However, in FIG. 22, a configuration for repairing a defective variable logic block is omitted. Elements having the same functions as the circuit elements already described with reference to FIGS. 1 to 3 are denoted by the same reference numerals.

FIG. 22 representatively shows two variable logic / variable connection units 1 arranged in the row direction. In the configuration shown in the figure, replacement of a defect with respect to the normal signal wiring 23 is performed by using the portion of the normal signal wiring 23 interposed between the wiring path variable circuits 24 as a minimum unit. Accordingly, the minimum unit used for replacing the defective portion of the normal signal wiring 23 is the spare signal wiring 127. Here, the case where the normal signal wiring in the vertical direction can be repaired will be described.
In order to connect the variable logic / variable connection unit 1 to the spare signal wiring 127 while bypassing the defective portion of the regular signal wiring 23, for example, the spare signal Detour signal wirings 125 and 126 connected to the wiring 127 are arranged. In order to bypass the defective portion of the normal signal wiring 23 and connect the wiring path variable circuit 24 to the spare signal wiring 127, for example, the spare signal wiring 127 is arranged along the row direction in which the wiring path variable circuit 24 is juxtaposed. Signal wirings 168 and 167 are provided. The spare signal line 127 and the bypass signal line 125,
Reference numerals 126, 167, and 168 are examples of second spare signal lines used to remedy defects in the normal signal lines.

In the configuration shown in FIG. 22, the switch circuit 20A of the variable connection section includes the normal signal line 23 or the bypass signal line 1
26 is connected to the logical core 27A. When the control data set in the latch circuit 20B indicates an input operation,
If the rescue instruction signal 154 is inactive, the former input operation is selected, and if the rescue instruction signal 154 is active, the latter input operation is selected. The switch circuit 21A of the variable connection unit connects the output signal from the logic core 27A to the normal signal wiring 23 or the bypass signal wiring 125. When the control data set in the latch circuit 21B indicates an output operation, the former output operation is selected if the repair instruction signal 155 is inactive, and the latter output operation is selected if the relief instruction signal 155 is active. Other configurations of the variable logic / variable connection unit 1 are the same as those described above, and thus detailed description thereof will be omitted. The signal logic values of the repair instruction signals 154 and 155 are determined in accordance with the program state of the fuse program circuit 6, as in the case of FIG.

In FIG. 22, the wiring path variable circuit 24
2 can programmably determine the connection mode between the front, rear, left, and right regular signal wirings, for example, as in FIG. Further, in consideration of, for example, rescue of the normal signal wiring in the vertical direction, the wiring path variable circuit 24 is configured such that when the upper and lower normal signal wirings 23 are connected by the user program information 157,
According to the rescue instruction signal signals 160 and 156, the bypass signal wiring 167 is replaced by the lower normal signal wiring 23 instead of the upper normal signal line 23, and the bypass signal wiring 168 is replaced by the upper normal signal line 23 instead of the lower normal signal line 23. It can be selectively connected to the signal wiring 23.

In the above configuration, for example, it is assumed that a signal path indicated by a broken line (a) is a normal signal path. At this time, assuming that there is a defect such as disconnection in the portion indicated by (c) in the normal signal wiring 23, the repair instruction signal 155, 1
54, according to the state of the control signals 160, 156, and 157 for the wiring path variable circuit 24 connected to the defective normal signal wiring, a bypass path indicated by a chain line (b) can be formed.

FIG. 23 shows an example of an array of variable logic / variable connection units 1 to which the basic circuit configuration shown in FIG. 22 is applied. In FIG. 23, there are a plurality of normal signal wirings 23 laid vertically and horizontally, and accordingly, a plurality of wiring path variable circuits 24, detour signal wirings 167 and 168, spare signal wiring 127 and detour signal wirings 125 and 126 are also provided. I have. Other configurations are the same as those in FIG. FIG.
3 will be described in detail.

In FIG. 23, 1-1, 1-2, 1-4,
1-5 is a variable logic / variable connection unit. FIG. 23 illustrates the wiring in the vertical direction. The same applies to the horizontal wiring.

For example, the variable logic / variable connection unit 1
Attention is paid to 2, 1-5 and 1-1. The logic functions programmed by the user are connected to the respective variable logic / variable connection units 1-
Logical cores 27A-2, 27A- in 2, 1-5 and 1-1
5, 27A-1. The variable logic / variable connection units 1-2, 1-5, and 1-1 are connected to the variable connection units 20A and 21A whose functions are set by latch data of the latch circuits 20B and 21B, for example, the normal signal wiring 23-1 and the wiring. It is assumed that they are connected to each other via the path variable circuit 24-1 and the normal signal wiring 23-2. The signal flow is as follows: the logic core 27A-2, the switch circuit 21A-2 of the variable connection unit, the normal signal wiring 23-1, and the switch circuit 20A-5 of the variable connection unit, the logic core 27A-5, and the normal signal wiring 23. -1 to the wiring path variable circuit 24-1,
Normal signal wiring 23-2, switch circuit 20 of variable connection unit
A-1 and the path of the logic 27A-1 are to be followed. The wiring path variable circuit 24-1 includes the regular signal wiring 23-1.
And 23-2 are connected.

Here, a case where the normal signal wiring 23-1 has a defect and the switching to the spare signal wiring 127-1 will be described. When the normal signal wiring 23-1 has a defect, the repair instruction signals 155-2, 154-5, and 160-1 are activated. The switch circuit 21A-2 in the variable logic / variable connection unit 1-2 sets the repair instruction signal 155-2 to a value indicating a defect of the normal signal wiring 23-1, for example, a logical value "0". The connection to the wiring 23-1 is canceled, and the bypass signal wiring 125-1 is selected as the output destination.

In the switch circuit 20A-5 in the variable logic / variable connection unit 1-5, since the rescue instruction signal 154-5 is set to the logical value "0" indicating the defect of the normal signal wiring 23-1. The input from the normal signal wiring 23-1 is canceled, and the input from the bypass signal wiring 126-1 is selected. Since the bypass signal lines 125-1 and 126-1 are both connected to the spare signal line 127-1, the connection relationship between the variable logic / variable connection units 1-2 and 1-5 is maintained.

Since the repair instruction signal 160-1 having a logical value "0" indicating a defect of the normal signal wiring 23-1 is given to the wiring path variable circuit 24-1, the normal signal wiring 23-1 is provided. The connection between the detour signal wiring 167-1 and the regular signal wiring 23-2 is discontinued. Since the bypass signal wiring 167-1 is also connected to the spare signal wiring 127-1, the connection relationship with the variable logic / variable connection units 1-2 and 1-5 is maintained. As can be seen from FIG. 23, only the normal signal line in which a defect has occurred can be switched to the spare signal line 127.

FIG. 24 shows an example of the variable logic / variable connection unit 1 described with reference to FIG. 24, components having the same functions as those of the circuit elements described in FIG. 4 are denoted by the same reference numerals. Reference numerals 20B and 21B denote latch circuits that hold user program information as control information for determining the connection state of the switch circuits 20A and 21A. The pass transistor 128 is a logical core 2
7A is selectively connected to the bypass signal wiring 126. The pass transistor 29 selectively connects the normal signal wiring 23 to the logic core 27A. The pass transistors 128, 2
9 is a NOR (NOR) gate 56-which receives the rescue instruction signal 154 and the user program information of the latch circuit 20B as inputs.
2, 56-3.

FIG. 25A shows an operation mode of switch circuit 20A in FIG. Relief instruction signal 1
When both the user program information of the latch circuit 54 and the user program information of the latch circuit 20B have the logical value “0”, the pass transistor 128 is turned on, and the logical core 27A is connected to the bypass signal line 126. When the rescue instruction signal 154 has the logical value “1” and the latch circuit 2
When the user program information of 0B is a logical value “0”, the pass transistor 29 is turned on and the normal signal line 23 is turned on.
Is connected to the logical core 27A. In other cases, the pass transistors 128 and 29 are both turned off, and the logic core 27A is disconnected from the normal signal wiring 23.

Similarly, the switch circuit 21A includes a pass transistor 131 for connecting the bypass signal line 125 to the logical core 27A, a pass transistor 30 for connecting the logical core 27A to the normal signal line 23, and a repair instruction signal 155 and the latch circuit 21B. And NOR gates 57-2 and 57-3 which receive the user program information as input.

FIG. 25B shows the operation of the switch circuit 21A in FIG. Relief instruction signal 1
When both the user program information 55 and the user program information of the latch circuit 21B have the logical value “0”, the pass transistor 131 is turned on, and connects the logical core 27A to the bypass signal wiring 125. When the rescue instruction signal 155 has the logical value “1” and the user program information of the latch circuit 21B has the logical value “0”, the pass transistor 30 is turned on, and the logical core 27A
Are connected to the normal signal wiring 23. In other cases, the pass transistors 131 and 30 are both turned off, and the core logic 27A is disconnected from the normal signal wiring 23.

FIG. 26 shows an example of the basic unit circuit 24U1 constituting the wiring path variable circuit 24 shown in FIG. The basic unit circuit 24U1 shown in FIG.
This is a circuit for realizing the middle vertical connection path P1 or the horizontal connection path P2. A pass transistor indicated by 170 in FIG. 26 corresponds to T1 or T2 in FIG.
The pass transistor 170 is selectively connected to the normal signal line 23-.
1 is connected to the normal signal wiring 23-2. The pass transistor 171 connects the bypass signal line 167 to the normal signal line 23-2.
Connect to The pass transistor 172 is a bypass signal line 1
68 is connected to the normal signal wiring 23-1. These pass transistors 170 to 172 serve as repair instruction signals 160, 1
The control is controlled by NOR gates 180A, 180B, 180C and a NAND gate 180D which receive 56 and user program information 157 as inputs.

FIG. 27 shows the basic unit circuit 24U1 of FIG.
Is shown. The rescue instruction signals 160 and 156 have a logical value of “1”, and the user program information 157 has a logical value of “1”.
When the value is "0", only the pass transistor 170 is turned on, and the normal signal line 23-1 is connected to the normal signal line 23-2. Both the repair instruction signal 160 and the user program information 157 have the logical value "0", When the repair instruction signal 156 has the logical value “1”, the pass transistor 171 is turned on, and the bypass signal line 167 is connected to the normal signal line 23-2. When the value of the relief instruction signal 160 is "1" and the value of the relief instruction signal 160 is "1", the pass transistor 172 is turned on, and the bypass signal line 168 is connected to the normal signal line 23-.
Connected to 1. When the user program information 157 has the logical value "1", the pass transistors 170, 171,
172 are both turned off. With the configuration in FIG. 26,
Only the normal signal line in which a defect has occurred can be connected to the spare signal line 127 via the bypass signal line.

FIG. 28 shows an example of another basic unit circuit 24U2 applicable to the wiring path variable circuit 24 shown in FIG. The basic unit circuit 24U2 shown in FIG.
This circuit realizes the connection path P4 in FIG. 12, and can be applied to the connection paths P3, P5, and P6. In FIG. 28, 1
The pass transistor denoted by 75 corresponds to the transistors T3, T4, T5, and T6 in FIG. The pass transistor 175 selectively connects the normal signal line 23-1 to the normal signal line 23-3. The pass transistor 174 connects the bypass signal line 167 to the normal signal line 23-3. The pass transistor 173 connects the bypass signal line 191 to the normal signal line 23-1. These pass transistors 173 to 175 receive the repair instruction signals 160 and 159 and a signal from the user program information 158 as inputs.
It is controlled by R gates 181A, 181B, 181C and NAND gate 181D.

FIG. 29 shows the operation of the basic unit circuit 24U2. When the repair instruction signals 160 and 159 have the logical value “1” and the user program information 158 has the logical value “0”, only the pass transistor 175 is turned on,
The regular signal wiring 23-1 and the regular signal wiring 23-3 are connected. When both the signal 160 and the user program information 158 have the logical value “0” and the signal 159 has the logical value “1”, the pass transistor 174 is turned on and the bypass signal wiring 16 is turned on.
7 is connected to the normal signal wiring 23-3. When both the signal 159 and the user program information 158 have the logical value “0” and the signal 160 has the logical value “1”, the pass transistor 173 is turned on, and the bypass signal line 191 is connected to the normal signal line 2.
3-1. When the user program information 158 has the logical value "1", the pass transistors 175, 174,
173 are both turned off.

FIG. 30 shows an example of still another basic unit circuit 24U3 constituting the wiring path variable circuit 24 shown in FIG. Basic unit circuit 24U3 shown in FIG.
Is a circuit for realizing the connection path P4 in FIG. 12, and is also applicable to the connection paths P3, P5, and P6. In particular, the normal signal lines 23-5 in the vertical direction are connected vertically without intervening a switch.

The pass transistor 176 selectively connects the normal signal line 23-5 to the normal signal line 23-3. The pass transistor 177 connects the bypass signal line 167 to the normal signal line 23-3. The pass transistor 178 connects the vertical bypass signal line 191 to the normal signal line 23-5. These pass transistors 176, 177, 1
Reference numeral 78 designates NOR gates 182A and 182 for inputting the rescue instruction signals 160 and 162 and the user program information 161.
The switch is controlled by a control signal formed by B, 182C and the NAND gate 182D.

FIG. 31 shows the basic unit circuit 24U3 of FIG.
Is shown. The rescue instruction signals 160 and 162 have the logical value “1”, and the user program information 161 has the logical value “1”.
When the value is "0", only the pass transistor 176 is turned on, and the normal signal line 23-5 is connected to the normal signal line 23-3. Signal 162 is a logical value "
When it is "1", the pass transistor 177 is turned on, and the bypass signal wiring 167 is connected to the normal signal wiring 23-3. When the value is “1”, the pass transistor 178 is turned on, and the bypass signal line 191 is connected to the normal signal line 23-5. Both of the switches 177 and 178 are turned off, so that only the defective line can be switched to the spare signal line.

FIGS. 32 to 35 show the layout of the spare signal lines 127 with respect to the normal signal lines 29. FIG. In each figure, an array of variable logic / variable connection units 1 is representatively shown. The bypass signal wirings 125 and 12
6, 167 and 168 are not shown. In FIG. 32, the spare signal lines 127 are arranged in columns at the right end of the array of the variable logic / variable connection units 1 and arranged in rows at the lower end of the array. According to this configuration, the increase in the chip area due to the provision of the spare signal wiring 127 can be suppressed as much as possible, and the defect of the regular signal wiring can be relieved.

In FIG. 33, the spare signal lines 127 are arranged in a matrix at the center of the array of the variable logic / variable connection units 1. According to this configuration, the distance from the spare signal wiring to the farthest variable logic / variable connection unit 1 can be reduced.

In the layout configuration of FIG. 34, spare signal lines 127 are arranged in a matrix at a ratio of one for every two normal signal lines 127. According to this configuration, the distance from the spare signal wiring to the farthest variable logic / variable connection unit 1 can be further reduced.

In the configuration of FIG. 35, spare signal lines 127 are arranged in a matrix at a ratio of one for each normal signal line 127. According to this, the distance to the variable logic / variable connection unit 1 farthest from the spare signal wiring can be further reduced.

<< Rescue of Variable Logic Block and Normal Signal Wiring >> Next, a semiconductor integrated circuit which can repair both the variable logic block and the normal signal wiring will be described. FIG. 36 shows a basic configuration capable of repairing both the variable logic block and the normal signal wiring. The configuration shown in the figure is obtained by combining the configurations shown in FIGS. 2 and 22 respectively. Circuit blocks having the same functions as those in FIGS. 2 and 22 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 36, for example, it is assumed that the normal signal path based on the logic determined by the user program information is the signal path shown by the broken line (a) in FIG. At this time, for example, it is assumed that there is a defect in the normal signal wiring shown in (c) of the figure and a defect in the variable logic block 27A shown in (d) of the figure. Then, the normal signal wiring 23 shown in FIG.
(E) so that the variable logic block 27A in (d) is replaced by the spare variable logic block 18A.
Switch circuits 21A and 20 shown in (f) and (g)
The state of the repair instruction signal is programmed so as to determine the state of the wiring path variable circuit 24 indicated by A and (h). Thereby, a detour path indicated by a chain line (b) can be formed.

FIG. 37 shows an example of an array of the variable logic / variable connection unit 1 and the spare variable logic unit 18 to which the basic circuit configuration shown in FIG. 36 is applied. FIG.
In FIG. 7, a plurality of normal signal wirings 23 are laid vertically and horizontally, and accordingly, a plurality of wiring path variable circuits 24, detour signal wirings 167 and 168, spare signal wiring 127, and detour signal wirings 125 and 126 are also provided. Other configurations are the same as those in FIG.

FIG. 38 shows the variable logic applied to FIG.
One example of the variable connection unit 1 is shown. The variable logic / variable connection unit 1 shown in FIG.
Has the configurations of the switch circuits 20A and 21A shown in FIG.

FIG. 39A shows the operation of switch circuit 20A of FIG. When the rescue instruction signal 154 and the user program information of the latch circuit 20B are both logical value "0" and the rescue instruction signal 54 is logical value "1", the pass transistor 128 is turned on and the logic core 27A
Are connected to the bypass signal wiring 126.

When the rescue instruction signal 154 has a logical value "1", the user program information of the latch circuit 20B has a logical value "0", and the rescue instruction signal 54 has a logical value "1", the pass transistor 29 is turned on. The regular signal wiring 23 is the logical core 2
7A.

When the rescue instruction signal 154 has a logical value "1", the user program information of the latch circuit 20B has a logical value "0", and the rescue instruction signal 54 has a logical value "0", the pass transistor 28 is turned on. The normal signal line 23 is connected to the spare signal line 25 to the spare variable logic block 18.

When the user program information of the latch circuit 20B has the logical value "1", the pass transistors 28, 128, 2
9 are both turned off, and the logic core 27A is cut off from the normal signal wiring 23. At this time, the number of pass transistors entering the signal propagation path is the same regardless of whether the connection to the spare variable logic block 18 is switched or not.

FIG. 39B shows an operation mode of the switch circuit 21A in FIG. Relief instruction signal 15
When the user program information of the latch 5 and the user program information of the latch circuit 21B are both logical values "0", the pass transistor 131 is turned on, and the logical core 27A is connected to the bypass signal wiring 125.

When the rescue instruction signal 155 has a logical value “1” and the user program information of the latch circuit 21B has a logical value “0”, the pass transistor 30 is turned on, and the logical core 27A is connected to the normal signal line 23. . The rescue instruction signal 155 has a logical value "1", the user program information of the latch circuit 21B has a logical value "0", and the rescue instruction signal 54 has a logical value.
When it is "0", the pass transistor 31 is turned on,
The normal signal wiring 23 is connected to a spare signal wiring 26 to the spare variable logic block 18. When the user program information of the latch circuit 21B has the logical value “1”, the pass transistors 131, 31, and 30 are all turned off, and the logical core 27A is disconnected from the normal signal wiring 23.

As described above, by using the variable logic / variable connection unit 1 shown in FIG.
4 can be switched to the spare signal line 127 only with the defective signal line 23 as a minimum unit, and the variable logic block 2 where the defect has occurred can be switched.
Only 7 can be switched to the spare variable logic block 18.

FIG. 40 shows the variable logic applied to FIG.
Still another example of the variable connection unit 1 is shown. In the configuration of the switch circuits 20A and 21A of FIG.
If the variable logic / variable connection unit 1 having a defect A is directly connected to the defective normal signal wiring 23, it cannot be remedied. That is, when the logic core 27A is defective, the pass transistors 29 and 30 in the switch circuits 20A and 21A in FIG. 38 are turned off, so that the connection between the bypass signal wiring 126 and the spare signal wiring 25 is reduced.
In addition, the connection between the bypass signal wiring 125 and the spare signal wiring 26 becomes impossible.

The switch circuits 20A, 20A shown in FIG.
1A, a pass transistor 170 for selectively conducting between the spare signal line 25 and the bypass signal line 126 and a pass transistor 171 for selectively conducting between the spare signal line 26 and the bypass signal line 125 are added. . Other configurations are the same as those in FIG.

FIG. 41A shows an operation mode of switch circuit 20A in FIG. Relief instruction signal 1
When both the user program information 54 and the user program information of the latch circuit 20B have the logical value "0" and the rescue instruction signal 54 has the logical value "1", the pass transistor 128 is turned on and the logical core 27A is connected to the bypass signal line 126. You.

When the rescue instruction signal 154 has a logical value "1", the user program information of the latch circuit 20B has a logical value "0", and the rescue instruction signal 54 has a logical value "1", the pass transistor 29 is turned on. , Normal signal wiring 23 is connected to logic core 27A.

When the rescue instruction signal 154 has a logical value “1”, the user program information of the latch circuit 20B has a logical value “0”, and the rescue instruction signal 54 has a logical value “0”, the pass transistor 2
8 is turned on, and the normal signal wiring 23 is connected to the spare signal wiring 25 to the spare variable variable logic block 18.

When the rescue instruction signal 154 has a logical value "0", the rescue instruction signal 54 has a logical value "0", and the user program information of the latch circuit 20B has a logical value "0", the pass transistor 170 is turned on. The bypass signal wiring 126 is connected to the spare signal wiring 25 to the spare variable logic block.

When the user program information of the latch circuit 20B is a logical value "1", the pass transistors 28, 12
8 and 29 are both turned off, and the logic core 27A is disconnected from the normal signal wiring 23. At this time, the number of pass transistors that enter the signal propagation path is the same whether the switching is made to the spare variable logic block or not.

FIG. 41B shows the operation of the switch 21A in FIG. Relief instruction signal 15
5. When both the user program information of the latch circuit 21B is the logical value "0", the pass transistor 131 is turned on, and the logical core 27A is connected to the bypass signal wiring 125 to the spare signal wiring 27.

When the rescue instruction signal 155 has a logical value "1" and the user program information of the latch circuit 21B has a logical value "0", the pass transistor 30 is turned on, and the logic core 27A is connected to the normal signal wiring 23. You.

When the rescue instruction signal 155 has a logical value "1", the user program information of the latch circuit 21B has a logical value "0", and the rescue instruction signal 54 has a logical value "0", the pass transistor 31 is turned on. Signal wiring 23 is connected to spare signal wiring 26 to spare variable logic block 18.

When the rescue instruction signal 155 is a logical value "0", the rescue instruction signal 54 is a logical value "0", and the user program information of the latch circuit 21B is a logical value "0", the pass transistor 171 is turned on. The bypass signal wiring 125 to the spare signal wiring 127 is connected to the spare signal wiring 26 to the spare variable logic block 18.

When the user program information 21B has the logical value "1"
At times, the pass transistors 131, 31, and 30 are all turned off, and the logic core 27A is disconnected from the normal signal wiring 23.

As is clear from the above, if the variable logic / variable connection unit 1 shown in FIG. 40 is employed, the variable logic / variable connection unit 1 having a defect in the
However, if the pass transistors 170 and 171 are turned on even if they are directly connected to the defective normal signal wiring 23, both defects can be relieved by the spare variable logic block 18 and the spare signal wiring 127. . FIG.
FIG. 2 shows an example of such a relief mode. For example, it is assumed that a normal signal path based on the logic determined by the user program information is a signal path indicated by a broken line (a) in FIG. At this time, for example, it is assumed that there is a defect in the normal signal wiring shown in (c) of the figure and a defect in the variable logic block 27A shown in (d) of the figure. Then, (E), (F), and (G) show that the normal signal wiring 23 of (A) is replaced with the spare signal wiring 127 and the variable logic block 27A of (D) is replaced with the spare variable logic block 18A. The state of the repair instruction signal is programmed so as to determine the states of the switch circuits 21A and 20A and the wiring path variable circuit 24 shown in (h). Thereby, a detour path indicated by a chain line (b) can be formed. By passing the signal through this detour path, it is possible to remedy both the normal signal wiring 23 in (c) and the logic core 27A in (d).

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto, and various changes can be made without departing from the gist of the invention. No.

For example, variable logic arranged in a matrix
The number of variable connection units or variable logic blocks is not limited to the above embodiment. In practice, the number will be much larger than in the case described above. The logic core is not limited to the look-up table format, but may include a plurality of logic gates and partially include a configuration for selecting any one of the logic gates according to the setting contents of the storage circuit. Further, the layout and the number of the first spare signal wiring and the second spare signal wiring are not limited to the above description, and can be appropriately changed. Further, as the specific logical configuration of the variable connection unit and the wiring path variable unit, various logics other than the above description can be adopted.

[0130]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the variable connection section provided corresponding to each variable logic block can connect the spare variable logic block to the normal signal wiring instead of the variable logic block, thereby providing one defective variable logic block. A block can be rescued by one spare variable logic block. Therefore, it is possible to cope with a plurality of randomly generated defects of the variable logic block while minimizing an increase in wasted area. Then, the logic function setting means can set the same logic function as the logic function to be set in the defect variable logic block in the spare variable logic block. Since the logic function setting operation is interlocked with the replacement instruction by the instruction means, the semiconductor integrated circuit is not completely different from the semiconductor integrated circuit that has not been remedied by the programming of the instruction means in the test process. It can be.

A spare signal line for connecting the variable connection section to the spare variable logic block is further provided, and the spare signal line is variably connected to a plurality of variable logic blocks for one spare variable logic block. The common connection to the sections makes it possible to reduce the number of wires for coupling the variable logic block to the variable connection section.

At this time, the spare variable logic block can be connected to an intermediate portion of the spare signal wiring, and variable connection portions of the variable logic block can be connected to both sides thereof. According to this, the maximum signal propagation distance from the variable connection section to the spare variable logic block can be shortened.

By assigning an address to the logical function setting storage means for each variable logical block, data setting for the storage means can be made more efficient.

A separation circuit and a compulsion circuit are provided in the variable connection section, and when replacing with a spare variable logic block, a state in which the normal signal wiring is connected to the spare signal wiring is forcibly attained. , The output of the logic core is forced to one of the power supply voltages even if the output is set to an intermediate level of the power supply voltage, so that it is possible to suppress the occurrence of undesired through current inside the logic core.

According to the present invention from the viewpoint of relieving a defect in the normal signal wiring, if the normal signal wiring receiving the output of the variable logic block has a defect, the variable connection unit leads the output to the spare signal wiring. Also, when the normal signal wiring of the signal input path of the variable logic block is defective, the variable connection unit causes the signal to be input from the spare signal wiring to the variable logic block instead of the normal signal wiring, and Since the defective portion of the signal wiring is separated from the signal transmission path and the spare signal wiring is merged with the normal signal wiring having no defect, only the portion of the regular signal wiring where the defect has occurred is replaced with the spare signal wiring, and the defect is replaced. Can be remedied.

Accordingly, only the defective signal wiring portion is replaced with the spare signal wiring. Therefore, it is not necessary to replace the variable logic blocks in units of columns or rows to repair defects of the normal signal wiring. Efficient remedy can be performed for the defect.

According to the present invention from the viewpoint of repairing both the normal signal wiring and the variable logic block, both the defect of the normal signal wiring and the defect of the variable logic block can be efficiently repaired.

[Brief description of the drawings]

FIG. 1 shows an FP as an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is an overall block diagram of a GA.

FIG. 2 is a block diagram illustrating an example of a detailed connection relationship between a variable logic / variable connection unit, a spare variable logic block, and a wiring path variable circuit in FIG. 1;

FIG. 3 is an explanatory diagram for explaining a replacement operation by a spare variable logic block;

FIG. 4 is a logic circuit diagram showing a detailed example of a switch circuit of a variable connection unit included in the variable logic / variable connection unit.

FIG. 5 is an explanatory diagram showing an operation mode of a switch circuit of the variable connection unit in FIG.

FIG. 6 is a logic circuit diagram showing another example of the switch circuit of the variable connection unit included in the variable logic / variable connection unit.

FIG. 7 is an explanatory diagram showing an operation mode of the switch circuit of the variable connection unit in FIG. 6;

FIG. 8 is a logic circuit diagram showing still another example of the switch circuit of the variable connection unit included in the variable logic / variable connection unit.

FIG. 9 is an explanatory diagram showing an operation mode of the switch circuit of the variable connection unit in FIG. 8;

FIG. 10 is a circuit diagram showing an example of a variable logic block in a look-up table format.

FIG. 11 is a circuit diagram showing an example of a wiring path variable circuit.

FIG. 12 is a functional explanatory diagram of the wiring path variable circuit of FIG. 11;

FIG. 13 is an overall block diagram showing another example of the FPGA.

FIG. 14 is an explanatory diagram of a layout image of an FPGA in which spare variable logic blocks are arranged in one row and one column at an end of a variable logic / variable connection unit.

FIG. 15 is an explanatory diagram of a layout image of an FPGA in which spare variable logic blocks are provided only in the column direction.

FIG. 16 shows an FPG in which a spare variable logic block is arranged at an intermediate portion in the matrix direction of an array of variable logic / variable connection units.
FIG. 4 is an explanatory diagram of a layout image of A.

FIG. 17 shows an FPGA in which a spare variable logic block is arranged in the middle of the array of variable logic / variable connection units in the row direction.
FIG. 4 is an explanatory diagram of a layout image.

18 is an example block diagram of a spare variable logic block suitable for arranging a spare variable logic block in the middle of an array of variable logic / variable connection units as in FIG. 16 or FIG. 17;

FIG. 19 shows F near the variable logic / variable connection unit.
It is a schematic device sectional view of PGA.

FIG. 20 is a system configuration diagram when a device test is performed on the FPGA as shown in FIG. 1;

FIG. 21 is a flowchart illustrating an example of an operation when a function test is performed on a variable logic block in a random selection mode to perform a device test on an FPGA;

FIG. 22 is a block diagram illustrating an example of a basic circuit configuration of a semiconductor integrated circuit that can be repaired by replacing a defective portion of a normal signal line with a spare signal line.

FIG. 23 is a block diagram showing an example of an array of variable logic / variable connection units to which the basic circuit configuration shown in FIG. 22 is applied.

24 is a logic circuit diagram showing an example of the variable logic / variable connection unit described in FIG.

FIG. 25 is an explanatory diagram illustrating an operation mode of the switch circuit of the variable connection unit illustrated in FIG. 24;

26 is a logic circuit diagram showing an example of a basic unit circuit constituting the wiring path variable circuit shown in FIG.

FIG. 27 is an explanatory diagram showing an operation mode of the basic unit circuit of FIG. 26;

FIG. 28 is a logic circuit diagram showing another example of the basic unit circuit forming the wiring path variable circuit.

FIG. 29 is an explanatory diagram showing an operation mode of the basic unit circuit of FIG. 28;

FIG. 30 is a logic circuit diagram showing still another example of the basic unit circuit forming the wiring path variable circuit.

FIG. 31 is an explanatory diagram showing an operation mode of the basic unit circuit of FIG. 30;

FIG. 32 is an explanatory diagram showing a layout image of an array of variable logic / variable connection units in which spare signal lines are arranged in one row and one column at an end of a normal signal line.

FIG. 33 is an explanatory diagram showing a layout image of an array of variable logic / variable connection units in which spare signal lines are arranged in one row and one column at the center of the normal signal lines in the matrix direction.

FIG. 34 shows one row in the middle of two rows of normal signal wiring,
FIG. 9 is an explanatory diagram showing, by a layout image, an array of variable logic / variable connection units in which one column of spare signal wirings is arranged between two columns.

FIG. 35 shows one row near the normal signal wiring,
FIG. 4 is an explanatory diagram showing a layout image of an array of variable logic / variable connection units in which one column of spare signal wiring is arranged in the vicinity of one column.

FIG. 36 is a block diagram showing an example of a basic configuration that enables both a variable logic block and a normal signal wiring to be repaired.

FIG. 37 is a block diagram showing an example of an array of variable logic / variable connection units and spare variable logic units to which the basic circuit configuration shown in FIG. 36 is applied.

FIG. 38 is a logic circuit diagram showing an example of a variable logic / variable connection unit applied to FIG. 36.

FIG. 39 is an explanatory diagram showing an operation mode of a switch circuit included in the variable connection unit of FIG. 38;

FIG. 40 is a logic circuit diagram showing another example of the variable logic / variable connection unit applied to FIG. 36;

FIG. 41 is an explanatory diagram showing an operation mode of a switch circuit included in the variable connection unit of FIG. 40;

FIG. 42 is a block diagram showing an example of an operation of repairing both defects of the logic core and the normal signal wiring connected thereto by using the spare variable logic block and the spare signal wiring.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Variable logic / variable connection unit 2 Address decode logic circuit 6 Fuse program circuit 8 Address generation circuit 9 Control data writing circuit 10A, 10B Operation mode setting terminal 11 Clock input terminal 12 Data input terminal 13 X address 14 Y address 15-1, 15-2, 15-3 Y selection signal 15-4 Spare Y selection signal 16-1, 16-2, 16-3 X selection signal 16-4 Spare X selection signal 17 Control data line 18, 18-1 Spare variable logic Block 18A Logical core 18B Latch circuit 20, 21 Variable connection unit 20A, 20B Switch circuit 20B, 21B Latch circuit 23 Regular signal wiring 24 Wiring path variable circuit 24A Switch circuit 24B Latch circuit 25 Spare signal wiring for redundant input 26 Redundant output Spare signal wiring 27 Variable logic block Lock 27A Logic core 27B Latch circuit 39-A, 39-B Level forcing transistor 40-A, 40-B Isolation transistor 127 Spare signal wiring 125, 126, 167, 168, 191 Detour signal wiring

Claims (14)

[Claims] 1. A plurality of variable logic blocks whose logic functions can be variably set, a spare variable logic block whose logic functions can be set variably and can replace said variable logic blocks, and a plurality of normal signal wirings And a connection relation between the variable logic block and the normal signal wiring, which is provided corresponding to the variable logic block, is variably set, and the connection between the normal signal wiring and the variable logic block is defined as the normal signal wiring. A variable connection unit that can be replaced with a connection with the spare variable logic block, a replacement instruction unit that instructs the replacement by the variable connection unit, and a setting of a connection mode for the variable connection unit; The logical function set in the variable logical block to be replaced by the instruction means is set in the spare variable logical block of the replacement destination Control means for controlling the setting of the logic function for the variable logic block and the spare variable logic block. 2. The semiconductor integrated circuit according to claim 1, further comprising a wiring path variable means for variably setting an interconnection relationship between said plurality of normal signal wirings. 3. The variable connection section connects the spare variable logic block to a normal signal wire via a spare signal wire, and the spare signal wire has a plurality of spare variable logic blocks for one spare variable logic block. 3. The semiconductor integrated circuit according to claim 2, wherein the variable connection is shared. 4. The semiconductor integrated circuit according to claim 3, wherein said spare variable logic block is connected to an intermediate portion of a spare signal line, and variable connection portions are connected to both sides thereof. 5. The variable logic blocks are arranged in a matrix, the spare variable logic blocks are arranged in a column direction, a row direction, or a matrix direction of the variable logic blocks, and the normal signal lines are arranged along the variable logic blocks. Arranged in a matrix direction, the wiring path variable means regulates interconnection at intersections of normal signal wirings, the spare signal wirings are arranged in a column direction or a row direction of a variable logic block, and the variable connection portions are corresponded. 4. The semiconductor integrated circuit according to claim 3, wherein the normal signal wiring is connectable to the nearest spare signal wiring instead of the connection between the variable logic block and the normal signal wiring. 6. The variable logic block includes a logic core,
Information for designating a logical function to be realized by the logical core includes first storage means set by the control means; the spare variable logical block includes a logical core and a logical function realized by the logical core. A second storage unit in which information for designating is set by the control unit, wherein the variable connection unit selectively connects a logic core of a corresponding variable logic block to the normal signal wiring, and A switch circuit for controlling a state in which the normal signal line is selectively connected to the spare signal line; and a third storage unit in which information for designating a switch state of the switch circuit is set by the control unit. The control means includes information to be set in the first storage means of the variable logic block corresponding to the variable connection unit instructed to be replaced by the replacement instruction means. 6. The semiconductor according to claim 3, wherein the logic function of the variable logic block is set in the second variable storage unit of the spare variable logic block, and the logic function of the variable logic block is set in the spare variable logic block. Integrated circuit. 7. The control unit includes an address signal generating unit and a decoding unit. The decoding unit decodes the address signal and stores the first and third storage units corresponding to respective variable logic blocks. A selection signal for selecting as one unit is output, and when the variable logic block of the first storage means selected by the selection signal is to be replaced, the second storage means of the spare variable logic block to be replaced is also selected. 7. The semiconductor integrated circuit according to claim 6, wherein the logic function is set by using a logic function. 8. The disconnection circuit for disconnecting the output of the third storage means from the signal input terminal of the switch circuit when the replacement is instructed by the replacement instruction means. 7. The power supply system according to claim 6, further comprising a forcing circuit for forcing a switch state of said switch circuit into a state in which said normal signal line is connected to said spare signal line.
A semiconductor integrated circuit as described in the above. 9. A plurality of variable logic blocks arranged in a matrix capable of variably setting a logic function of a logic core by setting data for a storage means, and data is supplied to the logic core of the variable logic block and supplied from the logic core. A plurality of normal signal wirings arranged in the matrix direction of the variable logic block for transmitting the output data, and logic signals are arranged in the column direction or the row direction or the matrix direction of the variable logic block and set data for the storage means. A plurality of spare variable logic blocks capable of variably setting the logic function of the core and replacing the variability logic block, and being arranged in the matrix direction of the variable logic blocks coupled to the logic core of the spare variable logic block A plurality of spare signal lines and a logical code of the variable logic block provided corresponding to each of the variable logic blocks. The connection relation between the normal signal wiring and the normal signal wiring is variably set by setting data for the storage means, and the connection between the normal signal wiring and the logic core of the variable logic block is changed to the normal signal wiring and the spare signal wiring. A variable connection unit that can be replaced with a connection, replacement instructing means for instructing the replacement by the variable connection unit, and controlling the setting of the connection mode for the variable connection unit, and replacing by the instruction of the replacement instructing means. A logical function for the variable logic block storage means and the spare variable logic block storage means such that the logic function set in the logical core of the target variable logic block is set in the logical core of the spare variable logic block to be replaced. Control means for controlling the setting of decision data. Circuit. 10. A plurality of variable logic blocks whose logic functions can be set variably, a plurality of normal signal wirings, a plurality of spare signal wirings used for relief of the normal signal wirings, and the plurality of normal signal wirings. Wiring path variable means capable of variably setting the interconnection relation between the normal signal wiring and replacing the connection between the normal signal wiring with the connection between the normal signal wiring and the spare signal wiring, and provided corresponding to the variable logic block. The connection between the variable logic block and the normal signal wiring can be set variably, and the connection between the normal signal wiring and the variable logic block can be replaced with the connection between the variable logic block and the spare signal wiring. A variable connection unit, replacement instructing means for instructing the replacement by the variable connection unit and the wiring path variable unit, and the variable connection unit and the wiring path. A semiconductor integrated circuit comprising: control means for controlling the setting of the connection mode to the road variable means and controlling the setting of the logical function to the variable logic block. 11. A plurality of variable logic blocks arranged in a matrix capable of variably setting a logic function of a logic core by setting data for a storage means, and data is supplied to the logic core of the variable logic block and supplied from the logic core. A plurality of normal signal lines arranged in the matrix direction of the variable logic block for transmitting the output data; a plurality of spare signal lines used for relieving the normal signal lines; Wiring path variable means capable of setting the connection relationship variably and replacing the connection between the normal signal wiring with the connection between the normal signal wiring and the spare signal wiring, and provided corresponding to each of the variable logic blocks The connection relationship between the logic core of the variable logic block and the normal signal wiring is variably set by data in the storage means, and A variable connection unit capable of replacing the connection between the regular signal wiring and the logic core of the variable logic block with a connection between the logic core and the spare signal wiring; and the replacement by the variable connection unit and the wiring path variable unit. Replacement instruction means for instructing, and control means for controlling the setting of the connection mode for the variable connection section and the wiring path variable means, and for controlling the setting of logic function determination data for the storage means of the variable logic block. A semiconductor integrated circuit, comprising: 12. A plurality of variable logic blocks whose logic functions can be set variably, and a spare variable logic which is connected to a first spare signal line and whose logic function can be set variably and which can replace said variable logic block. A block, a plurality of normal signal lines, and a plurality of second signal lines used for relief of the normal signal lines.
A spare signal line and a wiring path capable of variably setting an interconnecting relationship between the plurality of regular signal lines and replacing a connection between the regular signal lines with a connection between the regular signal line and the second spare signal line A variable means, provided in correspondence with the variable logic block, to variably set a connection relationship between the variable logic block and the normal signal wiring, and to connect a connection between the normal signal wiring and the variable logic block to the variable logic block. And the connection between the normal signal wiring and the variable logic block, and the connection between the regular signal wiring and the variable logic block to the connection between the normal signal wiring and the spare variable logic block via the first spare signal wiring. A variable connection unit that can perform the replacement by the variable connection unit and the wiring path variable unit; and the variable connection unit. And controlling the setting of the connection mode for the wiring path variable means, and setting the logical function set in the variable logical block to be replaced by the instruction of the replacement instruction means in the spare variable logical block of the replacement destination. Control means for controlling setting of a logic function for the variable logic block and the spare variable logic block. 13. A plurality of variable logic blocks arranged in a matrix capable of variably setting a logic function of a logic core by setting data for a storage means, and a logic core of the logic core connected to the first spare signal wiring and stored in the storage means by data of the storage means. A spare variable logic block capable of variably setting a logic function and replacing the variable logic block; and a variable logic block for supplying data to a logic core of the variable logic block and transmitting data output from the logic core. A plurality of normal signal lines arranged in the matrix direction of the logic block, a plurality of second spare signal lines used for rescue of the normal signal lines, and an interconnecting relationship between the plurality of normal signal lines are variably set. Wiring path variable means capable of replacing the connection between the normal signal wirings with the connection between the normal signal wiring and the spare signal wiring; The connection relationship between the logic core of the variable logic block and the normal signal wiring is variably set by data in the storage means, and the logic of the normal signal wiring and the variable logic block is provided. Replacing the connection with the core with the connection between the logical core and the second spare signal line, and connecting the regular signal line and the variable logic block with the regular signal line and the variable signal block via the first spare signal line. A variable connection unit that can be replaced with a connection with a spare variable logic block; a replacement instruction unit that instructs the replacement by the variable connection unit and the wiring path variable unit; and a connection to the variable connection unit and the wiring path variable unit. A logic that controls the setting of the mode and is set in the variable logic block to be replaced by the instruction of the replacement instruction means. Control means for controlling the setting of the logic function for the variable logic block and the spare variable logic block so that the function is set to the spare variable logic block of the replacement destination. . 14. The variable connection unit connects a logic core of a corresponding variable logic block to the normal signal wiring.
1 state, a second state in which the normal signal wiring is connected to the first spare signal wiring, a third state in which the normal signal wiring is connected to the second spare signal wiring, and a second state in which the first spare signal wiring is connected to the second state. 14. The semiconductor integrated circuit according to claim 12, further comprising a switch circuit capable of selectively taking a fourth state connected to the spare signal wiring.