WO2005034353A1 - Systeme de reecriture sur reseau prediffuse programmable - Google Patents

Systeme de reecriture sur reseau prediffuse programmable Download PDF

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Publication number
WO2005034353A1
WO2005034353A1 PCT/JP2003/012725 JP0312725W WO2005034353A1 WO 2005034353 A1 WO2005034353 A1 WO 2005034353A1 JP 0312725 W JP0312725 W JP 0312725W WO 2005034353 A1 WO2005034353 A1 WO 2005034353A1
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WO
WIPO (PCT)
Prior art keywords
circuit
address
information
programmable gate
gate array
Prior art date
Application number
PCT/JP2003/012725
Other languages
English (en)
Japanese (ja)
Inventor
Masaki Yamamoto
Takayasu Mochida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2005509315A priority Critical patent/JP4156626B2/ja
Priority to PCT/JP2003/012725 priority patent/WO2005034353A1/fr
Publication of WO2005034353A1 publication Critical patent/WO2005034353A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources

Definitions

  • the present invention relates to a field programmable gate array rewriting system, an address management device, and a field programmable gate array rewriting method.
  • a field programmable gate array (hereinafter simply referred to as an FPGA) add a circuit (add function) to an unused area (unused circuit part) of the circuit determination RAM while the operation is continued.
  • the following rewriting technologies are considered as rewriting technologies.
  • an address decoder is added to the circuit determination RAM.
  • circuit determination address and the circuit determination data are input into the FPGA in the FPGA operation continuation state.
  • the address decoder stores the circuit determining data in the circuit determining RAM according to the circuit determining address.
  • Patent Document 1
  • Patent Document 2
  • the user transmits the circuit determination data to the circuit determination RAM in the FPGA together with the circuit determination address.
  • the user has only to rewrite the FPG A circuit by managing the circuit determination address manually or by a method similar to manual.
  • the circuit determination data to the FPGA is transferred to the circuit determination RAM.
  • the user determines the circuit determining address for each circuit determining data.
  • the circuit determination information when rewriting a circuit of a field programmable gate array, even if a user does not give a circuit determination address of an unused area of the circuit determination information storage means, the circuit determination information is stored in the circuit determination information. It is an object of the present invention to provide a field programmable gate array rewriting system, an address X management device, and a field programmable gate array rewriting method which can be stored in an unused area of a storage means. . Disclosure of the invention
  • a rewriting system for a field programmable gate array is a circuit for indicating a storage area of the circuit determining information in a circuit determining information storage unit for storing circuit determining information which is information of a circuit to be generated.
  • Dress for decision A field programmable gate array comprising a storage destination determining means for storing the circuit determining information in the circuit determining information storage means,
  • Storage means for storing the circuit determination information
  • Address storage means for storing information of addresses not used in the circuit determination information storage means
  • the information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and Address management means having information and additional means for outputting the circuit determination address.
  • the address management means may include:
  • a control unit is provided for controlling the timing at which the circuit determining information and the circuit determining address are output from the adding unit.
  • the circuit determining information storage means stores the circuit determining information in a state where the operation of the field programmable gate array is continued. You.
  • the circuit determination information may include:
  • the information includes information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.
  • the address management means may include:
  • a writing unit that inputs the circuit determining information and the circuit determining address output from the adding unit and outputs the circuit determining information and the circuit determining address in parallel to the field programmable gate array.
  • the address management means may include:
  • the circuit determining information and the circuit determining address output from the adding means are input, and the circuit determining information and the circuit determining address are multiplexed and serially multiplexed.
  • the address storage means may include:
  • the information of the circuit determining address added to the circuit determining information by the adding means is stored as the information of the used address.
  • the circuit determination information is stored in the circuit determination information storage unit.
  • An address management device connected to a field programmable gate array including storage destination determination means for storing in a circuit determination information storage means,
  • Storage means for storing the circuit determination information
  • Address storage means for storing information on addresses not used in the circuit determination information storage means
  • the information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and Additional means for outputting information and the circuit determination address.
  • a control unit is provided for controlling the timing at which the circuit determining information and the circuit determining address are output from the adding unit.
  • the circuit determination information includes:
  • the information includes information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.
  • the circuit determining information and the circuit determining address output from the adding means are input, and the circuit determining information and the circuit determining address are multiplexed and serially output to the field programmable gate array.
  • Writing means for writing are input, and the circuit determining information and the circuit determining address are multiplexed and serially output to the field programmable gate array.
  • the address storage means stores the address data
  • the information of the circuit determining address added to the circuit determining information by the adding means is stored as the information of the used address.
  • a rewriting method of the field programmable gate array of the present invention includes a storage step of storing circuit determination information for determining a circuit generated in the field programmable gate array in a storage means,
  • the information of the unused address stored in the address storage means is added to the circuit determination information stored in the storage means as the circuit determination address, and An additional step for outputting information and the circuit determination address,
  • a circuit determining information storage step for storing the circuit determining information in the circuit determining information storage means in accordance with a circuit determining address indicating a storage area of the circuit determining information.
  • the rewriting method of the field programmable gate array of the present invention includes a control step of controlling a timing at which the circuit determining information and the circuit determining address are output from the additional step.
  • the circuit determining information storage means stores the circuit determining information in a state where the operation of the field programmable gate array is continued.
  • the circuit determining information may include: The information includes information for adding a switching circuit and a repair circuit for relieving a defect of the field programmable gate array.
  • the method for rewriting a field programmable gate array includes a writing step of making the circuit determining information and the circuit determining address output in the additional step parallel and outputting the parallel information to the field programmable gate array. Is provided.
  • the rewriting method of the field programmable gate array according to the present invention may further comprise a method of multiplexing the circuit determining information and the circuit determining address output in the adding step and serially outputting the multiplexed information to the field programmable gate array. Comprising steps.
  • the information of the circuit determining address added to the circuit determining information in the adding step is stored as the address of the used address.
  • the method includes a step of storing a used address to be stored in the means.
  • the present invention has an address management means for adding a circuit determining address to circuit determining information such as circuit determining data and outputting the FPGA which can be rewritten in an operation continuation state.
  • the circuit determination information is information for determining a circuit generated in the FPGA. This circuit determination information is created by the user and input to the address management means.
  • the circuit determination information is, for example, information indicating a logical expression of a circuit generated in FPGA.
  • the FPGA circuit generation unit has, for example, an S-RAM and a flip-flop (hereinafter, also simply referred to as FF), and the S-RAM and the flip-flop form a circuit corresponding to the circuit determination information.
  • FF flip-flop
  • a look-up table indicating an output corresponding to a predetermined input is created by S-RAM, and a predetermined delay is given by FF to form a circuit corresponding to the circuit determination information.
  • the circuit determining address is an address indicating an area for storing circuit determining information in the circuit determining information storage means. Then, in the present invention, the address storage means provided in the address management means stores the address information of the unused area in the circuit determination information storage means such as the circuit determination RAM in the FPGA.
  • the adding means adds a circuit determining address to the circuit determining information to be written in the circuit determining information storing means and outputs the information to the FPGA.
  • the user in rewriting the circuit of the FPGA, the user does not determine the address of the unused area of the circuit determination information storage means, but the circuit determination information is stored in the unused area of the circuit determination information storage means. Can be stored.
  • the unused area of the circuit determination information storage means is stored for each circuit determination information for changing the FPGA circuit. There is no need to determine the address.
  • the rewriting of the circuit of the FPGA is performed as a series of operations without the involvement of the user. It can be done by automation.
  • the address management means manages the unused addresses of the circuit determination information storage means, an additional circuit is generated in an unused area of the circuit determination information storage means while the operation of the FPGA is continued. Then, the circuit can be rewritten.
  • the circuit used for the operation is not overwritten and rewritten, so that the operation continuation state of the FPGA is changed.
  • the circuit can be rewritten while maintaining it.
  • the present invention it is possible to generate a replacement circuit and a switching circuit for a defective circuit in an operation continuation state of the FPGA to remedy the defective circuit.
  • a replacement circuit and a switching circuit for a defective circuit in an operation continuation state of the FPGA to remedy the defective circuit.
  • the present invention for example, in an exchange device or the like in which a system down is not recognized. It is possible to rewrite the FPGA circuit, such as adding functions and fixing bugs, while continuing operation.
  • a method of providing a circuit determining address and circuit determining information to a circuit determining information storage means for an FPGA that can be rewritten in an operation continuous state, that is, the circuit determining address is used.
  • the way of writing the circuit determination information into the circuit determination information storage means was undefined.
  • the circuit specification address and the interface specification between the circuit determination information and the circuit determination information storage unit are undefined.
  • the circuit determination information storage means stores the circuit determination address and the circuit determination information. It is necessary to prepare the peripheral environment of the FPGA so that the method of writing to the FPGA can be defined.
  • the storage destination determining means such as an address decoder stores which circuit determining information in which circuit determining address. It is possible to determine whether to store.
  • the address management means includes control means for controlling the circuit determining address of the adding means and the output timing of the circuit determining information, the user can control the address of the circuit determining information of the circuit to be rewritten. There is no need to decide when to enter control measures.
  • rewriting the circuit of the field programmable gate array refers to adding a new circuit to the field programmable gate array, modifying a circuit already formed on the field programmable gate array, and modifying the field programmable gate array. This includes any of the cases where the circuits already formed in the array are deleted, the case where wiring for connecting each circuit is generated, or any combination thereof.
  • field programmable gate array failures include It can include operations other than normal operations such as failure of the grammar gate array and operation delay.
  • adding means for adding a circuit determining address to circuit determining information and outputting the circuit determining information means that the circuit determining information and the circuit determining address of the circuit determining information are associated with each other and output.
  • FIG. 1 is an overall schematic diagram of a first embodiment of a field programmable gate array rewriting system of the present invention
  • FIG 2 is an internal block diagram of the address management unit shown in Figure 1;
  • FIG. 3 is a timing chart showing an example of the write timing of the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 4 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 5 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 6 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 7 is a schematic diagram of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 8 is a schematic diagram of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 9 shows the rewriting system of the field programmable gate array of the present invention.
  • FIG. 4 is a schematic diagram of a method for switching a defective circuit to a repair circuit in the first embodiment of the present invention
  • FIG. 10 is a table showing a sequence of a method of switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 11 is an overall schematic diagram of a second embodiment of the field programmable gate array rewriting system of the present invention.
  • FIG. 12 is a timing chart showing an example of the write timing of the second embodiment of the field programmable gate array rewriting system of the present invention.
  • FIG. 1 is an overall schematic diagram of a first embodiment of a field programmable gate array rewriting system according to the present invention.
  • the field programmable gate array rewriting system of the present embodiment includes an address management unit 100 and a field programmable gate array 101.
  • the field programmable gate array 101 is composed of an address decoder 102, a circuit determining RAM 103, a connection net 104, and circuit generators 108, 109, 110, 1 1 1, 1 1 1, 1 1 2, 1 1 3, 1 1 4, 1 1 5.
  • the number of circuit generators is not limited to the number shown in FIG. 1, but may be another number.
  • the circuit determining RAM 103 stores circuit determining data 105 for generating a circuit. Store.
  • the circuit determination data 105 stored in the circuit determination RAM I 03 is circuit data already generated in each circuit generation unit.
  • the circuit determination RAM 103 has a used area 106 and an unused area 107.
  • an area for storing circuit determination data is specified by an address.
  • connection net 104 is formed by wiring that connects each circuit generation unit shown in FIG.
  • each circuit generating unit shown in FIG. 1 corresponds to the address of the circuit determining RAM 103.
  • a circuit corresponding to the circuit determination data 105 stored in the circuit determination RAM 103 is generated.
  • each circuit generation unit of FPGA 101 includes an S-RAM for generating a logic circuit and flip-flops (FF). Further, each circuit generator of FPGA 101 has an FF for switching the circuit generator to another circuit generator.
  • FF logic circuit and flip-flops
  • circuit determination data 105 stored in the circuit determination RAM 103 is generated in each circuit generation unit, a look-up table indicating an output corresponding to a predetermined input by the S-RAM Then, a circuit corresponding to the circuit determination data is formed by giving a predetermined delay to the FF.
  • the look-up table formed in S—RAM is determined by the circuit determination data stored in the circuit determination RAM103.
  • the circuit generation unit 108 can function as, for example, a switching circuit. Further, the circuit generation unit 109 can function as, for example, a correction circuit.
  • the switching circuit is a circuit for switching a defective circuit to a correction circuit when there is a defective circuit.
  • a repair circuit is a circuit that can be switched in place of a circuit in which a failure has occurred.
  • the address management unit 100 outputs a circuit determination address (FPGAADDRESS) and circuit determination data (FPGADATA).
  • the circuit determination data is information for determining a circuit generated in the circuit generation unit of the FPGA. That is, the circuit determination data is information for determining a logic circuit determined by a combination of the S-RAM lookup table and the FF of the circuit generation unit.
  • This circuit determination data is stored in the circuit determination RAM 103. Then, based on the circuit determination data 105 stored in the circuit determination RAM 103, a circuit corresponding to the circuit determination data is generated in the circuit generation unit.
  • circuit determination address is an address for indicating an area for storing circuit determination data 105 in the circuit determination RAM 103.
  • the circuit determining address output from the address management unit 100 is input to the address decoder 102.
  • the circuit determination data output from the address management unit 100 is input to the circuit determination RAM 103.
  • the address decoder 102 stores the circuit determination data in the address indicated by the circuit determination RAM 103 based on the input circuit determination address.
  • the circuit determination data is the same as the circuit determination address of the circuit determination RAM 103 regardless of whether or not the operation of the FPGA 101 is continuing. Can be stored in the area.
  • the circuit determination RAM 103 is used. Since the circuit determination data is stored in the unused area of the FPGA, the operation of the device using the FPGA is not interrupted.
  • circuit generation unit a circuit corresponding to the circuit determination data stored in the circuit determination RAM 103 is generated by the circuit generation unit.
  • FIG. 2 is an internal block diagram of the address management unit shown in FIG.
  • the address management unit writes the FPGA data interface 201, the new data storage unit 202, the previously written address storage unit 203, and It includes a write order control unit 204, a write address addition unit 205, and an FPGA write interface 206.
  • the circuit determination data is input to the FPGA data interface 201 in accordance with the order of rewriting of the FPGA circuit which the user intends to perform.
  • the FPGA data interface 201 receives circuit determination data to be output to the FPGA, and outputs the data to the new data storage unit 202.
  • the new data storage unit 202 stores the circuit determination data output from the FPGA data interface 201.
  • the write order control unit 204 notifies the write address addition unit 205 of the timing to output the circuit determination data to which the circuit determination address has been added.
  • the write order control unit 204 determines the circuit to which the next circuit determination address is added after the circuit determination data to which the circuit determination address is added is written to the FPGA to generate the circuit. Notifying the write address addition unit 205 of the timing of writing the data for FPGA to the FPGA to generate the circuit.
  • the write order control unit 204 counts the number of write clocks, and the circuit determination address with the circuit determination address added to the write address addition unit 205. Notify when to output data for FPGA to FPGA write interface 206.
  • the write order control unit 204 controls the timing of writing the circuit determination data to which the circuit determination address has been added to the FPGA 101, so that the user This eliminates the need to determine the timing for inputting the determination data to the address management unit 100.
  • the write address adding unit 205 obtains the address of the unused area of the circuit determination RAM from the previous write address storage unit 203. In the write address adding section 205, the address of the unused area of the circuit determination RAM acquired from the previous write address storage section 203 becomes the circuit determination address.
  • the write address adding unit 205 stores the circuit determination data obtained from the new data storage unit 202 and the circuit determination address of the unused area obtained from the previous write address storage unit 203.
  • the address of the circuit determining RAM used this time is stored as the address of the use area of the circuit determining RAM in the FPGA.
  • the circuit determining address and the circuit determining data are output to the circuit determining RAM in the FPGA in the order output from the write address adding section 205.
  • FIG. 3 is a timing chart showing an example of the write timing of the first embodiment of the field programmable gate array rewriting system of the present invention.
  • an address for circuit determination and data for circuit determination are multiplexed and output serially.
  • circuit decision data such as additional circuits and correction circuits are written to the circuit decision RAM so that the address decoder can distinguish between the circuit decision address and the circuit decision data.
  • Data to the FPGA is there.
  • the FPGA write interface 206 outputs the circuit determination address and the circuit determination data 303 to the FPGA 101 in serial. I do.
  • the FPGA write interface 206 writes all of the circuit determination address and the circuit determination data 303 to the FPGA 101 in synchronization with the write clock 302.
  • the FPGA write interface 206 inputs the write start enable 301 to the FPGA 101 and then outputs the circuit determination address and the circuit determination data 303 to the FPGA. Do.
  • the FPGA write interface 206 outputs the first bit of the circuit determination address to the FPGA 101 at the rising edge of the clock. .
  • the FPGA write interface 206 determines the first circuit at the next rising edge of the clock. The remaining bits of the address are output to the FPGA 101.
  • the FPGA write interface 206 similarly outputs the circuit determination data of the first circuit determination address at every rising edge of the clock. To the FPGA 101.
  • the FPGA write interface 206 finishes outputting the final circuit determination address and circuit determination data, it stops the write clock 302 and ends the write.
  • the operation of the faulty circuit does not match the operation of the repair circuit due to the fault.
  • FIGS. 4 to 9 are schematic diagrams of a method for switching a defective circuit to a correction circuit in the first embodiment of the field programmable gate array rewriting system of the present invention
  • FIG. 10 shows the field of the present invention.
  • 6 is a table showing an order of a method of switching a defective circuit to a repair circuit in the first embodiment of the programmable gate array rewriting system.
  • the circuit generation XX of the write A d ress means the RAM A d d X X area for circuit determination in FIG. 4 to FIG.
  • circuit-determining RAMAddXX region shown in FIGS. 4 to 9 is a circuit generation unit corresponding to the address XX of the circuit-determining RAM103 shown in FIG.
  • circuit-determining RAMAddXX region and the circuit generation XX of the write Adress shown in FIG. 10 in FIGS. 4 to 9 are also simply referred to as an address XX.
  • connection nets are formed between the RAMAddXX regions for circuit determination.
  • the latch FF 501 is an FF provided in the defective circuit 401 from the beginning for circuit switching, separately from the FF forming the look-up table and the logic circuit by the S-RAM. As shown in FIG. 1O, in the writing order 0, the failure continues before the correction.
  • the inactivated latch FF501 is added to the address 2B.
  • the inactivated latch FF501 is connected to the control gate 403 in a region corresponding to the address 2B of the circuit determination RAM103. .
  • the FPGA modifies the correction circuit 61 and the switching circuit 6 connected to the input of the deactivated latch FF501. 0 2 and a switching point information circuit 603 are generated.
  • the circuit determination data input to the FPGA includes the correction circuit 61, the switching circuit 62 connected to the input of the inactivated latch FF501, and the switching point information circuit 6. 0 3 is generated.
  • the address information is switched to the address 1A, and the point information circuit 603 is generated (write order 2).
  • the area of the address 1A where the switching point information circuit 603 is generated is an area of the unused circuit generation unit.
  • a switching circuit 602 is generated at address 2A (write order 3).
  • the area of address 2A where the switching circuit 602 is generated is an unused area.
  • the address 1A is connected to the address 2A (write order 4).
  • the address 1A and the address 2A are connected, for example, by forming a wiring in an unwired area of the connection net shown in FIG.
  • a correction circuit 601 is generated at the address 2C (write order 5).
  • the area of the address 2C where the correction circuit 600 is generated is an unused area of the circuit generation unit.
  • the address 1B is connected to the address 2C (write order 6).
  • the address 1B and the address 2C are connected to each other by a wiring formed in an unwired area of the connection net shown in FIG. 6, for example.
  • the address 2C and the address 2B are connected (write order 7).
  • the address 2C and the address 2B are connected by, for example, a wiring formed in an unwired area of the connection net shown in FIG.
  • the switching circuit 602 inputs switching point information from the switching point information circuit 603.
  • This switching point information is input by a user who is monitoring the operation of the FPGA.
  • This switching point information indicates, for example, the timing at which the operation of the malfunctioning circuit 401 and the operation of the correction circuit 601 that are periodically operating coincide with each other.
  • the switching point information if the switching circuit 602 counts at a constant period, the value of the defective circuit 401 and the correction circuit 601 is determined by any value of the count. Information indicating whether the operations match can be given.
  • the switching circuit 602 outputs the coincidence signal to the deactivated latch FF501 at the timing indicated by the switching point information.
  • the switching circuit 602 outputs this coincidence signal to the inactivated latch FF501, so that when the operation of the defective circuit 401 coincides with the operation of the correction circuit 601, The operation switches from the defective circuit 401 to the correction circuit 601.
  • address 2A and address 2B are connected (write order 8).
  • the address 2A and the address 2B are connected by forming a wiring in a non-wiring area.
  • control gate 403 is released, and as shown in FIG. 10, at the address 2B, the control gate 403, which is an AND for a selector, is opened. Perform Pu IIUp (write order 9), and then activate the deactivated latch FF501. The Pul I Up of the control gate 403 rewrites the data to the address 2B again.
  • the switching circuit 602 latches the in-line signal so that the operation is switched from the defective circuit 401 to the correction circuit 601.
  • Output to FF501 (Fig.10, Write for circuit correction end). That is, switching is performed at a predetermined switching timing. If these series of operations are not performed by writing the circuit determination data output to the circuit determination RAM in the FPGA in the order of addresses, the operations will not switch properly.
  • an apparatus or method such as a tool for performing a series of operations is required.
  • the address management unit 100 determines a circuit determination address of circuit determination data for generating circuits such as the correction circuit 600 and the switching circuit 600.
  • the address management unit 100 together with the determined circuit determining address, stores circuit determining data for generating circuits such as the correction circuit 61 and the switching circuit 62.
  • the data is output to the RAM 103 for circuit determination in the FPGA as data with addresses in a sequence.
  • the user does not need to manage the address of the unused area in the circuit determination RAM 103.
  • an additional circuit / correction circuit is generated in an unused area of the circuit determination RAM 103, so that the operation of the FPGA is maintained even when a circuit is added or corrected. Can be.
  • the present embodiment is effective when applied to a case where a function is added or a defect is corrected while the operation is continued in an exchange device or the like in which system stoppage is not recognized.
  • the address management unit 1000 and the FPGA 101 can be connected to each other.
  • P The second embodiment of the field programmable gate array rewriting system
  • FIG. 11 is an overall schematic diagram of a second embodiment of the field programmable gate array rewriting system of the present invention.
  • FIG. 12 is a field programmable gate array rewriting system of the present invention.
  • 9 is a timing chart showing an example of a write timing according to the second embodiment.
  • This embodiment is different from the first embodiment of the above-described field programmable gate rewriting system in that a circuit determining address and a circuit determining address output from the address managing unit to the circuit determining RAM are different.
  • the point is that the data interface is a parallel twin.
  • Other structures and operations of the present embodiment are the same as those of the above-described first embodiment, and therefore, the points different from the above-described first embodiment will be mainly described below.
  • the system for rewriting the field programmable gate includes an address management unit 110 and a field programmable gate array 1101.
  • the field programmable gate array 1101 is composed of an address decoder 1102, a circuit determination RAM 1103, a connection net 1104, and a circuit generation section 1108, 110. 9, 1 1 1 0, 1 1 1 1 1, 1 1 1 2, 1 1 1 3, 1 1 1 4, 1 1 1 5.
  • the number of circuit generators is not limited to the number shown in FIG. 11, but may be another number.
  • the circuit determination RAM 110 stores the circuit determination data 111.
  • circuit determination RAM 1103 has a used area 1106 and an unused area 1107.
  • the area for storing the circuit determination data is specified by the address.
  • connection net 1104 is formed by wiring that connects the circuit generation units to each other.
  • connection nets 111, 104 have circuit generators 111, 111, 111, 112, 113, 111, 114, and 111, as use areas. Is formed.
  • the address management unit 11010 outputs a circuit determination address (FPGA ADDRESS) and circuit determination data (FPGADATA) in parallel twin.
  • FPGA ADDRESS circuit determination address
  • FPGADATA circuit determination data
  • the address for circuit determination output from the address management unit 110 is input to the address decoder 110.
  • the circuit determination data output from the address management unit 110 is used for circuit determination. Input to RA I 103.
  • the address decoder 111 stores the circuit determination data in the circuit determination RAM 110 based on the input circuit determination address.
  • the address decoder 1102 writes an additional circuit, a correction circuit, and the like to the circuit-determining RAM 1103. Must be given to FPGA 111 so that they can be distinguished and written.
  • the present embodiment is an embodiment in which a circuit determining address and circuit determining data are output to the field programmable gate array 111 in parallel twin.
  • the parallel twin means that two signal lines, a signal line for a circuit determination address and a signal line for a circuit determination data, are provided between the address management unit 1101 and the FPGA 1101. Means to exist.
  • one or more of the signal line of the circuit determining address and the signal line of the circuit determining data may be any number of two or more. You may do it. That is, in the present invention, the circuit determining address and the circuit determining data may be output to the field programmable gate array 111 in parallel.
  • the output of the circuit determination address and the circuit determination data to the field programmable gate array in parallel twin is performed by the FPGA write interface 206 shown in FIG.
  • the FPGA write interface 206 is used to write the circuit determination address 122 3 and the circuit determination data 122 4 to the FPGA 110 1. All are performed in synchronization with the write clock 122.
  • the FPGA write interface 206 inputs the write start enable signal 1201 to the FPGA 110, and then sets the circuit determination address to the FPGA 110. 1 '2 0 3 and data for circuit determination 1 204 are output.
  • the FPGA write interface 206 receives the first write clock 122 At the rising edge, the address for circuit determination 1 203 Outputs “!” Bit with circuit decision data 1 204 to FPGA 110 1.
  • FPGA write intuff:!: 206 is the first write clock 1
  • the operation of rewriting the defective circuit of the FPGA to the correction circuit is the same as the operation described with reference to FIGS. 4 to 10 in the first embodiment.
  • the interface between the circuit determination address and the circuit determination data output from the address management unit 110 to the circuit determination RAM 1103 is parallel, it is serial. Compared to the case where parallel is used, rewrite completion time is shorter in the case of parallel because there are more bits that can be input at one rising edge of the clock than in the case of serial. Industrial applicability
  • the present invention is effective when rewriting a circuit such as adding a function or correcting a defect to an FPGA while continuing operation in a switching device or the like in which a system stop is not recognized.

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  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)

Abstract

Selon l'invention, des informations relatives à l'adresse non utilisée dans une mémoire vive du circuit de décision d'un réseau prédiffusé programmable sont stockées dans une section précédente de stockage d'adresse d'écriture et des données du circuit de décision sont stockées dans une nouvelle section de stockage des données. En fonction de l'adresse non utilisée dans la mémoire vive du circuit de décision, une section d'addition d'adresse d'écriture ajoute une adresse du circuit de décision aux données du circuit de décision stockées dans la nouvelle section de stockage des données et la sort. Un décodeur d'adresse amène la mémoire vive du circuit de décision à stocker les données du circuit de décision en fonction de l'adresse du circuit de décision.
PCT/JP2003/012725 2003-10-03 2003-10-03 Systeme de reecriture sur reseau prediffuse programmable WO2005034353A1 (fr)

Priority Applications (2)

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JP2005509315A JP4156626B2 (ja) 2003-10-03 2003-10-03 フィールドプログラマブルゲートアレイの書き換えシステム
PCT/JP2003/012725 WO2005034353A1 (fr) 2003-10-03 2003-10-03 Systeme de reecriture sur reseau prediffuse programmable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/012725 WO2005034353A1 (fr) 2003-10-03 2003-10-03 Systeme de reecriture sur reseau prediffuse programmable

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WO2005034353A1 true WO2005034353A1 (fr) 2005-04-14

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6436120A (en) * 1987-07-30 1989-02-07 Nec Corp Redundant constitution gate array
JPH10233677A (ja) * 1996-12-20 1998-09-02 Hitachi Ltd 半導体集積回路
JPH11167556A (ja) * 1997-12-03 1999-06-22 Nippon Telegr & Teleph Corp <Ntt> 論理回路の動的な構成方法
JP2001320271A (ja) * 2000-05-02 2001-11-16 Fuji Xerox Co Ltd プログラマブル論理回路への回路の再構成方法および情報処理システム
JP2002009613A (ja) * 2000-06-27 2002-01-11 Fuji Xerox Co Ltd 回路機能の再構成方法、及びプログラマブル論理回路装置
JP2002314402A (ja) * 2001-04-16 2002-10-25 Mitsubishi Electric Corp プログラマブル論理回路装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6436120A (en) * 1987-07-30 1989-02-07 Nec Corp Redundant constitution gate array
JPH10233677A (ja) * 1996-12-20 1998-09-02 Hitachi Ltd 半導体集積回路
JPH11167556A (ja) * 1997-12-03 1999-06-22 Nippon Telegr & Teleph Corp <Ntt> 論理回路の動的な構成方法
JP2001320271A (ja) * 2000-05-02 2001-11-16 Fuji Xerox Co Ltd プログラマブル論理回路への回路の再構成方法および情報処理システム
JP2002009613A (ja) * 2000-06-27 2002-01-11 Fuji Xerox Co Ltd 回路機能の再構成方法、及びプログラマブル論理回路装置
JP2002314402A (ja) * 2001-04-16 2002-10-25 Mitsubishi Electric Corp プログラマブル論理回路装置

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JPWO2005034353A1 (ja) 2006-12-14
JP4156626B2 (ja) 2008-09-24

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