JPS6436120A - Redundant constitution gate array - Google Patents

Redundant constitution gate array

Info

Publication number
JPS6436120A
JPS6436120A JP19117987A JP19117987A JPS6436120A JP S6436120 A JPS6436120 A JP S6436120A JP 19117987 A JP19117987 A JP 19117987A JP 19117987 A JP19117987 A JP 19117987A JP S6436120 A JPS6436120 A JP S6436120A
Authority
JP
Japan
Prior art keywords
section
circuit
cell
fpla
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19117987A
Other languages
Japanese (ja)
Inventor
Yuichi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19117987A priority Critical patent/JPS6436120A/en
Publication of JPS6436120A publication Critical patent/JPS6436120A/en
Pending legal-status Critical Current

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the yield by providing a redundant array section capable of programming a defective cell to be replaced by means of an OR or an AND circuit if an integrated circuit is defective. CONSTITUTION:An FPLA (field programmable logic array) section 300 is provided as a redundant array section applying programming control so as to allow a logic circuit section 200 to execute a prescribed logic operation. The FPLA section 300 is programmed so that an OR circuit is formed if input information to a cell is '0' degeneration defect information and an AND circuit is formed if it is '1' degeneration information in a designated address according to the input information of the cell in the logic circuit section 200 connected thereto and the inputted address information and the circuit is operated normally. Thus, even if the cell is defective in the logic circuit section 200, the FPLA section 300 can relieve it to improve the yield.
JP19117987A 1987-07-30 1987-07-30 Redundant constitution gate array Pending JPS6436120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19117987A JPS6436120A (en) 1987-07-30 1987-07-30 Redundant constitution gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19117987A JPS6436120A (en) 1987-07-30 1987-07-30 Redundant constitution gate array

Publications (1)

Publication Number Publication Date
JPS6436120A true JPS6436120A (en) 1989-02-07

Family

ID=16270216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19117987A Pending JPS6436120A (en) 1987-07-30 1987-07-30 Redundant constitution gate array

Country Status (1)

Country Link
JP (1) JPS6436120A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233449A (en) * 1990-11-07 1993-08-03 Sharp Kabushiki Kaisha Liquid-crystal color display with comb-shaped pixel electrodes partially overlapping at the electrode ends
WO2005034353A1 (en) * 2003-10-03 2005-04-14 Fujitsu Limited Field programmable gate array rewrite system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233449A (en) * 1990-11-07 1993-08-03 Sharp Kabushiki Kaisha Liquid-crystal color display with comb-shaped pixel electrodes partially overlapping at the electrode ends
WO2005034353A1 (en) * 2003-10-03 2005-04-14 Fujitsu Limited Field programmable gate array rewrite system

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