JPH10163820A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which does not need to change a circuit and uses a flip-flop that reduces power consumption. SOLUTION: A comparator circuit 16 and a control circuit 18 are provided inside the layout of a flip-flop 10, the circuit 16 compares data that is currently held with data that is newly inputted, and the circuit 18 stops a clock buffer when the comparison results of the comparison circuit match and the circuit 18 operates the clock buffer when the comparison results of the comparator circuit do not match.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a flip-flop capable of reducing power consumption.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a conventional flip-flop. The illustrated flip-flop 56
Shows an internal configuration of a D-type flip-flop, which buffers a clock signal and outputs an internal clock signal C.
A clock buffer 58 for generating K, CK_, and
The holding circuit 14 holds input data in accordance with the internal clock signals CK and CK_ generated by the clock buffer 58 and outputs the input data as output data.

In the illustrated flip-flop 56,
The clock buffer 58 has two inverters 22 and 24 connected in series. The clock signal is input to the inverter 22 via the clock input terminal 26 of the flip-flop 56, and the output signals of the inverters 22 and 24 are the internal clock signals CK_ and CK, respectively. The internal clock signals CK and CK_ generated by the clock buffer 58 are supplied to the holding circuit 14.

[0004] The holding circuit 14 includes a clocked inverter 3.
6, inverters 38 and 40 and transfer gate 4
2 and a slave latch 34 having transfer gates 44 and 50 and inverters 46, 48 and 52. As described above, the internal clock signals CK, CK_ generated by the clock buffer 58 are input to the control terminal of the clocked inverter 36 and the control terminals of the transfer gates 42, 44, 50, respectively.

In the master latch 32, input data is input to a clocked inverter 36 via a data input terminal 28 of a flip-flop 56, and an output signal of the clocked inverter 36 is input to an inverter 38. The output signal of the inverter 38 is
The output signal of the inverter 40 is input to the transfer gate 42, and the output signal of the transfer gate 42 is input to the inverter 38.

In slave latch 34, the output signal of transfer gate 44 is input to inverter 46,
The output signal of the inverter 46 is input to the inverter 48 and the transfer gate 50. Inverter 4
The output signal 8 is output as output data via the data output terminal 30 of the flip-flop 56. The output signal of the transfer gate 50 is
2 and the output signal of the inverter 52 is input to the inverter 46.

In the illustrated flip-flop 56,
First, when the clock signal goes low,
When the internal clock signals CK and CK_ go to a low level and a high level, respectively, the clocked inverter 36 and the transfer gate 50 change from the off state to the on state, and the transfer gates 42 and 44 both change from the on state to the off state. Then, the input data is input to the master latch 32.

Next, when the clock signal goes high, that is, when the internal clock signals CK and CK_ go high and low, respectively, the clocked inverter 36 and the transfer gate 50 change from an on state to an off state. , The transfer gates 42 and 44 both change from the off state to the on state,
The input data is held in the master latch 32, is input to the slave latch 34, and is output as output data.

Thus, the flip-flop 5 of the illustrated example is
In 6, the internal clock signals CK and CK_ are generated according to the clock signal, input data is held according to these internal clock signals CK and CK_, and output as output data. However, the flip-flop 56 has a problem that power consumption increases because the two inverters 22 and 24 constituting the clock buffer 58 always operate according to the operating frequency of the clock signal.

One solution for preventing such an increase in the power consumption of the flip-flop is to use a gated clock, for example. As shown in FIG. 3, the gated clock is provided with, for example, an AND gate 60 and an EXOR gate 61 for controlling a clock signal, so that the clock signal supplied to the flip-flop 62 is stopped based on a certain condition. This prevents the clock buffer inside the flip-flop 62 from increasing power consumption.

However, in the method for reducing power consumption using a gated clock, in a logic circuit design stage, for example, a clock signal such as an AND gate 60 shown in FIG. Since it is necessary to add a logic gate, the number of gates of the entire semiconductor device increases, and it is necessary to make a circuit change such as a change in wiring connection.
There was a problem that it was troublesome.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device using a flip-flop which can reduce power consumption without having to change a circuit in view of the problems based on the prior art. To provide.

[0013]

In order to achieve the above object, the present invention provides a clock buffer for buffering a clock signal and generating an internal clock signal, and responding to the internal clock signal generated by the clock buffer. A holding circuit for holding input data and outputting the output data as output data, wherein the flip-flop further comprises a comparator for comparing currently held data with the input data. And a control circuit that stops the clock buffer when the comparison result of the comparison circuit matches, and operates the clock buffer when the comparison result of the comparison circuit does not match. A semiconductor device is provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings. FIG. 1 is a configuration circuit diagram of one embodiment of a flip-flop used in a semiconductor device of the present invention. The illustrated flip-flop 10 shows the internal configuration of a D-type flip-flop.
2, a holding circuit 14, a comparing circuit 16, and a control circuit 18.

The clock buffer 12 buffers the clock signal and generates the internal clock signals CK and CK_. In the illustrated example, the clock buffer 12 is a NAND gate 20.
And an inverter 24. The clock signal is supplied to the clock input terminal 26 of the flip-flop 10
The signal is input to one input terminal of the AND gate 20, and the NAN
The output signal of the D gate 20 is used as an internal clock signal CK_ and input to the inverter 24, and the output signal of the inverter 24 is used as the internal clock signal CK.

The holding circuit 14 holds the input data input through the data input terminal 28 of the flip-flop 10 in accordance with the internal clock signals CK, CK_ generated by the clock buffer 12, Is output as output data via the data output terminal 30 of the first embodiment. The holding circuit 14 in the example shown in FIG.
Has the same configuration as that of the conventional flip-flop 56 shown in FIG. 1, and the same reference numerals are given to the same components here, and description thereof will be omitted.

The comparison circuit 16 compares the data currently held by the flip-flop 10 with the input data and outputs the output result. In the illustrated example, the data currently held is That is, the holding circuit 14
And an EXOR gate 54 for detecting a mismatch between the output signal of the inverter 52 constituting the slave latch 34 and the input data. The output signal of the EXOR gate 54 is output from the NAND gate 2 constituting the clock buffer 12.
0 is input to the other input terminal.

When the comparison result of the comparison circuit 16 is coincident, that is, in the case of the example shown in FIG.
When the output signal of the R gate 54 is at a low level, the clock buffer 12 is stopped, and when the comparison result of the comparison circuit 16 does not match, that is, when the output signal of the EXOR gate 54 is at a high level, the clock buffer 12 is stopped. This is controlled so as to operate, and in the illustrated example, the NAND gate 20 of the clock buffer 12 is shared.

In the flip-flop 10 of the illustrated example, the data currently held by the flip-flop 10, that is, the output signal of the inverter 52 constituting the slave latch 34 of the holding circuit 14, is output by the comparison circuit 16.
The input data input through the data input terminal 28 of the flip-flop 10 is compared. As a result, the EXOR gate 54 constituting the comparison circuit 16 outputs a low level when both match, and outputs a high level when they do not match.

Here, when a low level is output from the EXOR gate 54, that is, when the flip-flop 10
When the data currently held and the input data match, the clock signal
The internal clock C gated by the AND gate 20
K and CK_ are stopped regardless of the clock signal.
That is, in the illustrated flip-flop 10,
The internal clocks CK and CK_ are set to a low level and a high level, respectively.

Conversely, when a high level is output from the EXOR gate 54, that is, when the data currently held by the flip-flop 10 does not match the input data, the control circuit 18 and the clock buffer 12 are turned off. The constituent NAND gate 20 is brought into the operating state, and the clock signal is buffered by the NAND gate 20 and the inverter 24 constituting the clock buffer 12, and the internal clocks CK and CK_ are generated accordingly.

The operation after the generation of the internal clocks CK and CK_ is the same as that of the conventional flip-flop 56 shown in FIG.

As described above, the flip-flop 1 of the illustrated example
In the case of 0, the clock buffer 12 is operated by a logical change of data lower than the operating frequency of the clock, so that power consumption can be reduced. Also, since the internal configuration of the flip-flop 10 has been changed,
The input terminal and the output terminal are compatible with the conventional flip-flop 56, and only the conventional flip-flop 56 needs to be replaced with the flip-flop 10 according to the present invention.
For example, there is an advantage that there is no need to change a circuit as in the case of using a gated clock.

Although the semiconductor device of the present invention has been described in detail above, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course. For example, in the above embodiment, a D-type flip-flop is described as an example of a flip-flop used in the semiconductor device of the present invention. However, it is needless to say that the present invention can be applied to any conventionally known flip-flop. That is.

[0025]

As described above in detail, the semiconductor device of the present invention compares the currently held data with the input data, and only when the input data is different from the currently held data, the clock is output. It has a flip-flop configured to operate a buffer and hold input data. Therefore, in the semiconductor device of the present invention, since the flip-flop operates at the timing of the logical change of the input data, which is lower than the operating frequency of the clock signal, the power consumption can be significantly reduced as compared with the conventional flip-flop. Can be. In addition, since the internal structure of the flip-flop itself has been changed, it is compatible with the conventional flip-flop in terms of the input terminal and the output terminal, and there is no hassle of changing the circuit such as adding a logic gate or changing the wiring connection. . That is, according to the semiconductor device of the present invention, the power consumption of the entire semiconductor device can be reduced by simply using the flip-flop according to the present invention instead of using the conventional flip-flop. There are advantages.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a flip-flop used in a semiconductor device of the present invention.

FIG. 2 is a configuration circuit diagram of an example of a conventional flip-flop.

FIG. 3 is a configuration circuit diagram of an example of a conventional flip-flop to which a gated clock is applied.

[Explanation of symbols]

10, 56, 62 flip-flop 12, 58 clock buffer 14 holding circuit 16 comparison circuit 18 control circuit 20 NAND gate 22, 24, 38, 40, 46, 48, 52 inverter 26 clock input terminal 28 data input terminal 30 data output terminal 32 Master Latch 34 Slave Latch 36 Clocked Inverter 42,44,50 Transfer Gate 54,61 EXOR Gate 60 AND Gate

Claims (1)

[Claims] 1. A clock buffer for buffering a clock signal and generating an internal clock signal, and a holding circuit for holding input data according to the internal clock signal generated by the clock buffer and outputting the input data as output data. A semiconductor device using the flip-flop, wherein the flip-flop further comprises: a comparison circuit for comparing currently held data with the input data; and And a control circuit for stopping the clock buffer and operating the clock buffer when the comparison result of the comparison circuit does not match.