JPS6075121A - Flip-flop - Google Patents

Abstract

PURPOSE:To generate a Q output and a Q' output in a nearly identical timing by connecting a transfer gate and an inverter in cascade and extracting a complementary output in a D flip-flop. CONSTITUTION:When a data input D is at a high level with a clock phi of L level, a transfer gate (TG)21 is turned on and TG23, 26 are turned off. Thus, although an output of the inverter (IV)22 goes to a low level and an output of an IV25 goes to a high level, the Q and Q' outputs remain in the preceding state. When the clock phi goes to a high level, the TG21 is turned off, the TG23, 26 are turned on and the outputs Q, Q' go respectively to high and low levels. With the data input at a low level, the outputs Q, Q' go respectively to a low and a high level similarly. The state of the data input D is transferred to the outputs Q, Q' at one period of the clock and the propagation delay to the outputs Q, Q' is made identical together in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D-type flip-flop.

An example of a circuit configuration of a D type flip-flop with a conventional complementary MO8 configuration is shown in FIGS. 1 and 2. Figure 1 shows a dynamic type D type flip-flop υ,
In particular, 1 and 3 are p-channel and n-channel complementary M
O8) Transfer gate composed of transistors, 2 and 4.5 are similar complementary MO8) Inverters using transistors, φ and f are clock inputs, D is data input,
Q, Q are flip-flop outputs. In this flip-flop, if, for example, the data output is at a high level, the clock φ is at a low level ($ is at a high level), the transformer 7 - gate 1 is not on, and the output of the inverter 2 is becomes a low level state.Next, when the clock φ becomes a high level state, the transfer gate 3 is turned on, the output Q of the inverter 4 becomes a high level state, and then the output Q of the inverter 5 becomes a low level state. In other words, in a dynamic flip-flop having such a configuration, the Q output lags the Q output by one inverter stage and becomes an inverted state of the Q output.

Figure 2 shows a conventional static type D-type flip-flop, in which reference numerals 11, 13, 15 and 17 refer to transfer gates composed of complementary MOS transistors;
2.14+1t3.18 is an inverter configured with complementary MO8) transistors.

For example, if the data output is at a high level, the transfer gate 11 is on when the clock φ is at a low level, and the output of the inverter 12 is at a low level. Next, when the clock φ reaches the g level state, the transfer gate 15 is turned on.
The output Q of the inverter 16 becomes high level. Next, the output Q of the inverter 18 becomes a low level state. That is, even in a static type flip-flop having such a configuration, the Q output lags behind the Q output by one inverter stage, resulting in an inverted state of the Q output.

As explained above, the Q output is the same as the Q output.
Since it has a delay of one stage, there is a drawback that the propagation delay time from the clock to the output Q, Q is unbalanced, and flip
The operating speed of a flop was determined by the output with a large propagation delay time.

In order to solve these drawbacks, the present invention uses a transfer game 1 using complementary MOS transistors r and an inverter so that when the clock φ becomes a high level state, the mirror and Q outputs are inverted almost simultaneously. The purpose is to appropriately combine and arrange them.

The present invention will be explained in detail below using the drawings.

FIG. 3 shows a female, mechanical type D type flip clock according to an embodiment of the present invention.
Reference numerals 6 and 27 designate transfer gates each having a complementary MOS transistor configuration, and 22°, 24, 25, and 27 designating inverters each having a complementary BIOS transistor configuration. Here, the input terminal of the transfer gate 21 is connected to the data input terminal, the output terminal of the transfer gate 21 is connected to the input terminal of the inverter 22, and the output terminal of the -17 switch 22 is connected to the input terminal of the transfer gate 23 and the input terminal of the inverter 25. connected to. The output terminal of the transfer gate 23 is connected to the input terminal of an inverter 24, and the output terminal of the inverter 24 is used as a Q output terminal. The output terminal of the inverter 25 is connected to the input terminal of the transfer gate 26.
The output terminal of is connected to the input terminal of the inverter 27, and the output terminal of this inverter 27 is designated as the q output terminal. In addition, the p-channel that constitutes each transfer gate,
Complementary flip-lock inputs φ and a are connected to the gate input terminals of the n-channel complementary MO8) transistors.

Next, the operation of this circuit will be explained. For example, when the data input is in a high level state, the clock φ is in a low level state (φ
is at a high level), the transfer gate 21 is on, and the transfer gates 23 and 26 are off. Therefore, the output of inverter 22 is at a low level, and the output of inverter 25 is at a high level, but the Q output and the Q output remain in their previous states. Next, when the clock φ becomes a high level state, the transfer gate 21 is turned off, and the transfer gate 23.26
is not on, the output Q of the inverter 24 is at a high level, and the output ζ of the inverter 270 is at a low level.

Similarly, when the data input D is at a low level, the output Q becomes a low level state and the output Q becomes a high level state in one cycle of the next clock φ. In this way, the state of data input D is transmitted to output Q and output Q in one clock cycle. As explained above, the propagation delay from when the clock φ changes from a low level state to a high level state until a new state is output to the Q and Q output terminals is one stage of transfer gates (23, 26). is equal to the delay of one inverter stage (24, 27). That is, transfer gate 23
and 26 element circuit parameters and inverters 24 and 2
If the element circuit parameters of 7 are made equal, the outputs Q and Q can be propagated with almost equal timing delays.

FIG. 4 shows another embodiment of the present invention.
Indicates type flip 70 cups, 31.33,
35, 37, 39.41 are transfer gates each having a complementary MOS transistor configuration, 32,
34, 36.38, 40.42 are complementary MO8 respectively
) This is an inverter with a transistor configuration. Here, the input terminal of the transfer gate 31 is a data input terminal, the output terminal of the transfer gate 31 is an input terminal of an inverter 32, and the output terminal of the inverter 32 is a transfer v-) 350 input terminal and an inverter 340 input terminal. connected to. The output terminal of the inverter 34 is connected to the input terminals of the transfer gates 33 and 39, and the transformer 7
The output terminal of the argate 33 is connected to the input terminal of the inverter 32. , the output terminal of the transfer gate 35 is connected to the input terminal of the inverter 36, the output terminal of the inverter 36 is connected to the Q output terminal, and the output terminal of the inverter 38 is connected to the input terminal of the inverter 38.
The output terminal of the inverter 38 is the transfer gate 37
The output terminal of the transfer gate 37 is connected to the input terminal of the inverter 36 . The output terminal of the transfer gate 39 is connected to the input terminal of the inverter 40, the output terminal of the inverter 40 is connected to the Q output terminal, the output terminal of the inverter 42 is connected to the input terminal of the transfer gate 41, The output terminal of is connected to the inverter 400 input terminal. Furthermore, complementary input terminals φ and Φ are connected to the gate input terminals of the p-channel and n-channel complementary MOS transistors constituting each transfer gate. The difference between this circuit and the circuit shown in Figure 3 is that this circuit is a static type flip-flop, so transfer gates 33, 37, 41 and inverters 38, 42 are added, so the main operation is as shown in Figure 3. It is similar to the circuit of In other words, the propagation delay from when the clock φ changes from a low level state to a high level state until a new state is output from the Q and Q output terminals is one stage of transfer gates (35, 39) and one stage of inverter. (
equivalent to a delay of 36,40) minutes. Therefore, if the element circuit parameters of transfer gates 35 and 39 and the element circuit parameters of inverters 36 and 40 are made equal, outputs Q and Q can be propagated with approximately equal timing delays.

As explained above, according to the D-type flip-flop of the present invention, the extra circuit that inverts the Q output to make the Q output is removed, and this allows the propagation delay time from the clock to the output to be reduced, and the flip-flop・It is possible to increase the operating speed of the flow 2 block, and to generate Q and Q outputs at approximately the same timing.

In addition, although the fully dynamic type D-type flip-flop and the fully static type D-type flip clock were explained in the embodiment, this is merely an example, and the present invention is not limited to the embodiment described herein. Of course, it is not limited.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a dynamic D-type flip-flop with a conventional complementary MO8) transistor configuration, Figure 2 is a circuit diagram of a static D-type flip-flop with a conventional complementary MO8) transistor configuration, and Figure 3 is a circuit diagram of a static D-type flip-flop with a conventional complementary MO8) transistor configuration.
The figure is a circuit diagram showing an embodiment of a dynamic type D-type flip-flop with a complementary MOS transistor configuration according to the present invention, and FIG. 4 shows an embodiment of a static-type Kuipflinop flop with a complementary MOS transistor configuration according to the present invention. It is a circuit diagram. 1, 3.11.13.15.17.21.23.26.
31.33°35, 37.39.41...Transfer gate. 2+ 4+ 5+ 12+ 14+ 16+ 18+
22+ 24+ 25+ 27°32, 34.36.3
8.40.42...In'Bark. D: --- Data input, Q: Flip-flop output, Q: Flip-flop output (
(inverted output of Q), φ......clock input, Tom...
...Clock input (inverted input of clock φ).

Claims (1)

[Claims] a complementary MO8) transistor circuit that stores binary states;
8) a transfer gate for controlling the binary state of the gingister circuit; and a transfer gate and an inverter, respectively, for receiving complementary outputs from the complementary transistor circuit through first and second cascade connections, respectively. A flip-flop that is characterized by the fact that it comes out.