JPS60148222A - Cmos clock signal generating circuit - Google Patents

Abstract

PURPOSE:To operate stably a CMOS single phase clock sequencing cicuit by applying a clock signal to a CMOS transfer gate via an inverter, an NAND gate and an NOR gate. CONSTITUTION:A clock signal 3C is inputted to the inverter IV35, the NAND gate 31, and the NOR gate 33, an output of the IV35 is inputted to the NAND gate 32 and the NOR gate 34 and the output of the gates 31, 32 is used respectively as the input of the gates 32, 31. Moreover, the output of the gates 33, 34 is used respectively as the input of the gates 34, 33. A data input signal 3I is inputted to a CMOS transfer gate TRF38 of the CMOS single phase clock sequencing circuit, the output of the gates 34, 32 is applied respectively to an N- channel and P-channel gate of the TRF38 and the output of the TRF38 is inputted to the CMOSTRF39 via the IV36. The output of the gates 33, 32 is applied respectively to the N-channel and P-channel gate of the TRF39. The output of the TRF39 is outputted via the IV37. The signal 3I is operated stably not through the TRF39 at the trailing of the signal 3C.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMOS clock signal generation circuit that supplies a single-phase clock sequential circuit having a cMOS (complementary metal oxide semiconductor) transfer gate. This invention relates to a CMOS clock signal generation circuit that prevents an input signal to a previous stage of a sequential circuit from being transmitted to the next stage of a sequential circuit at a change point of a cyclic signal by eliminating signal overlap i.

[Prior art]

Conventionally, in a single-phase clock sequential circuit having a 0MO8) transfer gate, a clock input and a signal obtained by inverting this clock input have been used as a clock transfer signal of the transfer gate. When positive and negative signals are used in this way, the p-type and n-type transistors may become conductive at the same time at the signal change point, so the data input signal to the previous sequential circuit is transmitted to the next sequential circuit. It had the disadvantage that it sometimes

Hereinafter, for convenience of explanation, a sequential circuit having a CMOS transfer gate will be explained as a shift register.

In Fig. 1 showing a conventional example, one data input signal is set to 0.
MO8) As input to transfer gate 14, this CMO
The output of the S transfer gate 14 is input to the inverter 12, the output of the inverter 12 is input to the transfer gate 15, and the output of the inverter 12 is input to the transfer gate 15.
The output of 5 is input to the inverter 130, and the inverter 13
Let the output of this circuit be the output of this circuit. The clock signal IC is input to the gate of the n-type transistor of the inverter 11.0MO8) transfer gate 14 and the gate of the p-type transistor of the transfer gate 15, and the output signal of the inverter 11 is input to the gate of the n-type transistor of the transfer gate 14. and the gate of the n-type transistor of the CMOS transfer gate 15.

With such a circuit #4 configuration, the clock signal IC and the output of the inverter 11 become the waves shown in FIG. In FIG. 2, 21 is the conduction region of the ram transistor (pm), and 22 is n
In the cross region of the fi transistor, there is a section in which the CMOS transfer gates 14 and 15 are conductive at the same time. As a result, the input signal II passes through the transfer gate 14 to the inverter 1 at the falling edge of the clock 1d IC.
2, and 0MO8) transfer gate 15 is inverted (by transfer gate 15) and becomes the output of this shift register, which may cause this circuit to malfunction without operating as a shift register.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a CMOS clock signal generation circuit in which a sequential circuit operates stably.

[Structure of the invention]

The CMOS clock signal generation circuit of the present invention generates a clock signal through an inverter, a first NAND gate, and a first NAND gate.
input to the OR gate and turn the output of the inverter on to the second ON
The output of the first NAND gate or its delayed output is input to the second NAND gate, and the second NOR gate is input to the second NAND gate.
The output of the AND gate or its delayed output is input to the first NAND gate, the output of the first NOR gate or its delayed output is input to the second NOR gate, and the output of the second ONOR gate or The delayed output is connected as one input of the first ONOR gate, and is applied to the gate signal of the p-type transistor of the transfer gate of the single-phase clock sequential circuit having the first and second CMOS transfer gates. second N
The present invention is characterized in that the output of the AND gate is supplied to the gate signals of the n-type transistors of the first and second 0MO8) transfer gates, and the outputs of the first and second NOR gates are supplied.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows one example of the present invention.

Clock signal 3C is inverter 35, NAND game)
31. input to NOR gate 33 and output of inverter 35 t-NAND gate 32 . N01t is input to gate 34, the output of NAND gate 31 is input to NAND gate 32, and the output of NAND gate 32 is input to NAND gate 3.
1, the output of the NOR gate 33 is set as the input of the NOR gate 340, and the output of the NOR gate 34 is set as the input of the NOR gate 330. Data input signal 3I 0MO8)
Connect Lance 7 Agate 38 manually and apply NOR to the gate of the n-type transistor of this 0MO8 transfer gate.

The output of the gate 34 is input, the output of the NAND gate 31 is input to the gate of the p-type transistor, the output of this transfer gate 38 is input to the inverter 36, and the output of the inverter is input to the 0MO8) Lance 7 Agut 39 The output of the NOR gate 33 is input to the gate of the n-type transistor of this transfer gate, the output of the NAND gate 32 is input to the gate of the p-type transistor,
The output of this transfer gate is used as an input to an inverter 27, and the output of this inverter is used as an output of this circuit.

In this circuit configuration, as shown in the timing diagram shown in FIG. They cannot be at a high level at the same time. Therefore, the data input signal 3■ is the clock signal 3
At the falling edge of KCMO8), the transfer gate 38 is passed through, and inverted by the inverter 36, passed through the CMOS transfer gate 39, and inverted by the inverter 37, and is not outputted as an output of this circuit.

In this way, in the CMO8 single-phase clock sequential circuit, the input No. 100 does not pass through from the previous stage to the next stage at the change point of the clock signal, and the CMO8 single-phase clock sequential circuit can operate stably. Further, another embodiment of the present invention is shown in FIG. In FIG. 5, an inverter 513° NAN is applied to the clock signal 50.
D gate 501. Input to NOR gate 507, output of inverter 513 1 Input to NAND gate 504, NOR gate 510, output of NAND gate 501? The input signal to the inverter 502, the output sound of the inverter 502 is input to the inverter 503, and the output of the inverter 503 is NA
The output of the NAND gate 504 is input to the inverter 505. The output of the inverter 505 is input to the inverter 506. The output of the inverter 506 is input to the NAND gate 501.
7 is input to the inverter 508, and the inverter 50
8 is input to the inverter 509, and the inverter 50
9 is input to the NOR gate 510, the output of the NOR gate 510 is input to the inverter 511, the output of the inverter 511 is input to the inverter 512, the output of the inverter 512 is input to the NOR gate 507, and the data input signal 5I is input to the NOR gate 507. 0MO8) Input the output of the inverter 512 to the gate of the n-type transistor of this transfer gate, input the output of the inverter 503 to the gate of the p-type transistor, and input the output of this transfer gate. inverter 515
The output of this inverter is input to the fcMOS transfer gate 516, the output of the inverter 509 is input to the gate of the n-type transistor of this CMOS transfer gate, and the inverter 4 is input to the gate of the p-type transistor.
The output of the inverter 506 is inputted to the output sound inverter 517 of the transfer gate 516, and the output of this inverter is used as the output of this circuit. Inverters 502, 503, 505, 506, 508. 150
9.511 and 512 act as delay elements.

In this circuit, the outputs of inverters 503 and 506 do not go to low level at the same time, and the outputs of inverters 509.
All 12 outputs are never at high level at the same time. Therefore, when the clock signal 5C falls, the data input signal 5N passes through the 0MO8 transfer gate 514, is inverted by the inverter 515, passes through the 0MO8 transfer gate 516, is inverted by the inverter 517, and is output as the output of this circuit. There isn't.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to output the CMOS clock 1g generation circuit which enables the CMO 8-phase clock Ilu sequence circuit to operate more stably.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a timing diagram for explaining the first drawing operation, and FIG. Figure 5 is a flowchart showing an embodiment of the present invention, and Figure 4 is a timing chart for explaining the operation of Figure 3. 11.12,13,35,36,37,502,503
,505゜506.508,509,511,512,
515, 517... Inverter, 31, 32,
501, 504...NAND gate, 33.3
4,507.510...NOR gate, 14.
15°38.39,514. ．． 516...0M
O8) Transfer gate O l 7 Figure 22 Figure 3 Figure 4 Figure K'-L34 output ゛萬 5 Figure

Claims (1)

[Claims] A clock signal is input to an inverter, a first NAND gate and a first NOR gate, an output of the inverter is input to a second NAND gate and a second NOR gate, and the output of the first NAND gate or its The delayed output is input to the second NAND gate, the output of the second NAND gate or its delayed output is input to the first NAND gate, and the output of the first NOR gate or its delayed output is input to the first NAND gate. a single-phase clock sequential circuit having first and second CMOS transfer gates, the input being an input to a second NOR gate, the output of the second NOR gate or its delayed output being connected as the input to the first NOR gate; p! of the CMOS transfer gate! 1) The first . Second
The output of the NAND gate of the first and second 0MO8)
A CMOS clock signal generation circuit characterized in that the outputs of the first and second NOR gates are supplied to the gate signals of the n-type transistors of the Rice-Far gate.