JPH06283977A - Dynamic type flip-flop - Google Patents

Abstract

PURPOSE:To provide a dynamic type flip-flop capable of performing the initialization of a state. CONSTITUTION:A clocked CMOS NOR gate 20 at a first stage inputs data DIN and a Set signal as a control signal. and introduces the NOR of them synchronizing with a clock pulse phi inputted separately. A clocked CMOS NOR gate 30 at a second stage inputs the output signal DIN<-> of the clocked CMOS NOR gate 20 at the first stage and a Reset signal as the control signal, and introduces the NOR of them synchronizing with a pulse phi<-> of negative phase for the clock pulse phi inputted separately, and outputs DOUT as an output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit, and more particularly to a dynamic flip-flop capable of initializing a state.

[0002]

2. Description of the Related Art For example, most of the circuits mounted on a digital television LSI or the like are so-called static flip-flops in which some of the signals on the output side are returned to the input side in terms of circuitry. . However, the static flip-flop itself has a large circuit scale, which causes a problem that the LSI chip area becomes large.

Therefore, in order to solve such a problem, in recent years, it has been considered to configure a circuit with a dynamic flip-flop. That is, the dynamic flip-flop is a flip-flop that outputs a part of the signal on the output side as it is without returning to the input side in terms of a circuit, and the circuit scale of itself is smaller than that of the static type. is there.

In order to further reduce the circuit scale and power consumption, the dynamic flip-flop described above is used as a complementary metal-oxide-semiconduct CMOS (CMOS).
or) It is configured with a logic gate.

Conventionally, as a dynamic flip-flop having the above-mentioned CMOS structure, for example,
As described in Kyoritsu Shuppan Co., Ltd., December 1983, "Introduction to VLSI Design," some are composed of two clocked CMOS inverters.

The structure and operation will be described below with reference to FIGS. 15, 16 and 17. FIG. 15 is a circuit diagram showing a conventional dynamic flip-flop, and FIG. 16 is FIG.
FIG. 17 is a circuit diagram showing a concrete circuit configuration of FIG. 17, and FIG. 17 is a waveform diagram showing a main part signal waveform of FIG.

15, 10 and 15 are clocked CMOS inverters, 1 is an input terminal, 2 is an output terminal, and in FIG. 16, 11, 12, 16, and 17 are shown.
Is a P-channel MOS transistor (hereinafter simply referred to as PMO
Call S. ), 13, 14, 18, and 19 are N channels M
OS type transistors (hereinafter simply referred to as NMOS),
Reference numerals 3, 4, 5 and 6 are clock pulse input terminals. In addition, in the present specification, a bar described above the symbol in the drawing is described as "?" After the symbol in the following description.

As shown in FIG. 15, the conventional dynamic flip-flop comprises clocked CMOS inverters 10 and 15 connected in series. Then, the clocked CMOS inverter 10 is, as shown in FIG.
A PMOS 11 whose gate input is a reverse phase pulse φ1 input from the clock pulse φ1 input from the input terminal 3, and a PM whose gate input is the data D _IN input from the input terminal 1.
OS12 and its source terminal on the power supply side,
The drain terminal is arranged on the output node 7 side, and is connected in series between the power supply and the output node 7, and the NMOS 13 having the data D _IN as a gate input and the clock pulse φ1 input from the input terminal 4 are gated. The source terminals of the NMOS 14 to be input are arranged on the GND side and the drain terminals thereof are arranged on the output node 7 side, respectively.
Connected in series with ND, and clocked CM
The OS inverter 15 also has the same configuration and has a PMOS 16 whose gate input is a reverse-phase pulse φ2 − of the clock pulse φ2 input from the input terminal 5, and a signal D _{IN at the} output node 7.
The PMOS 17 having the gate as a gate input is connected in series between the power supply and the output terminal 2 after arranging the source terminal on the power supply side and the drain terminal on the output terminal 2 side, and connecting the output node 7 NMO that uses the signal D _IN ￣ of
S18 and clock pulse φ input from the input terminal 6
An NMOS 19 having 2 as a gate input has its source terminal on the power supply side and its drain terminal on the output terminal 2 side, and is connected in series between the output terminal 2 and GND.

Now, the operation will be described with reference to FIGS. 16 and 17. First, the clock pulse φ1 is H (high level)
, The NM whose gate input is the clock pulse φ1
PMO with OS14 and anti-phase pulse φ1￣ as gate input
Simultaneous conduction with S11, PMOS12 and NMOS13
And switch operation. Data D input at this time
_{If IN} is L (low level), PMOS 12 becomes conductive and NM
Since the OS 13 is cut off, the output node 7 is insulated from GND and the PMOSs 11 and 12 are conductive,
The signal D _IN ￣ at the output node 7 becomes H. Conversely, the data D _IN
When H is H, the NMOS 13 is turned on and the PMOS 12 is turned off, so that the output node 7 is insulated from the power source and the NMOS 1
Since 3 and 14 are connected to GND, signal D _IN ￣
Is L.

Next, the signal D _IN ￣ is the clocked CM of the next stage.
Although the gates are input to the PMOS 17 and the NMOS 18 of the OS inverter 15, as shown in FIG. 17, when the clock pulse φ1 is H, the clock pulse φ2 is L
Therefore, NMO with clock pulse φ2 as gate input
PMOS with S19 and anti-phase pulse φ2 ￣ as gate input
16 is cut off, so that the output terminal 2 is isolated from the power supply and GND, and the output signal D _OUT retains its previous level.

After that, when the clock pulse φ2 becomes H, the PMOS 16 and the NMOS 19 become conductive at the same time, and P
The MOS 17 and the NMOS 18 perform a switch operation. At this time, if the signal D _IN ￣ is L, the output signal D is output to the output terminal 2.
_If H is output as _OUT and conversely the signal D _IN ￣ is H, then L
Is output.

As described above, conventionally, a two-phase clock type dynamic flip-flop has been constructed.

[0013]

In the conventional dynamic flip-flop described above, the control signal (Set
Signals and reset signals, etc.) cannot be input, so setting and resetting could not be performed. That is, there is a problem that the state of the flip-flop cannot be initialized.

It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a dynamic flip-flop capable of initializing a state.

[0015]

In order to achieve the above-mentioned object, in the present invention, a logical operation of data input from the first input terminal and a signal input from the second input terminal is performed by a clock. A plurality of clocked logic gates that perform the operation result in synchronization with the clock pulse input from the input terminal and output from the output terminal are output from the output terminal of the clocked logic gate in the previous stage So as to be inputted to the first input terminal of the clocked logic gate as the data, so that a set signal or a reset signal is inputted as the signal from the second input terminal of each clocked logic gate. Configured.

[0016]

For example, as the clocked logic gate,
Two clocked NOR gates are used and two of these clocked NOR gates are connected in cascade. In this case, the flip-flop can be set by inputting the set signal from the second input terminal of the preceding clocked NOR gate. In addition, the second clocked NOR gate in the latter stage
The flip-flop can be reset by inputting a reset signal from the input terminal of the. Therefore,
The state of the flip-flop can be initialized.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a concrete circuit configuration of FIG. 1, and FIG.
4 is a waveform diagram showing the signal waveform of the main part of FIG.

In FIG. 1, reference numerals 20 and 30 denote clocked Cs.
MOS NOR gates 8 and 9 are control signal input terminals, and in FIG. 2, reference numerals 21, 22, 23, 31, and 3 are used.
2, 33 are PMOS, 24, 25, 26, 34, 35,
36 is an NMOS.

In this embodiment, as shown in FIG.
_A first-stage clocked CMOS NOR gate 20 that performs a logical operation between _IN and a Set signal (denoted as S in the figure) as a control signal in synchronization with the clock pulse φ, and its output signal D _IN
A second-stage clocked CMOS NOR gate 30 that performs a logical operation between a clock signal and a reset signal (denoted as R in the figure) as a control signal in synchronization with a reverse phase pulse φ of the clock pulse φ
And, and outputs D _OUT as an output signal.

The configuration of this embodiment will be described in more detail with reference to FIG.

The clocked CMOS NOR gate (hereinafter referred to as NOR) 20 in the first stage has a PMOS 21 whose gate input is the data D _IN input from the input terminal 1 and a gate for the Set signal input from the input terminal 8. Input P
Reverse phase pulse φ input from the MOS 22 and the input terminal 3
A PMOS 23 having a gate input of ￣ is connected in series between the power supply and the output node 7 with its source terminal on the power supply side and its drain terminal on the output node 7 side. The drain terminal of the NMOS 24 having the gate input of the clock pulse φ input from 4 is connected to the output node 7, and between the source terminal and GND,
An NMOS 25 having a gate input of the data D _IN input from the input terminal 1 and an NMOS 26 having a gate input of the Set signal input from the input terminal 8 respectively have a source terminal on the GND side and a drain terminal on the drain side. NMOS
It is arranged on the source terminal side of 24 and connected in parallel.

Further, the NOR 30 of the second stage also has the PMOS 3
1, 32, 33 and NMOSs 34, 35, 36 are connected in the same manner as the NOR 20 of the first stage, respectively. However, the PMOS 31 and the NMOS 35 use the signal D _IN ￣ at the output node 7 as a gate input, and PM
The OS 32 and the NMOS 36 are R input from the input terminal 9.
The eset signal is used as a gate input, the PMOS 33 is used as a gate input for the clock pulse φ input from the input terminal 4, and the NMOS 34 is used as a gate input for the negative phase pulse φ_ input from the input terminal 3.

Next, the operation of this embodiment will be described with reference to FIGS. 2, 3 and 4. When the setting and the reset are not performed, the Set signal and the Reset signal are both L (low level), and therefore, in that case, the PMOSs 22 and 32 are turned on (that is, made conductive) and the NMOSs 26 and 3 are turned on.
6 is off (ie, shut off).

Therefore, first, in the NOR 20, when the clock pulse φ becomes H (high level), the PMOS 23
And the NMOS 24 is turned on. At that time, if the input data D _IN is H, the NMOS 25 is turned on and the PMOS 25 is turned on.
Since 21 is turned off, the output node 7 is electrically connected to GND,
The signal D _{IN − at the} output node 7 becomes L as shown in FIG. On the contrary, if the data D _IN is L, the PMOS 21 is turned on,
Since the NMOS 25 is turned off, the output node 7 is brought into conduction with the power source, and the signal D _{IN —} becomes H as shown in FIG. In this way, the inverted signal of the data D _IN is output to the output node 7. As described above, the NOR 20 operates in synchronization with the rising of the clock pulse φ.

On the other hand, in the NOR 30, the clock pulse φ
While H is H, the PMOS 33 and the NMOS 34 are off. Therefore, the input / output relationship of the NOR 30 is cut off, and the signal D _{IN — at} the output node 7 is not output from the output terminal 2 as the output signal D _OUT .

After that, when the clock pulse φ becomes L and the anti-phase pulse φ_ becomes H, the input / output relation of the NOR 20 is conversely disconnected, and the PMOS 33 and the NMOS 34 of the NOR 30 are turned on. At that time, the signal D _IN ￣ is H
Then, the NMOS 35 is turned on and the PMOS 31 is turned off, so that the output terminal 2 is electrically connected to the GND and the output signal D
_OUT becomes L as shown in FIG. Conversely, the signal D _IN ￣ is L
Then, the PMOS 31 is turned on and the NMOS 35 is turned off, so that the output terminal 2 is electrically connected to the power source and the output signal D _OUT
Becomes H as shown in FIG. In this way, the inverted signal of the signal D _{IN —} is output from the output terminal 2. That is, as the output signal D _OUT , the data D _IN is output as a signal in synchronization with the rising of the negative phase pulse φ_. As described above, the NOR 30 operates in synchronization with the rising of the negative phase pulse φ_.

As described above, the operation without setting and resetting is the same as the operation when the two-phase clock is the single-phase clock in the conventional example of FIG.

Next, when setting is performed, the Set signal is set to H as shown in FIG. The period in which the Set signal is set to H is set in advance so that the clock pulse φ rises within that period.

When the Set signal goes high in this way, NOR2
Since the PMOS 22 of 0 is turned off and the NMOS 26 is turned on, the output node 7 is isolated from the power supply. Therefore,
After that, when the clock pulse φ becomes H, the NMOS 24
Is turned on, the output node 7 conducts to GND, so that the signal D _IN _ is always L regardless of the data D _IN . On the other hand, even if the Set signal becomes H, the operation of the NOR 30 is the same as before, so when the signal D _IN ￣ is L,
When the negative-phase pulse φ- becomes H, the output signal D _OUT from the output terminal 2 becomes H which is an inverted signal of the signal D _IN _, and as a result, data is set.

Next, when resetting is performed, the Reset signal is set to H as shown in FIG. The period in which the Reset signal is set to H is set in advance so that the reverse-phase pulse φ_ rises within that period.

When the Reset signal goes high as described above, the PMOS 32 of the NOR 30 is turned off and the NMOS 36 is turned on, contrary to the case of the set, so that the output terminal 2 is insulated from the power supply. Therefore, after that, when the reverse-phase pulse φ_ becomes H, the NMOS 34 is turned on, so that the output terminal 2 becomes conductive with the GND, whereby the output signal D _OUT changes to the signal D
It always becomes L regardless of _IN , and as a result, the data has been reset.

As described above, data setting and resetting are performed in synchronization with the rising of the anti-phase clock pulse φ_, as shown in FIG.

When the Reset signal is set to H, the signal D _IN ￣
However, the output signal D _OUT always becomes L, and even if the Set signal becomes H immediately before that, it is preferentially reset.

As described above, this embodiment is composed of a clocked CMOS NOR gate, operates with a single-phase clock, and performs a reset-priority dynamic in which setting and resetting are performed in synchronization with the rising of the negative-phase pulse φ_. It is an example of a type set / reset flip-flop.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention, FIG. 6 is a circuit diagram showing a concrete circuit configuration of FIG. 5, and FIG.
FIG. 7 is a waveform diagram showing a signal waveform of a main part of FIG. 6.

In FIG. 5, 40 and 50 are clocked Cs.
It is a MOS NAND gate, and in FIG.
1, 42, 43, 51, 52, 53 are PMOS, 44,
Reference numerals 45, 46, 54, 55 and 56 are NMOS.

In this embodiment, as shown in FIG. 5, data D
_IN and Reset Negative signal as control signal (R in the figure
A clocked CMOS NAND gate 40 in the first stage, which performs a logical operation with (denoted as N) in synchronization with the clock pulse φ,
The output signal D _IN and Set Negative as a control signal
It is composed of a second-stage clocked CMOS NAND gate 50 that performs a logical operation with a signal (denoted as SN in the figure) in synchronization with a reverse phase pulse φ of a clock pulse φ, and outputs D _OUT as an output signal. To do.

The structure of this embodiment will be described in more detail with reference to FIG. The first-stage clocked CMOS NAND gate (hereinafter referred to as NAND) 40 has an NMOS 4 whose gate input is the data D _IN input from the input terminal 1.
6, an NMOS 45 whose gate input is the Reset Negative signal input from the input terminal 8, and an NMOS whose gate input is the clock pulse φ input from the input terminal 4.
44 and 44 are connected in series between the GND and the output node 7 with the source terminal on the GND side and the drain terminal on the output node 7 side, respectively, and the reverse input from the input terminal 3. Connect the drain terminal of the PMOS 43 that receives the phase clock pulse φ ￣ as the gate input to the output node 7,
Between the source terminal and the power source, a PMOS 41 having a gate input of the data D _IN input from the input terminal 1 and a PMOS 42 having a gate input of the Reset Negative signal input from the input terminal 8 are respectively provided. The source terminal is disposed on the power supply side, the drain terminal is disposed on the source terminal side of the PMOS 43, and the PMOS 43 is connected in parallel.

The second-stage NAND 50 is also a PMOS
51, 52, 53 and NMOSs 54, 55, 56 are connected in the same manner as the NAND 40 of the first stage, respectively. However, the PMOS 51 and the NMOS 56 use the signal D _IN ￣ at the output node 7 as a gate input, and
The PMOS 52 and the NMOS 55 use the Set Negative signal input from the input terminal 9 as a gate input, and
The S53 has a gate input of the clock pulse φ input from the input terminal 4, and the NMOS 54 has a gate input of the anti-phase pulse φ input from the input terminal 3.

Next, the operation of this embodiment will be described with reference to FIGS. 6 and 7.

When setting and resetting are not performed,
Both the Set Negative signal and the Reset Negative signal are H
Therefore, in that case, the PMOSs 42 and 52 are turned off and the NMOSs 45 and 55 are turned on. The operation at this time is almost the same as the operation in the case where the setting and resetting is not performed in the above-described first embodiment, that is, the NAND 40 operates in synchronization with the rising edge of the clock pulse φ and the NAND 50 operates in the reverse phase pulse. It operates in synchronization with the rise of φ, and as the output signal D _OUT , the data D _IN is output as a signal synchronized with the rise of the antiphase pulse φ. The signal waveform at this time is also the same as that shown in FIG.

Next, when resetting is performed, the Reset Negative signal is set to L as shown in FIG. In addition, Reset
The period in which the Negative signal is set to L is preset so that the rising edge of the clock pulse φ comes within that period.

When the Reset Negative signal goes to L in this way, the PMOS 42 of the NAND 40 turns on and the NMO
Since S45 is turned off, the output node 7 is insulated from GND. Therefore, thereafter, when the clock pulse φ becomes H, the PMOS 43 is turned on, so that the output node 7 is brought into conduction with the power supply, whereby the signal D _IN _ always becomes H regardless of the data D _IN . On the other hand, the operation of the NAND 50 is similar to the case where the setting and resetting is not performed, so
_{When IN} ￣ is H and the reverse phase pulse φ￣ becomes H, the output signal D _OUT from the output terminal 2 becomes L which is the inverted signal of the signal D _IN ￣, and as a result, the data is reset. It will be.

Next, when setting is performed, the Set Negative signal is set to L as shown in FIG. In addition, Set Negati
The period in which the ve signal is set to L is set in advance so that the reverse phase pulse φ_ rises within that period.

When the Set Negative signal goes to L in this way, the PMOS 52 of the NAND 50 turns on and the NMO
Since S55 is turned off, the output terminal 2 is insulated from GND. Therefore, after that, when the reverse-phase pulse φ- becomes H, the PMOS 53 is turned on, so that the output terminal 2 is electrically connected to the power supply, whereby the output signal D _OUT is always H regardless of D _IN _, and as a result, , The data has been set.

As described above, data setting and resetting are performed in synchronization with the rising of the anti-phase clock pulse φ_, as shown in FIG.

[0048] It should be noted that, if the Set Negative signal to L, if signal D _IN ¯ what a is, the output signal D _{OU T} would always become H, Reset Negative signal in the immediately preceding example is L
Even if is set, it will be set preferentially.

As described above, this embodiment is composed of clocked CMOS NAND gates, operates with a single-phase clock, and sets and resets in synchronization with the rise of the negative-phase clock pulse φ_. It is an example of a dynamic type set / reset flip-flop.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention, FIG. 9 is a circuit diagram showing a concrete circuit configuration of FIG. 8, and FIG.
Reference numeral 0 is a waveform diagram showing a signal waveform of a main part of FIG. 9.

As shown in FIG. 8, this embodiment is an example of a reset-type dynamic set / reset flip-flop composed of a clocked CMOS NOR gate, as in the first embodiment. This embodiment is different from the first embodiment in that it operates with a two-phase clock.

That is, as shown in FIG. 9, in the NOR 20, the NMOS 24 has the gate input of the clock pulse φ1 input from the input terminal 4, and the PMOS 24 has the PMOS input.
Reference numeral 23 is a gate input of a reverse phase pulse φ1 ￣ of the clock pulse φ1 input from the input terminal 3, and therefore N
The OR 20 operates in synchronization with the rising edge of the clock pulse φ1. On the other hand, in NOR30, NMOS
Reference numeral 34 designates a clock pulse φ2 input from the input terminal 6 as a gate input, and PMOS 33 has a reverse phase pulse φ2 of the clock pulse φ2 input from the input terminal 5.
Since the gate is used as the gate input, the NOR 30 operates in synchronization with the rising edge of the clock pulse φ2.

In this embodiment, when the setting and the reset are not performed, both the Set signal and the Reset signal are L and PM
Since the OSs 22 and 32 are turned on and the NMOSs 26 and 36 are turned off, the operation in that case is the same as in the case of the conventional example shown in FIG. 16, and therefore the signal waveform at that time is also as shown in FIG.

Further, in the present embodiment, the operation for setting or resetting is almost the same as the operation for setting or resetting in the first embodiment.
However, in this embodiment, the setting and resetting are performed in synchronization with the rising of the clock pulse φ2, and the signal waveform at that time is as shown in FIG.

In FIG. 10, the clock pulse φ1 rises during the period in which the Set signal is H, and the clock pulse φ2 rises during the period in which the Reset signal is H. Are set in advance.

FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention, FIG. 12 is a circuit diagram showing a concrete circuit configuration of FIG. 11,
FIG. 13 is a waveform diagram showing the signal waveform of the main part of FIG.

As shown in FIG. 11, this embodiment is an example of a set-priority dynamic type set / reset flip-flop composed of clocked CMOS NAND gates, as in the second embodiment. This embodiment differs from the second embodiment in that it operates with a two-phase clock.

That is, as shown in FIG.
, The NMOS 44 uses the clock pulse φ1 input from the input terminal 4 as a gate input, and PM
OS43 is a clock pulse φ input from the input terminal 3.
Since the reverse phase pulse φ1 of 1 is used as the gate input, the NAND 40 operates in synchronization with the rising of the clock pulse φ1. On the other hand, in the NAND 50, the NMOS 54 has the gate input of the clock pulse φ2 input from the input terminal 6, and the PMOS 5
3 has a gate input of a reverse phase pulse φ2 of the clock pulse φ2 input from the input terminal 5, and therefore NA
The ND 50 operates in synchronization with the rising edge of the clock pulse φ2.

In this embodiment, when the setting and resetting are not performed, the Set Negative signal and the Reset Negati signal are set.
Both ve signals are H, PMOS 42 and 52 are off, NMO
Since S45 and 55 are turned on, the operation in that case is as shown in FIG.
This is the same as the case of the conventional example shown in FIG. 6, and therefore the signal waveform at that time is as shown in FIG.

In this embodiment, the operation for setting or resetting is almost the same as the operation for setting or resetting in the second embodiment.
However, in this embodiment, setting and resetting are performed in synchronization with the rising of the clock pulse φ2, and the signal waveform at that time is as shown in FIG.

In FIG. 13, the clock pulse φ1 rises during the period when the Reset Negative signal is L, and the clock pulse φ2 during the period when the Set Negative signal is L. Is set in advance so that each of the rising edges comes.

Various means are conceivable as means for generating two-phase clocks such as clock pulses φ1 and φ2. Here, one means is shown in FIG. 14, and its operation will be briefly described.

The circuit shown in FIG. 14 has a 2-input NOR gate 10.
8 and 109 and an inverter 107.
A signal obtained by cross-connecting the input NOR gates 108 and 109, inputting the master clock MCK and the output signal from the 2-input NOR gate 109 to the 2-input NOR gate 108, and inverting the master clock MCK to the 2-input NOR gate 109 by the inverter 107. By inputting MCK and the output signal from the 2-input NOR gate 108,
Clock pulses φ1 and φ as two-phase clocks that do not overlap
Get 2.

Further, a plurality of the dynamic flip-flops of the above-mentioned respective embodiments are connected in cascade, and clock input terminals for inputting clock pulses and set input terminals for inputting Set signal (or Set Negative signal). , Or Reset signal (or Reset Negati
If the shift register is configured by connecting the reset input terminals for inputting (ve signal) respectively, a Set signal (or Set Negative signal) is input from the set input terminal.
From the reset input terminal to the Reset signal (or Reset
By inputting each of the Negative signals), all the flip-flops connected in cascade can be set or reset at the same time, and their states can be initialized.

[0065]

According to the present invention, there is an effect that a dynamic flip-flop capable of initializing a state, which could not be realized by the conventional technique, can be realized by a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of FIG.

FIG. 3 is a waveform diagram showing a signal waveform of a main part of FIG.

FIG. 4 is a waveform diagram showing a main part signal waveform of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

6 is a circuit diagram showing a specific circuit configuration of FIG.

FIG. 7 is a waveform diagram showing a signal waveform of a main part of FIG.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

9 is a circuit diagram showing a specific circuit configuration of FIG.

FIG. 10 is a waveform diagram showing a signal waveform of a main part of FIG.

FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention.

12 is a circuit diagram showing a specific circuit configuration of FIG.

FIG. 13 is a waveform diagram showing a signal waveform of a main part of FIG.

FIG. 14: 2 used in the third and fourth embodiments
It is a circuit diagram which shows one specific example of the generation means of a phase clock.

FIG. 15 is a circuit diagram showing a conventional dynamic flip-flop.

16 is a circuit diagram showing a specific circuit configuration of FIG.

FIG. 17 is a waveform diagram showing a main part signal waveform of FIG. 16.

[Explanation of symbols]

1 ... Input terminal, 2 ... Output terminal, 3, 4, 5, 6 ... Clock pulse input terminal, 8, 9 ... Control signal input terminal, 1
0, 15 ... Clocked CMOS inverter, 20, 30
... Clocked CMOS NOR gate, 40, 50 ... Clocked CMOS NAND gate.

Claims (1)

[Claims] 1. A logical operation between data input from a first input terminal and a signal input from a second input terminal is performed in synchronization with a clock pulse input from a clock input terminal, and the operation result is obtained. A plurality of clocked logic gates that output from the output terminal, and the operation result output from the output terminal of the clocked logic gate in the previous stage is input as the data to the first input terminal of the clocked logic gate in the subsequent stage. So that the state of the flip-flop can be initialized by inputting a set signal or a reset signal as the signal from the second input terminal of each clocked logic gate. Dynamic flip-flop characterized by.