JPS55104121A - Delayed type flip flop with direct reset - Google Patents

Delayed type flip flop with direct reset

Info

Publication number
JPS55104121A
JPS55104121A JP1247279A JP1247279A JPS55104121A JP S55104121 A JPS55104121 A JP S55104121A JP 1247279 A JP1247279 A JP 1247279A JP 1247279 A JP1247279 A JP 1247279A JP S55104121 A JPS55104121 A JP S55104121A
Authority
JP
Japan
Prior art keywords
reset
level
terminal
clock signal
delayed type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1247279A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP1247279A priority Critical patent/JPS55104121A/en
Priority to CA331,184A priority patent/CA1130399A/en
Priority to US06/054,974 priority patent/US4281259A/en
Priority to DE7979103838T priority patent/DE2967106D1/en
Priority to EP79103838A priority patent/EP0011128B1/en
Publication of JPS55104121A publication Critical patent/JPS55104121A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To enable to reset directly, by connecting the transistor Tr of reverse conducting type to the connection point between the transmission gate of the master and slave sections of delayed type FF and the inverter. CONSTITUTION:The master section consists of the transmission gate TG3 which turns on when the clock signal from the CL terminal is 0 and of the inveter IV4, and the slave section 2 consists of TG5 which turns on when the clock signal is 1 and the IV6. The n channel MOSFET 7 is connected between the connecting point A of TG5 and IV6 and the level 0, and P channel MOSFET 8 is connected between the connection point of TG5 and IV6 and the level 1. The gate of FET7 and FET8 is directly or via IV9 to the reset R terminal. FET7 and FET8 are conducted with the reset signal of the R terminal, the 0 or 1 level fed to the input of IV4 and IV6 is direclty reset, enabling to reset independently of the level of the clock signal at that time.
JP1247279A 1978-11-08 1979-02-05 Delayed type flip flop with direct reset Pending JPS55104121A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1247279A JPS55104121A (en) 1979-02-05 1979-02-05 Delayed type flip flop with direct reset
CA331,184A CA1130399A (en) 1978-11-08 1979-07-05 Digital phase comparing apparatus
US06/054,974 US4281259A (en) 1978-11-08 1979-07-05 Digital phase comparing apparatus
DE7979103838T DE2967106D1 (en) 1978-11-08 1979-10-08 Digital phase comparing apparatus
EP79103838A EP0011128B1 (en) 1978-11-08 1979-10-08 Digital phase comparing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1247279A JPS55104121A (en) 1979-02-05 1979-02-05 Delayed type flip flop with direct reset

Publications (1)

Publication Number Publication Date
JPS55104121A true JPS55104121A (en) 1980-08-09

Family

ID=11806305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1247279A Pending JPS55104121A (en) 1978-11-08 1979-02-05 Delayed type flip flop with direct reset

Country Status (1)

Country Link
JP (1) JPS55104121A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63254815A (en) * 1987-04-13 1988-10-21 Hitachi Ltd Dynamic flip-flop
JPH06283977A (en) * 1994-03-01 1994-10-07 Hitachi Ltd Dynamic type flip-flop

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63254815A (en) * 1987-04-13 1988-10-21 Hitachi Ltd Dynamic flip-flop
JPH06283977A (en) * 1994-03-01 1994-10-07 Hitachi Ltd Dynamic type flip-flop

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