JPS63151215A - Hazard free circuit - Google Patents

Abstract

PURPOSE:To attain hazard free by providing a transmission gate retarding a 1st input signal additionally in response to the delay time of an inverter to a circuit including a conventional AND/OR inverter circuit. CONSTITUTION:In receiving three signals of the 1st, 2nd and 3rd input signals 111, 117 and 127 to obtain an output logic signal 133, the input signal 11 is retarded corresponding to the delay time of the inverter 115 by a transmission gate 125. That is, the delay signal 123 corresponds to the delay in the inverter 115. Thus, the input signal 111 supplied to an AND gate 131 is retarded by the transmission gate 125 corresponding to the time delay of the inverted output signal 113 inputted to an AND gate 121. Thus, no faulty output due to the delay in the inverter 115 is caused in the output logic signal 133.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example ■, Correspondence between the Example and Figure 1 Relationship ■, Structure of the Example ■, Operation of the Example ■, Summary of the Example ■0 Modifications of the Invention Effects of the Invention [Summary] A hazard-free circuit T path including an and-or inverter, Obtain a first logical product output of the negative logic output of the first input signal and the second input signal, and a second logical product output of the third input signal and the first input signal, and calculate the negative logical sum of these two wheel filling outputs. In this case, a transmission gate is provided to delay the first input signal in accordance with the delay time of the in-hark that takes the negative logic of the first input signal, and a second logical product is performed based on the signal passed through the transmission gate 1. By providing an output, there are no unwanted hazards in the output logic signal.

[Industrial application field]

The present invention relates to hazard-free circuits, such as CMOS
In an AND-OR-IN park macro cell using a gate array, when obtaining an AND-OR inverter output signal for at least three input signals, no undesirable signal (hazard waveform) is generated in the output. The present invention relates to a hazard-free circuit constructed as described above.

[Conventional technology]

Conventionally, AND signals have been widely used for various types of signal processing.
The OR inverter is configured by, for example, a CMOS gate array macrocell on an LSI.

An example of a circuit using an AND-OR inverter is one configured to obtain one output based on three input signals as shown in FIG. Here, AND-OR-IMPARK is based on two input signals A and B, and input signal C is applied as a control signal for switching. and gate 33
1 performs a logical product of input signal A and input signal B and outputs a logical product output signal 329. In addition, the inverter 31
5 inverts the input signal C and outputs an inverted output signal 313. The AND gate 321 performs a logical product of the other input signal B and the inverted output signal 313 and outputs a logical product output signal 319. The AND output signal 329 obtained in this way
and AND output signal 319 are supplied to NOR gate 335, and an output signal which is the NOR of these two signals is obtained.

A truth table representing the operation of the hazard-free circuit shown in FIG. 4 is shown in FIG. The logic state of the output signal changes depending on the two human input signals A and input signal B, and another input signal C. The output signal of an AND-OR inverter based on the operation shown in this truth table is applied to various circuits.

[Problem that the invention seeks to solve]

By the way, in a conventional hazard-free circuit including an AND-OR inverter configured as described above, ideally, the two input signals A and B are both in the logic state "
When the output signal is "1", the output signal can take a logic state of "0" regardless of which logic state the other input signal C, which is a control signal, takes.

It's ideal. Therefore, even if the two input signals A and B are both in the logic state "1" and the other input signal C transitions from the logic state "1" to the logic state "0", the Then the output signal must be in the logic state "O".

However, as a practical matter, the inverter 315 has a delay time inherent to the element. Therefore, the inverted output signal 313 obtained by inverting the input signal C has a time delay with respect to the input signal C. Therefore, although the output signal should normally be in the logic state "0", due to the internal delay of the inverter 315, a signal waveform different from the original function occurs in the output signal.

Now, when the two input signals A and the human input signal B are both in the logic state "'1", the input signal C changes from the logic state "1" to the logic state "0", as shown in FIG. 6(a). Let's look at the case where the transition occurs. Inverted output signal 313 of inverter 315
transitions from the logic state "o" to the logic state "1pa" after a delay time corresponding to the internal delay of one stage of the macrocell (
6(C)), the AND output signal 329 based on the input signals A and C also changes from the logic state "'1" to the logic state after a delay time corresponding to the internal delay of one stage of macrocell by the AND gate 331. Transition to “’0” (6th
(See Figure (b)), the AND output signal 319 of the AND gate 321 also changes from the logic state "0" to the logic state "1" after a delay time corresponding to the internal delay of one stage of the macrocell from the rise of the inverted output signal 313. (Figure 6(d))
In this way, since the times at which the AND output signal 329 and the AND output signal 319 transition are different, the time at which the AND output signal 329 falls and the time at which the AND output signal 319 transitions are different.
Both signals are in logic state “0” between the times when 9 rises.
A state occurs, and the output signal of the NOR gate 335 becomes the logic state "'1" during that time.Therefore,
As shown in FIG. 6(e), a hazard waveform appears after a delay corresponding to one stage of macrocells.

Because of the hazard thus created, this and
Depending on the logic circuit connected after the OR inverter, malfunction may occur. For example, if the output signal of the AND-OR inverter is used as a clock signal for a flip-flop, there is a problem that the flip-flop may malfunction.

Therefore, there is a restriction in using the AND-OR inverter that a circuit that may cause such a malfunction cannot be connected as a subsequent stage of the AND-OR inverter.

By the way, as a means to solve the problems caused by such a hazard waveform, a circuit configuration as shown in FIG. 7 has been used in the past. In other words, an AND gate 551 that takes the AND of two input signals A and B is added separately, and the AND gate 551
．． The outputs of the AND gate 331 and the AND gate 321 were introduced into a NOR gate 535, and an output signal was obtained from the NOR gate 535. As a result, even if the control input signal C transitions from the logic state "I" to the logic state "0" when the two input signals A and B are both in the logic state "1", the output signal will not change. The hazard waveform will not occur again.

However, there is a problem that a new AND gate 551 must be added for hazard suppression, and the circuit configuration as a hazard-free circuit including an AND-OR inverter becomes large.

The present invention was created in view of the above points, and an object of the present invention is to provide a hazard-free circuit that has a simple circuit configuration and does not generate any undesirable signals in the output.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the hazard-free circuit of the present invention.

In the figure, the inverter 115 has a first input signal 111
The inverted output signal 113 is output by taking the negative logic of .

AND gate 121 outputs the inverted output signal 113 and the second
A logical product is performed based on the input signal 117 and a first logical product output signal 119 is output.

The transmission gate 125 receives the first input signal 11
1 by a desired time and output a delayed signal 123.

The AND gate 131 performs a logical product based on the delayed signal 123 and the third input signal 127 and outputs a second logical product output signal 129 .

The NOR gate 135 receives the first AND output signal 119
and the NOR based on the second AND output signal 129 to output an output logic signal 133.

Therefore, overall, at least the first input signal 111,
Second input signal 117. When the output logic signal 133 is obtained by inputting the three third human input signals 127, the transmission gate 125 is configured to delay the first input signal 111 in accordance with the delay time of the inverter 115.

[For production]

The AND gate 121 outputs a first AND output signal 11 of the negative logic output of the first input signal 111 and the second input signal 117.
Give 9.

The delayed signal 123 of the first input signal 111 delayed for a predetermined time by the transmission gate 125 is ANDed with the third input signal 127 by the AND gate 131, and a second AND output signal 129 is output.

Second AND output signal 129 and first AND output signal 119
The output logic signal 133 from the NOR gate 135 is obtained.

Since the delayed signal 123 corresponds to the delay of the inverter 115, an undesired signal output due to the delay of the inverter 115 does not occur in the output logic signal 133.

In the present invention, the first input signal 111 supplied to the other AND gate 131 corresponds to the time delay of the inverted output signal 113 inputted to one AND gate 1-121.
Since the output logic signal 133 is delayed by the transmission gate 125, no undesirable signal output due to the delay of the impark 115 occurs in the output logic signal 133.

〔Example〕

Hereinafter, one example of the present invention will be explained based on the drawings. Explain in detail.

FIG. 2 shows the configuration of a hazard-free circuit in one embodiment of the present invention. FIG. 3 shows the configuration of an AND-OR inverter included in the hazard-free circuit according to the embodiment of the present invention shown in FIG.

■． Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The first input signal 111 corresponds to the human input signal C.

Inverted output signal 113 corresponds to the inverted output signal of inverter 215.

Inverter 115 corresponds to inverter 215.

The second input signal 117 corresponds to input signal B.

The first logical product output signal 119 is ant game-1-221
corresponds to the output signal of

AND gate 121 corresponds to AND gate 221.

Delay signal 123, transmission gate 1 This corresponds to the output signal of 225.

Transmission gate 125 corresponds to transmission gate 225.

The third input signal 127 corresponds to the input signal.

The second AND output signal 129 corresponds to the output signal of the AND gate 231.

AND gate 131 corresponds to AND gate 231.

The output logic signal 133 corresponds to the output logic signal 233 (output signal D) of the NOR games 1 to 235.

The NOR gate 135 corresponds to the NOR gate 235.

2-jlU Risk 1 An embodiment of the present invention will be described below assuming that the above-mentioned correspondence exists.

In the embodiment of the present invention shown in FIG. 2, the hazard-free circuit is formed of a CMOS gate array, and includes an impark 215 and an AND-OR inverter 210, which are macro cells thereof. This and or inverter 2
If 10 is represented by a symbol, it has a configuration as shown in FIG. 3, which is the same configuration as the conventional one. In other words, two AND gates 231 and 221, and a NOR gate 2 that NORs their output signals.
It consists of 35.

The configuration of this AND-OR inverter 210 will be specifically shown. 4 FETs connected in series 251.253,2
55 and 257 and four other FETs 261, 263
．． 265 and 267. In other words, FET
Connect the drain of 251 to the positive voltage source terminal of, for example, 5 volts,
The sources are connected to the drains of the FETs 253, respectively. The source of FET 253 is connected to the drain of FET 255, and the source of FET 255 is connected to the drain of FET 257. The source of FET 257 is grounded.

The same applies to the other four FETs 261, 263, 265 and 267. That is, the drain of the FET 261 is connected to the positive voltage source terminal, and the source is connected to the drain of the FET 263. The source of FET263 is FET
The source of the IET 265 is connected to the drain of the FET 267. FET2
The source of 67 is grounded.

Furthermore, the sources of FET 251 and FET 261 are connected in common, the gates of two FETs 253 and 255 are connected, and the gate of FET 257 is connected to FET 263.
, and both gates of two FETs 261 and 267 are connected.

Here, four FETs 251, 253, 261 and 2
63 is a P-channel FET, and the other four FETs 25
5, 257, 265 and 267 are N-channel FETs.

Input signal C is supplied to inverter 215 and also to transmission gate 225. This transmission gate 225 is a switch consisting of a pair of N-type transistor and P-type transistor. That is, the N-type transistor side is connected to the positive voltage source terminal, and the P-type transistor side is grounded. The output of this transmission gate 225 is supplied to both gates 1- of FETs 257 and 263 in the AND-OR inverter 210.

In addition, the input signal B is input to the AND-OR inverter 210
It is designed to be supplied to the gates of two FETs 251 and 265 within.

Furthermore, the other input signal A is the AND-OR inverter 2.
It is commonly supplied to both gates of two FETs 253 and 255 in FET 10.

The output signal D (output logic signal 233) of the AND-OR inverter 210 is taken out from a common connection point between the source of the FET 263 and the drain of the FET 265.

(b) Ashing The operation of the embodiment configured as described above is substantially the same as that described in connection with FIGS. 4 and 5. In other words,
The truth table when an AND-OR inverter essentially functions is the same as that shown in FIG.

In the embodiment shown in FIG. 2, the transmission gate 225 provides a delay time corresponding to the internal delay of the inverter 215, which is one stage of the macrocell.

That is, when power is turned on to the hazard-free circuit including this AND-OR inverter, the transmission gate 225 becomes conductive, and since it is one macro cell, its internal time occurs. The input signal C is
The signal is supplied to the AND-OR inverter 210 after being delayed by the delay time inherent to the transmission gate 225.

In this way, the signal supplied to both gates of FETs 257 and 263 in AND-OR inverter 210 can be input to inverter 21 without polarity inversion of input signal C.
It is delayed by a time corresponding to the internal delay of 5. Therefore, both FETs 26 in the AND-OR inverter 210
Since the inverted signal of the input signal C supplied to both the gates 4 and 267 and the signal delayed by the transmission gate 225 (input signal C) change their logic states almost simultaneously, the NOR gate 235 is Such a hazard waveform will not occur.

(2) Summary of the Embodiment In this way, the input signal C is delayed by the transmission gate 225 in accordance with the delay time of the impark 215 and is supplied to the AND gate 231. As a result, no undesirable signal output occurs in the output logic signal 233.

Therefore, there is no problem even if a flip-flop circuit is connected after the AND-OR inverter 210 and the output logic signal Q 233 of the NOR gate 235 is used for its clock.

■0-shot H modification Note that in the embodiment of the present invention described above, the transmission gate 225 is a so-called one-stage transmission gate 225, but it may be formed in multiple stages in consideration of the internal delay of the inverter 215. . In short, the inverter 21
The transmission gate 225 may be formed to delay the time corresponding to the internal delay in 5.

Further, in the embodiments of the present invention described above, an example of an FBT with only one power supply was shown, but it goes without saying that an FET with two power supplies may be used.

Furthermore, in "■, Correspondence between Examples and FIG. 1",
Although the correspondence between FIG. 1 and the present invention has been described, those skilled in the art will easily imagine that the present invention is not limited to this and that there are various modifications.

[Effect of the Invention] As described above, according to the present invention, the logical product output of the negative logic output of the first input signal and the second input signal and the logical product of the third input signal and the first input signal When taking the NOR at the output, by providing a transmission gate that delays the first input signal in accordance with the delay time of the inverter and supplying it to the AND gate, it is possible to prevent undesirable signal output from the output logic signal. This is extremely useful from a practical point of view.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a hazard-free circuit of the present invention, Fig. 2 is a block diagram of a hazard-free circuit according to an embodiment of the present invention, and Fig. 3 is a block diagram of the hazard-free circuit according to an embodiment of the present invention. Fig. 4 is a block diagram of a U hazard-free circuit including a conventional AND-OR inverter; Fig. 5 is an explanatory diagram of the operation of the AND-OR inverter shown in Fig. 4; FIG. 6 is an operating waveform diagram of the AND-OR inverter shown in FIG. 4, and FIG. 7 is a configuration diagram showing another conventional hazard-free circuit. In the figure, 111 is the first input signal, 113 is the inverted output signal, 115 is the inverter, 117 is the second input signal, 119 is the first AND output signal, 121.131 is the ant game-1, 123 is the delayed signal, 125 is a transmission gate, 127 is a third input signal, 129 is a second AND output signal, 133 is an output logic signal, 135 is a NOR gate, 210 is an AND-OR inverter, 215.315 is an inverter, 221. 231, 321, 331, 551 are AND gates, 225 is a transmission gate, 233 is an output logic signal, 235 is a NOR gate, 313 is an inverted output signal, 319.329 is an AND output signal, 335.535 is a NOR logic It is a Japanese gate. 2nd generation [Oebu I row t customer υ day] Imperial edict 2nd figure λa inba'-ta 94-tJ+ffl 3rd figure Figure front bundle I =) Su Shu Kui Explanation 1 Flash Figure 6

Claims (4)

[Claims] (1) An inverter (115) that takes the negative logic of the first input signal (111) and outputs an inverted output signal (113), an inverted output signal (113) and a second input signal (117)
A first logical product output signal (119) is obtained by performing a logical product based on
and a transmission gate (12) that delays the first input signal (111) by a desired time and outputs a delayed signal (123).
5), an AND gate (131) that takes a logical product based on the delayed signal (123) and a third input signal (127), and outputs a second logical product output signal (129), and a first logical product output signal (129). 119) and a second AND output signal (129) to output an output logic signal (133); A hazard-free circuit characterized in that it is configured to input three signals, a second input signal (117) and a third input signal (127), and output an output logic signal (133). (2) The hazard-free circuit according to claim 1, wherein the transmission gate (125) is a transmission gate formed by a pair of PNP transistor and NPN transistor. (3) Transmission gate (125) is PNP
The hazard-free circuit according to claim 1, characterized in that it is constructed by connecting a plurality of pairs of transistors and NPN transistors in series. (4) The first input signal (111) is an AND gate (12
1) and an AND gate (131).