JP2900994B2 - Arbiter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to an arbiter circuit, and more particularly to an arbiter circuit having a latch circuit composed of a logic gate circuit.

2. Description of the Related Art When a plurality of independent systems (for example, a multiprocessor system) share a plurality of resources, and each system requests the use of resources asynchronously, two requests arriving at a time difference occur. As for the signal, the permission signal is returned in response to the signal that has arrived first, and for two simultaneously arriving request signals, the permission signal is returned to only one of the two request signals, thereby arbitrating the resource usage. The circuit is called an arbiter circuit.

Conventionally, an arbiter circuit comprises two NOR gates 1 and 2 whose inputs and outputs are cross-coupled to each other, and first and second inverters 3 and 4, as shown in FIG.
The first and second inverters 3 and 4 serve as output buffers, and a cross-coupled NOR gate is an essential element.

[0003] A similar function can be realized by a NAND gate, not by a NOR gate that is cross-coupled. Since this can be described in substantially the same manner as that of the NOR gate, only the arbiter circuit in which the NOR gates are cross-coupled will be described below.

In FIG. 6, an input RX indicates a request signal from the system X, and an input RY indicates a request signal from the system Y. The output AX is a permission signal to the system X, and the output AY is a permission signal to the system Y.

A request from the system is expressed by lowering the level of a request signal. The permission to the system is expressed by setting the permission signal to low level. For example, if (RX, RY) = (L, H), where L indicates a low level and H indicates a high level, the system X
Is sending a request signal. In response to this, the state of the arbiter circuit in FIG. 6 is such that the output (AX, AY) = (L, H), and a permission signal to the system X is returned.

Also, (RX, RY) = (L, H), (A
(X, AY) = (L, H) from (RX, RY) =
(L, L). That is, suppose that Y also issued the request signal after X. At this time, the arbiter circuit is NOR
Since the cross-coupling of the gates performs a latch operation, the output does not change and remains in the state of (AX, AY) = (L, H).

Next, when the request signal from X disappears and (RX, RY) = (H, L), the permission signal to Y is returned only (AX, AY) = (H, L). )
Becomes The above operation is exactly what is required of the arbiter.

However, first, (RX, RY) = (H,
H), RX and RY are simultaneously (L, L)
Is changed to At this time, the internal cross-coupled NO
There is a case where both outputs of the R gate become a so-called metastable state in which the output becomes an intermediate level of “dangling” and becomes stable.

For this reason, both AX and AY are at the L level, and permission to use one resource is issued to the systems X and Y.
Is transmitted to both, and the system may malfunction.

In an actual circuit, due to internal noise or the like, the two outputs of the latch eventually escape from the metastable state and settle to complementary values (the inverted values of each other). However, the time it takes to exit this metastable state is inherently indeterminate, so that the danger of system malfunction is never avoided.

Therefore, when an arbiter circuit is used in the configuration of FIG. 6, it is necessary to take some measures to avoid a malfunction due to the metastable state of the internal latch circuit. Conventionally, as a typical countermeasure, FIG.
The following circuit configuration is known. FIG. 7 is based on the conventional arbiter circuit of FIG. 6 and further includes a circuit for avoiding malfunctions by metastable.

In FIG. 7, the first NOR of the cross-link is shown.
The output of the gate 1 is connected to the source of the first nMOSFET 703 and the gate of the second nMOSFET 704, and the output of the second NOR gate 2 is connected to the first nMOS
It is connected to the gate of the FET 703 and the source of the second nMOSFET 704.

With such a configuration, the first and second n
MOSFETs 703 and 704 are connected to the first NOR gate 1
It does not turn on unless the difference between the output of the second NOR gate 2 and the output of the second NOR gate 2 exceeds the threshold value of the nMOSFET. That is,
Until the difference between the outputs of the two NOR gates 1 and 2 becomes sufficiently large <, the first and second pMOSFETs 705 and 706
Is ON and the output is kept at a high level. Only after exiting the metastable state (only when there is a difference in the output level of NOR), either nMOSFET turns ON
And a low level is output. Therefore, the configuration of FIG. 7 avoids a situation in which the outputs RX and RY both go low.

The arbiter circuit having the configuration shown in FIG. 7 is described in the literature "Introduction to VLSI Systems, Cover Mead, by Lin Conway, lntroduction to VLSI Systems, Ca."
ver Mead and Lynn Conway, Addison-Wesley)
(Japanese translation "Introduction to VLSI system" Sugaya et al.).

[0015]

The conventional arbiter circuit as shown in FIG. 7 requires a total of 12 transistors, and has a drawback that the number of elements is large. The reason is that it is necessary to newly add four transistors to avoid the metastable state.

An object of the present invention is to provide an arbiter circuit that realizes a function of avoiding a malfunction due to a metastable state with a smaller number of elements.

[0017]

According to the present invention, there are provided first and second logic gate circuits having a plurality of transistors of a first conductivity type connected in series between a circuit power supply and an output point. The input and output of the first and second logic gate circuits are cross-connected, and a request signal is supplied to each of the inputs of the first and second logic gate circuits, respectively. An arbiter circuit configured to derive a permission signal corresponding to a request signal from each output of the first and second logic gate circuits, wherein a source is provided at an output point of the first logic gate circuit. A first transistor of a second conductivity type, the drain of which is connected to a series connection point of the transistors of the first logic gate circuit;
Source at the output point of the logic gate circuit of
A second transistor of a second conductivity type having a drain connected to a series connection point of the transistors of the logic gate circuit, wherein the first and second gates and the source are cross-connected to each other; An arbiter circuit characterized in that the permission signal is derived from the drains of the first and second transistors, respectively.

Further, the first and second logic gate circuits are NOR gates, and the first and second logic gate circuits are NAND gates.

In the present invention, the connection of a transistor to the output of an input / output cross-coupled logic gate circuit is the same as that of a conventional arbiter circuit. Of the logic gate circuit. As an example of an arbiter circuit using cross-coupling of NOR gates, the first and second pMOSFs in FIG.
The ETs 705 and 706 have been eliminated, and equivalent functions are instead realized by the pMOSFETs in the first and second NOR gates 1 and 2. Therefore, the number of elements is 2 compared to the conventional configuration.
A smaller number of arbiter circuits can be realized.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the arbiter circuit of the present invention. This figure shows an arbiter circuit in which NOR gates are cross-coupled. In FIG. 1, first and second pMOSFE
T101, 102 and first and second nMOSFET 11
1 and 112 constitute the first NOR gate 1.

The third and fourth pMOSFETs 10
3, 104 and the fourth and fifth nMOSFETs 114, 1
15 constitute the second NOR gate 2. First
The output and the input of the second NOR gate are cross-coupled to each other to form a latch circuit. Then, the second NO MOSFET is added to the gate of the third nMOSFET 113.
The output of the R gate 2 is input.

Further, in the third nMOSFET 113, the series connection point of the series-connected transistors (first and second pMOSFETs 101 and 102) inside the first NOR gate 1 is connected to the drain thereof, The output of NOR gate 1 is connected to its source.

On the other hand, the output of the first NOR gate 1 is supplied to the gate of the sixth nMOSFET 116. Further, the sixth nMOSFET 116 is connected to the second NO
The connection point of the series-connected transistors (the third and fourth pMOSFETs 103 and 104) inside the R gate 2 is connected to its drain, and the output of the second NOR gate 2 is connected to its source.

The input RX indicates a request signal from the system X, and the input RY indicates a request signal from the system Y. The output AX is a permission signal to the system X, and the output AY is a permission signal to the system Y. A request from the system is expressed by making the level of the request signal low. The permission to the system is expressed by setting the permission signal to low level, as in the conventional case.

Next, the operation of the circuit of FIG. 1 will be described with reference to the drawings. First, when both inputs are at the H level (see FIG. 2), the system X and the system Y do not issue a request signal. At this time, the second and fifth nMOSFE
Since T112 and 115 receive the H-level inputs RX and RY and are ON, the first and third pMOSFETs 10 and 115 are turned on.
The gate potentials of the gates 1 and 103 are at the GND level. Therefore, the first and third pMOSFETs 101 and 103 are both turned on.

On the other hand, the second and fourth pMOSFETs 10
2 and 104 are turned off in response to H-level inputs RX and RY
As a result, the pMOSFETs 101 and 103 are pulled up after all, and an H level signal is output from both the first and second outputs AX and AY. (Note that in FIG. 2, transistors that are ON are circled. Enclosed). That is, when there is no request signal from either Sysdem X or Y,
No permission signal to X and Y is generated.

Next, when the first input RX is at the H level and the second input RY is at the L level (see FIG. 3), a request signal is sent from the system Y and no request signal is sent from the system X. is there. At this time, the second nMOSFET 11
2 is turned on in response to the input of the H level, and the third pMOSF
The gate potential of the ET 103 becomes the GND level and turns on. The third pMOSFET is pulled up, and the second output AX goes to H level.

The first and second pMOSFETs 10
1, 102 are OFF, and the third nMOSFET 1
13 is ON. Also, the first and second MOSFETs
111 and 112 are ON. Therefore, the third nMO
Since the signal path from the drain of the SFET 113 to the ground is conductive, the output AY is at the L level (in FIG. 3, the transistors that are ON are circled). That is, when there is a request signal from the system Y and no request signal from the system X, only the permission signal RY to the system Y is returned.

Next, when the first input RX is at the L level and the second input RY is at the H level, since this is essentially the same as the above case, the description is omitted. This corresponds to a case where there is a request signal from the system X and no request signal from the system Y, and only the permission signal RX to the system X is returned.

When both inputs are at the L level (see FIG. 4), this is basically a state in which the previous state is maintained. For example, it is assumed that (RX, RY) = (H, L) and the state is (AX, AY) = (H, L). That is, it is assumed that a request signal is input from the system Y and a permission signal to the system Y is output.

It is assumed that (RX, RY) = (L, L) at the next transition. That is, suppose that the system X also transmitted the request signal after the request signal of the system Y. Even in this case, the state remains (AX, AY) = (H, L). The state at this time is shown in FIG.

First and third nMOSFETs 111 and 11
A3 is pulled down at 3, and AY becomes L level. Also the third
AX is pulled up by the pMOSFET 103
Becomes H level. In FIG. 4, transistors that are ON are circled.

From the above operations, it can be seen that the circuit having the configuration shown in FIG. 1 operates as an arbiter circuit.

Then, the operation for the metastable state will be examined next. First, (RX, RY) = (H, H)
It is assumed that the systems X and Y have issued request signals at the same time.

It should be noted here that the third and sixth nMOS
This is the operation of the FETs 113 and 116. Third nMOSF
As long as a voltage (denoted as Va in the figure) applied between the source and the gate of the ET 113 does not exceed the threshold voltage of the third nMOSFET 113,
Does not turn on. The same is true for nMOSFET 116
Can also be said about. Therefore, the response (AX, AY) = (L, L) is not generated according to the same principle as the conventional arbiter circuit of FIG.

Further, as compared with the configuration of FIG. 7, the total number of transistors can be reduced by two, and an arbiter circuit can be realized with a smaller number of elements than in the prior art.

As described in the section of "Prior Art", an embodiment in which a NAND gate is used as a logic gate to be cross-coupled is shown in FIG. 5 as a second embodiment. The principle is exactly the same as that of the NOR gate.

In FIG. 5, first and second pMOSFETs
501, 502 and first and second nMOSFETs 511,
512 constitute the first NAND gate 5. Also, the fourth and fifth pMOSFETs 504 and 505 and the third and third
The fourth nMOSFETs 513 and 514 and the second NAN
The D gate 6 is constituted.

The third pMOSFET 503 uses the output of the second NAND gate 6 as its gate input, and the first and second nMOSFETs 511 and 51 connected in series.
2 is connected to the drain, and the output of the first NAND gate 5 is connected to the source. Also, the sixth pMO
The SFET 506 uses the output of the first NAND gate 5 as its gate input, and connects the first and second nMOs connected in series.
The connection point of SFETs 513 and 514 is connected to the drain,
The output of the second NAND gate 6 is connected to the source terminal.

It should be noted that the polarity of the input / output is inverted in the case of the NAND gate configuration as compared with the case of the NOR gate configuration. That is, a request from the system is expressed by setting the level of the request signal to high.
The permission to the system is expressed by setting the permission signal to a high level. Then, when two inputs simultaneously transition to the H level from (RX, RY) = (L, L), a metastable state occurs.

To avoid a malfunction caused by this,
According to the same principle as in the case of FIG.
SFETs 503 and 506 are introduced. The operating principle is the same as in the case of the NOR type.

The transistor used is MOSFE
It should be noted that not only T but also a complementary gate formed by another electric switch transistor can be used.

[0044]

According to the present invention, an arbiter circuit can be realized with a smaller number of transistors than in the prior art, so that the layout area can be reduced and an arbiter circuit with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of an arbiter circuit of the present invention.

FIG. 2 is a diagram illustrating an operation when both inputs are at an H level in the arbiter circuit of FIG. 1;

FIG. 3 shows a first input RX in the arbiter circuit of FIG.
FIG. 11 is a diagram showing an operation when the second input RY is at the L level and the second input RY is at the L level.

FIG. 4 is a diagram illustrating an operation when both inputs are at L level in the arbiter circuit of FIG. 1;

FIG. 5 is a diagram showing a second embodiment of the arbiter circuit of the present invention.

FIG. 6 is a diagram illustrating an example of a conventional arbiter circuit.

7 is a diagram showing a circuit example based on the conventional arbiter circuit of FIG. 6 to which a circuit for avoiding malfunction due to metastable has been added.

[Description of Symbols] 1, 2 NOR gate circuits 5, 6 NAND gate circuits 101 to 104 pMOSFETs 113, 116 added in series connection nMOSFETs 503, 506 added pMOSFETs 511 to 514 nMOSFETs connected in series

Claims (3)

(57) [Claims] And a first and second logic gate circuit having a plurality of transistors of a first conductivity type connected in series between a circuit power supply and an output point. The inputs and outputs of the logic gate circuits are cross-connected, and request signals are respectively supplied to the respective inputs of the first and second logic gate circuits. An arbiter circuit configured to be derived from each output of the first and second logic gate circuits, respectively, wherein a source is provided at an output point of the first logic gate circuit, and the source of the arbiter circuit is also the first logic gate circuit. A first transistor of a second conductivity type having a drain connected to a series connection point of the transistor, and a source connected to an output point of the second logic gate circuit, and a series connection of the transistors of the second logic gate circuit. To a point And a second transistor of a second conductivity type to which rain is respectively connected. The first and second gates and the sources are cross-connected to each other, and the drains of the first and second transistors are connected to each other. An arbiter circuit wherein each of the permission signals is derived. 2. The arbiter circuit according to claim 1, wherein said first and second logic gate circuits are NOR gates. 3. The arbiter circuit according to claim 1, wherein said first and second logic gate circuits are NAND gates.