JPS6035851B2 - Set-reset type flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master-slave set-reset flip-flop circuit.

FIG. 1 shows the configuration of a conventional IJ guard set reset type flip-flop circuit.

Of these, FIG. 1a shows a pair of AND gate parts 1,
This is a set-reset type flip-flop circuit which is composed of a pair of OR gate parts 5, 6 and a NAND gate part 2, and operates in synchronization with the rising edge of a clock signal CP. 7 and 8, and is a set-reset type flip-flop circuit that operates in synchronization with the falling edge of the clock signal CP2. FIG. 2 shows a case where the self-triggered set-reset flip-flop circuit described above is constructed using complementary MOS transistors, and FIG. In addition, FIG. 1B shows those that operate in synchronization with the falling edge of the clock signal CP2. Figure 3 shows a conventional set with a 1-bit delay function constructed by connecting the triggered set reset type flip-flop circuits shown in Figure 1 a and b in series and inputting the same signal CK as the clock signal. A reset type flip-flop circuit (hereinafter referred to as an RS flip-flop circuit).

). In the figure, AND gate sections 1, 2 and NOR gate sections 3, 4 constitute a master flip-flop (main flip-flop) 10 which receives set signal S, reset signal R and clock signal CK, and OR gate sections 5, 6 and The NAND gate sections 7 and 8 constitute a slave flip-flop (auxiliary flip-flop) 20 which receives the output signals QM, QM of the master flip-flop 10 and the clock signal CK as inputs. In such an RS flip-flop circuit, when the clock signal CK is logic "1", the slave flip-flop 2
0 is separated from the master flip-flop 10, and the information before the master flip-flop 10 is held by a pair of NAND game sections 7 and 8. At this time, information corresponding to the signals S and R is read in the master flip-flop 10. Next, when the clock signal CK becomes logic “0”,
The master flip-flop is separated from the path of the signals S and R, and holds information read in advance by a pair of NOR gates 3 and 4. Also, at this time, the slave flip-flop occurs. 2 0 is master flip-flop -01
Because of this coupling, the information held in master flip-flop 10 is sent to slave flip-flop 201.

When the clock signal CK returns to logic "1" again, the slave flip-flop 20 retains the information sent from the master flip-flop 10. By the way, in order for the above-mentioned S flip-flop circuit to operate stably without causing malfunction, when the clock signal CK is logic "1" and the master flip-flop 10 reads information according to the signals S and R, In particular, if this information is the same as the previously read information, the signals S and R are
must be a DC-defined signal.

FIG. 4 is a timing chart showing an example of the operation of the RS flip-flop circuit shown in FIG. 3 above. In Fig. 4, first the signal S becomes logic "0", and the signal R becomes logic "''
1”, this circuit enters the reset state and the pair of output signals Q of the master flip-flop 10
M and Qs are each at logic "1", and the pair of output signals QM and Qs of the slave IJ flip-flop 20 are each at logic "0". At this time, even if a thin pulse of logic "0" is mixed into the signal R, this circuit will not malfunction, and the signal Q
The logic levels of M, Qs and signal QM, Qs do not change. Next, signal S becomes logic “1” and signal R becomes logic “0”.
When set respectively, this circuit enters a set state, and when signal CK rises to logic "1", signal QM becomes logic "1".
The signal QM rises and the signal QM falls to logic "0". In the set state, when the signal that once rose to logic "1" falls to logic "0", signal Qs rises to logic "1" and signal Qs falls to logic "0". Furthermore, even if a narrow pulse of logic "0" is mixed into the signal S at this time, this circuit will not malfunction. Also, both signals S and R are logic “0”
When set to , this circuit enters the holding state and the signals QM,
Qs and signals QM, Qs maintain their previous states. This circuit does not malfunction even if a thin pulse of logic "1" is mixed into the signal S in the above-mentioned holding state. However, the signal S,
When a thin pulse of logic "1" is mixed into the signal R as noise when both R are set to logic "0" and a holding operation is performed, the output signals QM, QM of the master flip-flop 10 are inverted. . Once these signals QM and QM are inverted, this state is held by the pair of NOR gate parts 3 and 4, so even if the logic "1" pulse disappears, both signals QM and QM will return to their original state. cannot be reversed, resulting in malfunction. Such malfunctions are likely to occur when the signals S and R are obtained by a data bus method or when they are obtained as time share signals with other signals. This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a highly reliable set-reset type that does not cause malfunctions even when noise is mixed into the input signal. An object of the present invention is to provide a flip-flop circuit.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
FIG. 5 is a block diagram of an embodiment of the present invention, and the same reference numerals are given to the parts corresponding to the conventional one. The AND gate section 1 and the NOR gate section 3 constitute a compound inversion logic circuit (first compound inversion logic circuit) 11, and the AND gate section 2 and the NOR gate section 4 constitute another compound inversion logic circuit (second compound inversion logic circuit). circuit) 12. One of the above composite inversion logic circuits 11 which receives the set signal S and the clock signal CK as inputs.
The output signal QM of the other composite inverting logic circuit 12 is inputted via the AND gate 31 to the NOR gate section 4 of the other composite inverting logic circuit 12 which inputs the reset signal R and the clock signal CK. 32 to the NOR gate section 3 of one of the composite inversion logic circuits 11. That is, the pair of composite inverting logic circuits 11,
12 is a master flip-flop whose input and output ends are cross-coupled so that one output is the input of the other. 10, and AND gates 31, 3 are placed in the middle of the cross-coupling path.
2 are inserted.

The OR gate section 5 and the NAND gate section 7 constitute a composite inversion logic circuit (third composite inversion logic circuit) 21, and the output signal QM and clock signal CK of one of the composite inversion logic circuits 11 of the main flip-flop 10 are inputted. Given. Further, the OR gate section 6 and the NAND gate section 8 constitute another compound inversion logic circuit (fourth compound inversion logic circuit) 22, which combines the output signal QM of the other compound inversion logic circuit 12 of the main flip-flop 10 and the clock signal CK. is given as input. The output signal Qs of the upper compound inversion logic circuit 21 is input to the NAND gate section 8 of the other compound inversion logic circuit 22, and the output signal Qs of the other compound inversion logic circuit 22 is input to the NAND gate section of the other compound inversion logic circuit 21. 7 is input. That is, the input and output terminals of the pair of compound inverting logic circuits 21 and 22 are cross-coupled so that the output of one is the input of the other, thereby forming the slave flip-flop 20. Next, the operation of the circuit configured as described above will be explained.

Figure 6 shows the RS flip-flop circuit (
3 is a timing chart showing an example of the operation of a set/reset type flip-flop circuit. First, as shown in FIG. 6, when the signal S is logic "0" and the signal R is logic "1",
That is, when the clock signal CK becomes logic "1" in the reset state, the output signal of the AND gate section 2 of the mask flip-flop becomes logic "1" and the subsequent output signal of the NOR gate section 4, that is, the signal QM. becomes logic “0”. If the signal QM is a logic "0", the output signal of the AND gate 32 inserted in the middle of the cross-coupling of the master flip-flop 10 also becomes a logic "0". At this time, since the output signal of the AND gate section 1 to which the signal S of logic "0" is input is also logic "0", the NOR gate section 3
The output signal of , that is, the signal QM becomes logic "1". Next, when the clock signal CK becomes logic "0" with the signal S being logic "0" and the signal R being logic "1", the information of the master flip-flop 10 is sent to the slave flip-flop 201, and the OR gate is The output signal of section 5 becomes logic "1" and the output signal of OR gate section 6 becomes logic "0". When the output signal of the OR gate section 6 becomes logic "0", the output signal of the NAND gate section 8 that follows, that is, the signal Qs becomes logic "1".
”.On the other hand, since both the input signals of the NAND gate section 7 become logic "1", the output signal of this NAND gate section 7, that is, the signal Qs becomes logic "0".The clock signal C
When K is logic “0”, the master flip-flop 10
The output signals of one AND gate section 1, 2 are the signals S, R
However, since the output signal Qs of the slave flip-flop 20 is logic "0" and Qs is logic "1", the master flip-flop 10
The output signal QM remains at logic "1", and QM remains at logic "0". Next, signal S is logic “1” and signal R is logic “0”
Then, when the clock signal CK becomes logic "1", the output signal of the AND gate section 1 of the master flip-flop 10 becomes logic "1", and the subsequent output signal of the NOR gate section 3, that is, the signal QM becomes logic "1". becomes 0”.

If the signal QM is a logic "0", the output signal of the AND gate 31 inserted in the cross-coupling of the master flip-flop 10 also becomes a logic "0". At this time, logic “0”
Since the output signal of the band gate section 2 to which the signal R of `` is input is also logic "0", the output signal of the NOR gate section 4, that is, the signal QM becomes logic "1". Next, the signal S
When the clock signal CK becomes a logic "0" while the signal R is a logic "1" and the signal R is a logic "0", the information in the master flip-flop 10 is sent to the two slave flip-flops and the OR gate is output. The output signal of section 5 becomes logic "0" and the output signal of OR gate section 6 becomes logic "1". When the output signal of the OR gate section 5 becomes logic "0", the output signal of the NAND gate section 7, that is, the signal Qs, becomes logic "1".
On the other hand, since both input signals of the NAND gate section 8 become logic "1", the output signal Qs of this NAND gate section 8 becomes logic "0". When the clock signal CK is logic "10", the output signals of the two AND gates 1 and 2 of the master flip-flop 10 are logic "0" regardless of the signals S and R.
”, but since the output signal Qs of the slave flip-flop 20 is a logic “1” and Qs is a logic “0”, the output signal QM of the master flip-flop 10 is a logic “1”.
1”, QM remains logic “0”. Then the signals S, R
When both become logic "0", the output signals of the two AND gate sections 1 and 2 of master flip-flop 10 both become logic "0", regardless of the clock signal CK. At this time, if the signal Qs is logic "1" and Qs is logic "0", the output signal of the AND gate 31 becomes logic "0", and the subsequent output signal of the NOR gate section 4, that is, the signal QM becomes logic "1". become. Further, when the signal QM becomes a logic "1", the output signal of the AND gate 32 becomes a logic "1", and the subsequent output signal of the NOR gate section 3, that is, the signal QM becomes a logic "0". Therefore, in this case, the clock signal C
When K becomes logic "0", signal Qs becomes logic "1" in the same way as when the signal S is logic "1" and the signal R is logic "0".
, the signal Qs becomes logic "0". In this manner, this circuit operates as a set-reset type flip-flop circuit in the same way as the conventional circuit. Next, the clock signal CK is now logic “1”.
”, both signals S and R are set to logic “0”, and this R
Let us consider the state when the S flip-flop circuit is performing a holding operation.

At this time, it is assumed that signals QM and Qs are set to logic "1" and signals QM and Qs are set to logic "0", respectively, as shown in FIG. If a narrow pulse of logic "1" is mixed into the signal R in this state, the output signal of the AND gate section 2 is inverted to logic "1". When the output signal of the AND gate section 2 becomes logic "1", the subsequent output signal QM of the NOR gate section 4 is inverted to logic "0". As a result, the output signal of the AND gate 32 becomes logic "0".
At this time, the output signal of the AND gate section 1 is logic "0", so when the output signal of the AND gate 32 becomes logic "0", the output signal QM of the AND gate section 3 becomes "0". The logic is inverted to “1”.Then, the above QM=
The state of "0" and QM="1" continues during the period when R is at logic "1". However, when the signal R returns to logic "0" again during the period when CK="1", the signal R returns to logic "1" until now.
”, the output signal of the AND gate section 2 becomes logic “0” again.
”. When the output signal of the AND gate unit 2 returns to logic “0”, the output signal QM of the NOR gate unit 4 returns to logic “1”.
”. When the signal QM becomes logic “1”, the output signal of the AND gate 32 also becomes logic “1”, so the output signal QM of the NOR gate section 3 becomes logic “0” again. Therefore, after this, Even if CK becomes logic "0", the same information is sent to the slave flip-flop 201 as before signal R becomes logic "1", so signals Qs and Qs become logic "1".
1” and is held as logic “0”.Furthermore, S=R=“
0" and CK="1", even if a thin pulse of logic "1" is mixed into S, it goes without saying that Qs and Qs are held at the same logic as before the pulse was mixed, as described above. Also, as in the past, when CK="1", S="0" and R="1"
Needless to say, when CK="1", S="1", and R="0", no malfunction will occur even if a thin pulse is mixed into S or R. In this way, according to the above embodiment, the operation of the slave flip-flop 20 is determined only by the states of the signals S and R at the falling edge of the clock signal CK, and the signal S or R is not activated during the period when CK is logic "1". Even if noise is mixed in, the pair of output signals QM, QM of the master flip-flop 10 will return to their original logic once the noise disappears, and will not malfunction. Therefore this RS
Flip-flop circuits become extremely reliable. FIG. 7 shows a complementary MO circuit of the embodiment shown in FIG. 5 above.
It is a circuit diagram when configured with S transistors,
The symbols in the figure correspond to those in FIG.

Also, compared to the case where the conventional circuit shown in FIG. 3 is constructed using MOS transistors, two P-channel MO
S transistors P1, P2 and two N-channel MOs
Only a total of four MOS transistors, S transistors N1 and N2, are increased. FIG. 8 shows another embodiment of the present invention, in which the circuit of the embodiment shown in FIG. 5 is provided with direct set and direct reset functions.

Therefore, the NOR gate section 3 of one compound inversion logic circuit 11 of the master flip-flop 10 is replaced with an OR gate section 41 and a NAND gate section 42 connected in series as shown in the figure. 1 and the output signal of AND gate 32 are input. Further, the direct reset signal D·R is inputted to the logic section located at the final stage of the composite inversion logic circuit 11, that is, the NAND gate section 42, together with the output signal of the OR gate 41. Similarly, master flip-flop 1
The NOR gate section 4 of the other complex inversion logic circuit 12 of 0
is also replaced with an OR gate section 43 and a NAND gate section 44 connected in series as shown, and the output signals of the AND gate section 2 and AND gate 31 are input to this OR gate section 43. In addition, the composite inversion logic circuit 12
The direct set signal D·S is inputted together with the output signal of the OR gate 43 to the logic section located at the final stage, that is, the NAND gate section 44 . Also, a pair of complex inverting logic circuits 21, 2 of the slave flip-flop 20
The NAND gate sections 7 and 8 located at the final stage of the second NAND gate section 2 are replaced with three-input type NAND gate sections 7' and 8', respectively, and one input terminal of one of the NAND gate sections 7' is connected to the direct set terminal. The signals D and S are input to one input terminal of the other NAND gate section 8', and the direct reset signals D and R are input, respectively. In such a configuration, the direct reset signal D which is now logic “0”
・If R is input, signal QM is input regardless of other signals.
, Qs are forced to logic "1", and signals QM, Qs are forced to logic "0".

Moreover, if the direct set signal D・S of logic "0" is input, the signals QM, Qs become logic "1", and the signals QM, Qs become logic "1".
Qs are respectively forced to logic "0". 9th
This figure is a circuit diagram in which the embodiment circuit shown in FIG. 8 is constructed using complementary MOS transistors, and the reference numerals in the figure correspond to those in FIG.

Also, compared to the case where the conventional circuit shown in FIG. 3 is constructed using MOS transistors, six P-channel M
OS transistors PI to P6 and six N-channel M
Only a total of 12 MOS transistors, including OS transistors NI to N6, are increased. Note that among these, the N-channel transistors N3 and N4 or N5 and N6 can be omitted by using either one in common. In the embodiment circuits shown in FIGS. 8 and 9, a case has been described in which both a direct set signal and a direct reset signal are provided, but only one of them may be provided.

Furthermore, the present invention is not limited to the above embodiments, but
For example, in the above embodiment, depending on the states of the signals S and R at the falling edge of the clock signal CK, the slave flip-flop 2
Although the case where the operation of 0 is determined has been described, the operation may be determined by the states of the signals S and R at the rising edge of the clock signal CK. As described above, according to the present invention, it is possible to provide a highly reliable set-reset type flip-flop circuit that does not malfunction even when noise is mixed into the input signal.

[Brief explanation of the drawing]

Figures 1a and b are block diagrams of conventional triggered set-reset flip-flop circuits, and Figures 2a and b are circuit diagrams in which the triggered set-reset flip-flop circuits are realized using MOS transistors, respectively.
FIG. 3 is a conventional set-reset type flip-flop circuit, FIG. 4 is a timing chart showing an example of the operation of the conventional circuit shown in FIG. 3, FIG. 5 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is a timing chart showing an example of the operation of the above embodiment circuit, FIG. 7 is a circuit diagram in which the above embodiment circuit is realized by MOS transistors, FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. The embodiment circuit of FIG. 8 above is M
FIG. 2 is a circuit diagram realized by OS transistors. 10... Master flip-flop, 20... Slave flip-flop, 1, 2... AND gate section, 3, 4...
...Nor gate part, 5,6,41,43...Or gate part, T,7',8,8',42,44...NAND gate part, 31,32...And gate, 11,12,21,2
2...Composite inversion logic circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. A first AND circuit to which a set signal and a clock signal are supplied, a first NOR circuit to which the output of the first AND circuit is supplied as one of its two inputs, a reset signal, and the above. a second AND circuit to which a clock signal is supplied; a second NOR circuit to which the output of the second AND circuit is supplied as one of its two inputs; and an output of the second NOR circuit as one of its two inputs. a third AND circuit, whose output is supplied to the first NOR circuit as the remaining input; the output of the first NOR circuit is supplied as one of the two inputs, and the output is supplied to the second NOR circuit; a main flip-flop consisting of a fourth AND circuit which is supplied as the remaining input to the NOR circuit; a first OR circuit which is supplied with the output of the first NOR circuit and the clock signal; a second OR circuit to which an output and said clock signal are supplied; a first NAND circuit to which the output of said first OR circuit is supplied as one of its two inputs; and said second OR circuit as one of its two inputs. a second NAND circuit to which the output of the circuit is supplied; means for supplying the output of the second NAND circuit as a remaining input of the first NAND circuit; an auxiliary flip-flop comprising means for supplying the output of the first NAND circuit as the remaining input of the third AND circuit; and means for supplying the output of the first NAND circuit as the remaining input of the third AND circuit; A set-reset type flip-flop circuit comprising means for supplying the output of the second NAND circuit as an input. 2. A direct reset signal is further supplied to each of the first NOR circuit and the second NAND circuit, and the output states of the main flip-flop and the auxiliary flip-flop are set by the direct reset signal. The set-reset type flip-flop circuit described in . 3. A direct set signal is further supplied to each of the second NOR circuit and the first NAND circuit, and the output states of the main flip-flop and the auxiliary flip-flop are set by the direct set signal. The set-reset type flip-flop circuit described in . 4 A direct reset signal is further supplied to each of the first NOR circuit and the second NAND circuit, and a direct set signal is further supplied to each of the second NOR circuit and the first NAND circuit, and these 2. A set-reset type flip-flop circuit according to claim 1, wherein the output states of said main flip-flop and said auxiliary flip-flop are set by a direct reset signal and a direct set signal.