JPS6070817A - Logical circuit - Google Patents

Abstract

PURPOSE:To give priority to an input signal of an FF over a clock signal by providing a switch MOSFET so as not to form a current path turned on/off complementarily with the MOSFET and connected directly to a power supply or ground. CONSTITUTION:P-channel switch MOS transistor (TR) TR2 and an N-channel switch MOSTR4 are provided in pairs with an N-channel MOSTR (NMOS)TR1 for set and a PMOSTR3 for reset. The TR2, TR4 are connected respectively in series between a data input MOS 4 and a power supply VDD and between MOS5 and ground. The MOSTR2, TR4 are turned on/off complementarily with the MOSTR1, TR3 by a set signal and a reset signal. A through-current is prevented by the switch MOSTR2, TR4 and the set and reset operation is guaranteed independently of the state of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit such as a flip-flop composed of CMO8 circuits, and in particular, to a logic circuit such as a flip-flop that is configured with a CMO8 circuit, and in particular to a logic circuit that ensures priority of an asynchronous forced input signal such as set or reset with respect to a data latch clock. 5 relates to the logic circuit.

Flip of conventional CMOS (complementary MO8) logic circuit
For example, the flop is 1 [J! A type that logically guarantees a set or reset function within a flip-flop circuit for clock input, such as a+, and a type shown in FIG.
There is a type that uses a tiger/sphere gate 3 to simplify the circuit. Figure 1 1al '7) Since the circuit has a large number of elements, it is not suitable for large-scale integrated circuits. On the other hand, the first
The circuit in Figure 1al has a small number of elements (suitable for large-scale integrated circuits, but for level triggering, the cent or reset signal must be synchronized with the clock signal to ensure isolation).
At the time of reset or reset, a path such as i or 12 in the figure through which a through current flows is formed, and the potential of node (2) becomes unstable, making it impossible to expect normal logic operation of the flip-flop. Also, through current 11. If +2 continues to flow, the reliability of the device will be affected (on the other hand).

If an attempt is made to ensure exclusion by synchronizing the set/reset signal with a clock signal, problems arise in that the logic design for this purpose becomes complicated and the overall O performance deteriorates.

The present invention provides a through-flow m flow 1. Another object of the present invention is to provide a 51C circuit that can prevent I2, and to ensure that a Frino pull-up set or reset signal using a transfer gate has priority over a clock signal.

By the way, in the circuit configuration of FIG. 1 181, the through current i and 1. If this can be prevented, the number of elements in one circuit can be reduced,
It has the advantage of being a flip-flop suitable for large-scale integrated circuits. On the other hand, the through current i.

(i,) occurs when the reset signal and the clock signal are applied simultaneously and the data signal is at the "L"("H") level. Therefore, in order to prevent the through current 11 (+2), it is sufficient to provide a switch that cuts off the path through which the through current flows in response to a cent (reset) signal.

The present invention has been made from this point of view.

Hereinafter, one embodiment of the present invention will be described based on FIG. 2.

Figure 1 (through current 'III flowing in the circuit of bl)
! In order to prevent this, in this embodiment, a P-type switch MO8) is used in pair with an N-channel type MOS transistor Tr8 for setting and a P-channel type MOS transistor Tr8 for resetting. A Tr2 and an N-type switch MOS transistor Tr4 are provided, respectively. This MO8+ transistor T and Tr4
are connected in series between the data MOs 4 and 5 and the power supply voltage VD or ground potential, respectively.

The MOS transistors Tr2 and Tr4 are turned on and off in a complementary manner to the MOS transistors Trl and Tr11 based on the cent signal and reset signal example.

Therefore, the path through which the through current 'I+'2 was flowing in the circuit shown in FIG.
2" T4.

As a result, in the circuit of this embodiment, a through current is prevented, and the node ■' becomes stably at the "L" level or "H'" level regardless of the state of the clock signal, and set and reset operations are guaranteed. .

Note 1: In the case of normal data input, the set signal is “L”
level, and the reset signal is set to the "H11 level," so the MOS transistors Tr2 and Tr4 are turned on. As a result, the data input transistors 4 and 5 are connected to the power supply and ground, respectively. There is no problem when inputting data.In this way, by adding the transistors Tr2 and Tr4, priority can be guaranteed for the set signal and reset signal over the clock signal.

In Figure 1, Ia to IC are CMOS inverters,
2 is a CMQS inverter for latch feedback.

As explained above, according to the present invention, the through current i1. +2 can be prevented, so
Stable circuit operation of flip-flops can be guaranteed. Therefore, priority can be guaranteed for the clock signal of the cent signal and reset signal, which are input signals of the flip-flop, within the flip-flop circuit. Further, since priority is guaranteed for set and reset, the set signal and reset signal can be handled asynchronously with respect to the clock signal, making logic design easier. moreover.

The flip-flop of the present invention, which has the same logic function as the circuit shown in Figure 1, has an overwhelmingly smaller number of elements than the 181 shown in Figure 1, so it occupies less space for two circuits and is suitable for highly integrated logic circuits. It has advantages.

In the above embodiment, a D flip-flop was explained as an example, but the present invention is applicable to other types of flip-flops.
It can also be applied to logic circuits other than flops, flips, and fronts.

[Brief explanation of the drawing]

181 is a circuit diagram showing an example of a conventional flip-flop logic circuit, FIG. 1 1b+ is a circuit diagram showing an example of a flip-flop simplified using a transfer gate, and FIG. 2 is a circuit diagram showing an example of a flip-flop according to the present invention. FIG. 2 is a circuit illustrating a flip-flop as an example of logic circuit related to FIG. Trl...Set MOS Tr/Jista k Tr2.
...Switch MOS transistor, Tr8...Reset MO8) transistor' T14...Switch MO
8) transistor, 3...transfer gate, 4. Death: MO8) transistor for data input. Continued from page 1 0 Author: Katsuharu Horiguchi, 3-chome, Midori-cho, Musashino City, Air Communication Research Institute, 0 author: Ryota Kasai, Midori-cho, Musashino City, 3-chome, Air Communications Research Institute, 0 author: Hiroshi Yoshimura, 3 Midori-cho, Musashino City Inside the Chome Air Communication Research Institute

Claims (1)

[Claims] 1. In a complementary MO8 circuit consisting of a P-channel type MQS transistor and an N-channel type MOS transistor, a MOS that receives a signal that forcibly fixes the logic level of a configuration that has the function of constantly maintaining a certain logic level)
The transistor is characterized by being provided with a switch MO8) which is turned on and off in a complementary manner to the transistor MO8) to prevent the formation of a current path directly connected to the power supply or ground. logic circuit.