JP3672184B2 - Macro cell for relay - Google Patents

Description

【００９６】
したがって、入力信号ＶＯＦＦが“Ｈ”レベルの場合、本実施形態はレベルシフト回路として動作する。
【００９７】
よって、本実施形態は、レベルシフト機能のあるトライステートゲートとして働き、ＶＤＤ１を切っても出力信号には影響がない。また、ＶＤＤ１を切った場合に、不安定となる入力信号Ａおよびその反転信号を遮断できるので、スタティックリーク電流が流れない。また、意図的に電源電圧に差を持たせている場合はもとより、同一電圧を供給する電源の系統間での電圧にズレが生じた場合でも、スタティックリーク電流の増加を防ぐことができる。
（第６の実施の形態）
図６は、第６の実施形態における中継用マクロセルの回路図である。これは、レベルシフト機能のあるラッチ２個とクロックド・インバータを組み合わせた構成になっている。ＶＤＤ１（第３の電位）とＧＮＤ（第２の電位）間に入力信号Ａ（第１の入力信号）が供給されるインバータＩＮ１とイネーブル信号Ｅ（第３の入力信号）が供給されるインバータＩＮ２と、ＶＤＤ２（第１の電位）とＧＮＤ間に入力信号ＶＯＦＦ（第２の入力信号）が供給されるインバータＩＮ３と、これら信号とその反転信号により制御される２つのラッチと、このラッチの出力信号により制御されるクロックド・インバータから構成されている。入力信号Ａ、イネーブル信号Ｅとこれらの反転信号はＶＤＤ１の電源系統に含まれ、入力信号ＶＯＦＦとその反転信号および出力信号ＺはＶＤＤ２の電源系統に含まれている。
【００９８】
第１のラッチ（第１のレベルシフト回路、第１の保持回路）は、入力信号Ａに応じた信号を出力する。ＮＭＯＳトランジスタＭＮ６０６（第１のＭＯＳトランジスタ）は、ソースがＧＮＤに接続され、ゲートに入力信号ＶＯＦＦが供給されている。ＮＭＯＳトランジスタＭＮ６０４（第３のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ６０６のドレインに接続され、ゲートに入力信号Ａが供給されている。ＮＭＯＳトランジスタＭＮ６０５（第４のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ６０６のドレインに接続され、ゲートにインバータＩＮ１（ＮＭＯＳトランジスタＭＮ６０１，ＰＭＯＳトランジスタＭＰ６０１）を介した入力信号Ａの反転信号が供給されている。また、ＰＭＯＳトランジスタＭＰ６０４（第５のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ６０４のドレインに接続されている。ＰＭＯＳトランジスタＭＰ６０５（第６のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ６０５のドレインに接続されている。そして、ＰＭＯＳトランジスタＭＰ６０４のゲートが、ＰＭＯＳトランジスタＭＰ６０５とＮＭＯＳトランジスタＭＮ６０５のドレインに接続され、ＰＭＯＳトランジスタＭＰ６０５のゲートが、ＰＭＯＳトランジスタＭＰ６０４とＮＭＯＳトランジスタＭＮ６０４のドレインに接続されている。
【００９９】
また、ＮＭＯＳトランジスタＭＮ６０９（第２のＭＯＳトランジスタ）は、ソースがＧＮＤに接続され、ゲートにインバータＩＮ３（ＮＭＯＳトランジスタＭＮ６０３，ＰＭＯＳトランジスタＭＰ６０３）を介した入力信号ＶＯＦＦの反転信号が供給されている。ＮＭＯＳトランジスタＭＮ６０７（第７のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ６０９のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ６０４とＮＭＯＳトランジスタＭＮ６０４のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ６０５とＮＭＯＳトランジスタＭＮ６０５のドレインに接続されている。ＮＭＯＳトランジスタＭＮ６０８（第８のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ６０９のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ６０５とＮＭＯＳトランジスタＭＮ６０５のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ６０４とＮＭＯＳトランジスタＭＮ６０４のドレインに接続されている。
【０１００】
そして、ＰＭＯＳトランジスタＭＰ６０５とＮＭＯＳトランジスタＭＮ６０５，ＭＮ６０８のドレイン電圧が第１のラッチの出力信号として、後段のクロックド・インバータに出力される。
【０１０１】
第２のラッチは、イネーブル信号Ｅに応じた信号を出力する。ＮＭＯＳトランジスタＭＮ６１２は、ソースがＧＮＤに接続され、ゲートに入力信号ＶＯＦＦが供給されている。ＮＭＯＳトランジスタＭＮ６１０は、ソースがＮＭＯＳトランジスタＭＮ６１２のドレインに接続され、ゲートにイネーブル信号Ｅが供給されている。ＮＭＯＳトランジスタＭＮ６１１は、ソースがＮＭＯＳトランジスタＭＮ６１２のドレインに接続され、ゲートにインバータＩＮ２（ＮＭＯＳトランジスタＭＮ６０２，ＰＭＯＳトランジスタＭＰ６０２）を介したイネーブル信号Ｅの反転信号が供給されている。
【０１０２】
また、ＰＭＯＳトランジスタＭＰ６１０は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ６１０のドレインに接続されている。ＰＭＯＳトランジスタＭＰ６１１は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ６１１のドレインに接続されている。そして、ＰＭＯＳトランジスタＭＰ６１０のゲートが、ＰＭＯＳトランジスタＭＰ６１１とＮＭＯＳトランジスタＭＮ６１１のドレインに接続され、ＰＭＯＳトランジスタＭＰ６１１のゲートが、ＰＭＯＳトランジスタＭＰ６１０とＮＭＯＳトランジスタＭＮ６１０のドレインに接続されている。
【０１０３】
また、ＮＭＯＳトランジスタＭＮ６１５は、ソースがＧＮＤに接続され、ゲートにインバータＩＮ３を介した入力信号ＶＯＦＦの反転信号が供給されている。ＮＭＯＳトランジスタＭＮ６１３は、ソースがＮＭＯＳトランジスタＭＮ６１５のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ６１０とＮＭＯＳトランジスタＭＮ６１０のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ６１１とＮＭＯＳトランジスタＭＮ６１１のドレインに接続されている。ＮＭＯＳトランジスタＭＮ６１４は、ソースがＮＭＯＳトランジスタＭＮ６１５のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ６１１とＮＭＯＳトランジスタＭＮ６１１のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ６１０とＮＭＯＳトランジスタＭＮ６１０のドレインに接続されている。
【０１０４】
そして、第２のラッチの出力信号として、ＰＭＯＳトランジスタＭＰ６１１とＮＭＯＳトランジスタＭＮ６１１，ＭＮ６１４のドレイン電圧が、後段のクロックド・インバータに出力される。また、第２のラッチの出力信号の反転信号として、ＰＭＯＳトランジスタＭＰ６１０とＮＭＯＳトランジスタＭＮ６１０，ＭＮ６１３のドレイン電圧が、後段のクロックド・インバータに出力される。
【０１０５】
クロックド・インバータについて説明する。ＶＤＤ２とＧＮＤ間に、ＰＭＯＳトランジスタＭＰ６１６，ＭＰ６１７とＮＭＯＳトランジスタＭＰ６１６，ＭＮ６１７が直列接続されている。ＰＭＯＳトランジスタＭＰ６１７は、ソースがＶＤＤ２に接続され、ゲートに第２のラッチからの出力信号の反転信号が供給されている。ＮＭＯＳトランジスタＭＮ６１７は、ソースがＧＮＤに接続され、ゲートに第２のラッチからの出力信号が供給されている。また、ＰＭＯＳトランジスタＭＰ６１６は、ソースがＰＭＯＳトランジスタＭＰ６１７のドレインに接続され、ゲートに第１のラッチからの出力信号が供給されている。ＮＭＯＳトランジスタＭＮ６１６は、ソースがＮＭＯＳトランジスタＭＮ６１７のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ６１６のドレインに接続され、ゲートに第１のラッチから出力信号が供給されている。そして、出力信号Ｚとして、ＰＭＯＳトランジスタＭＰ６１６とＮＭＯＳトランジスタＭＮ６１６のドレイン電圧が出力される。
【０１０６】
次に、本実施形態の動作について説明する。入力信号ＶＯＦＦに“Ｈ”レベルが入力されている場合、入力信号Ａおよびイネーブル信号Ｅの信号レベルを変換して出力信号Ｚに信号を出力するレベルシフト回路として動作する。入力信号ＶＯＦＦが“Ｈ”レベルなので、ＮＭＯＳトランジスタＭＮ６０６とＮＭＯＳトランジスタＭＮ６１２はオン状態となり、ＮＭＯＳトランジスタＭＮ６０９とＮＭＯＳトランジスタＭＮ６１５はオフ状態となる。
【０１０７】
入力信号Ａが“Ｈ”レベルの場合を考える。第１のラッチのＮＭＯＳトランジスタＭＮ６０４はオン状態となり、ＮＭＯＳトランジスタＭＮ６０５はオフ状態となる。したがって、ＮＭＯＳトランジスタＭＮ６０４のドレイン電圧はＧＮＤレベルとなる。そして、ＰＭＯＳトランジスタＭＰ６０５のゲートにはＧＮＤレベル（“Ｌ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ６０５はオン状態となる。すると、ＰＭＯＳトランジスタＭＰ６０５のドレイン電圧はＶＤＤ２レベルとなり、第１のラッチの出力信号として、次段のクロックド・インバータに出力される。また、ＰＭＯＳトランジスタＭＰ６０４のゲートにＶＤＤ２レベル（“Ｈ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ６０４はオフ状態となる。
【０１０８】
イネーブル信号Ｅが“Ｈ”レベルの場合、第２のラッチでも同様に動作し、第２のラッチの出力信号としてＶＤＤ２レベル（“Ｈ”レベル）の信号が、出力信号の反転信号としてＧＮＤレベル（“Ｌ”レベル）の信号が、次段のクロックド・インバータに供給される。
【０１０９】
この時、クロックド・インバータは、ＮＭＯＳトランジスタＭＮ６１６，ＭＮ６１７がオン状態となるので、出力信号ＺとしてＧＮＤレベル（“Ｌ”レベル）の信号が出力される。
【０１１０】
入力信号Ａが“Ｌ”レベルの場合を考える。ＮＭＯＳトランジスタＭＮ６０４はオフ状態、ＮＭＯＳトランジスタＭＮ６０５はオン状態となる。したがって、ＮＭＯＳトランジスタＭＮ６０５のドレイン電圧はＧＮＤレベルとなり、次段のクロックド・インバータに出力される。そして、ＰＭＯＳトランジスタＭＰ６０４のゲートにＧＮＤレベル（“Ｌ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ６０４はオン状態となる。すると、ＰＭＯＳトランジスタＭＰ６０４のドレイン電圧はＶＤＤ２レベルとなり、ＰＭＯＳトランジスタＭＰ６０５のゲートにＶＤＤ２レベル（“Ｈ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ６０５はオフ状態となる。
【０１１１】
この時、クロックド・インバータは、ＰＭＯＳトランジスタＭＰ６１６，ＭＰ６１７がオン状態となるので、出力信号ＺとしてＶＤＤ２レベル（“Ｈ”レベル）の信号が出力される。
【０１１２】
イネーブル信号Ｅが“Ｌ”レベルの場合、第２のラッチから、出力信号としてＧＮＤレベル（“Ｌ”レベル）の信号が、出力信号の反転信号としてＶＤＤ２レベル（“Ｈ”レベル）の信号が、次段のクロックド・インバータに供給される。
【０１１３】
この時、クロックド・インバータは、ＰＭＯＳトランジスタＭＰ６１７とＮＭＯＳトランジスタＭＮ６１７は共にオフ状態となるので、出力信号Ｚとしてハイインピーダンスの信号が出力される。
【０１１４】
一方、入力信号ＶＯＦＦに“Ｌ”レベルが入力されている場合、ＮＭＯＳトランジスタＭＮ６０６，ＭＮ６１２はオフ状態、ＮＭＯＳトランジスタＭＮ６０９，ＭＮ６１５はオン状態となる。第１のラッチおよび第２のラッチは、入力信号ＶＯＦＦに“Ｈ”レベルが入力されていた時の入力信号Ａ，イネーブル信号Ｅに応じた信号を保持しているので、ＶＤＤ１を切っても出力信号Ｚは“Ｈ”レベル（ＶＤＤ２レベル）、“Ｌ”レベル（ＧＮＤレベル）、または、ハイインピーダンスを出力し続ける。
【０１１５】
以下に、第６の実施形態における真理値表を表２に示す。表２中の“Ｘ”は、“Ｈ”または“Ｌ”である。
【０１１６】
【表２】

【０１１７】
入力信号ＶＯＦＦが“Ｌ”レベルの時に、ＶＤＤ１を切ったとすると、入力信号Ａ、イネーブル信号Ｅおよびこれらの反転信号は不安定な状態となる。しかし、ＮＭＯＳトランジスタＭＮ６０６，ＭＮ６１２はオフ状態となっているので、ＶＤＤ２からＧＮＤにスタティックリーク電流は流れない。また、ＶＤＤ１を切った場合でも、第１および第２のラッチは保持した信号を出力し続けるので、これら２つのラッチの出力信号やその反転信号に影響はない。
【０１１８】
よって、本実施形態は、レベルシフト機能のあるクロックド・インバータとして働き、ＶＤＤ１を切っても出力信号には影響がない。また、ＶＤＤ１を切った場合に、不安定となる入力信号Ａ、イネーブル信号Ｅおよびこれらの反転信号を遮断できるので、スタティックリーク電流が流れない。また、意図的に電源電圧に差を持たせている場合はもとより、同一電圧を供給する電源の系統間での電圧にズレが生じた場合でも、スタティックリーク電流の増加を防ぐことができる。（第７の実施の形態）
図７は、第７の実施形態における中継用マクロセルの回路図である。これは、レベルシフト機能のあるラッチ２個を有するトライステートゲートになっている。ＶＤＤ１（第３の電位）とＧＮＤ（第２の電位）間に入力信号Ａ（第１の入力信号）が供給されるインバータＩＮ１と、イネーブル信号Ｅ（第２の入力信号）が供給されるインバータＩＮ２と、ＶＤＤ２（第１の電位）とＧＮＤ間に入力信号ＶＯＦＦ（第３の入力信号）が供給されるインバータＩＮ３と、これら入力信号とその反転信号により制御される２つのラッチと、このラッチの出力信号により制御される２つのＭＯＳトランジスタから構成されている。入力信号Ａ，Ｅとこれらの反転信号はＶＤＤ１の電源系統に含まれ、入力信号ＶＯＦＦとその反転信号および２個のラッチと出力信号ＺはＶＤＤ２の電源系統に含まれている。
【０１１９】
第１のラッチ（第１のレベルシフト回路、第１の保持回路）について説明する。ＮＭＯＳトランジスタＭＮ７０８（第１のスイッチ素子）は、ソースがＧＮＤに接続され、ゲートに入力信号ＶＯＦＦが供給されている。ＮＭＯＳトランジスタＭＮ７０４（第３のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７０８のドレインに接続され、ゲートにインバータＩＮ１（ＮＭＯＳトランジスタＭＮ７０１，ＰＭＯＳトランジスタＭＰ７０１）を介した入力信号Ａの反転信号が供給されている。ＮＭＯＳトランジスタＭＮ７０５（第４のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７０８のドレインに接続され、ドレインがＮＭＯＳトランジスタＭＮ７０４のドレインに接続され、ゲートにインバータＩＮ２（ＮＭＯＳトランジスタＭＮ７０２，ＰＭＯＳトランジスタＭＰ７０２）を介したイネーブル信号Ｅの反転信号が供給されている。
【０１２０】
また、ＮＭＯＳトランジスタＭＮ７０７（第５のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７０８のドレインに接続され、ゲートにイネーブル信号Ｅが供給されている。ＮＭＯＳトランジスタＭＮ７０６（第６のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７０７のドレインに接続され、ゲートに入力信号Ａが供給されている。
【０１２１】
ＰＭＯＳトランジスタＭＰ７０４（第７のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５のドレインに接続されている。ＰＭＯＳトランジスタＭＰ７０６（第８のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ７０６のドレインに接続されている。そして、ＰＭＯＳトランジスタＭＰ７０４のゲートが、ＰＭＯＳトランジスタＭＰ７０６とＮＭＯＳトランジスタＭＮ７０６のドレインに接続され、ＰＭＯＳトランジスタＭＰ７０６のゲートが、ＰＭＯＳトランジスタＭＰ７０４とＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５のドレインに接続されている。
【０１２２】
また、ＮＭＯＳトランジスタＭＮ７１１（第３のスイッチ素子）は、ソースがＧＮＤに接続され、ゲートにインバータＩＮ３（ＮＭＯＳトランジスタＭＮ７０３，ＰＭＯＳトランジスタＭＰ７０３）を介した入力信号ＶＯＦＦの反転信号が供給されている。ＮＭＯＳトランジスタＭＮ７０９（第９のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１１のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ７０４とＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ７０６とＮＭＯＳトランジスタＭＮ７０６のドレインに接続されている。ＮＭＯＳトランジスタＭＮ７１０（第１０のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１１のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ７０６とＮＭＯＳトランジスタＭＮ７０６のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ７０４とＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５のドレインに接続されている。
【０１２３】
そして、第１のラッチの出力信号として、ＰＭＯＳトランジスタＭＰ７０６とＮＭＯＳトランジスタＭＮ７０６，ＭＮ７１０のドレイン電圧が次段に出力される。
【０１２４】
次に、第２のラッチ（第２のレベルシフト回路、第２の保持回路）について説明する。ＮＭＯＳトランジスタＭＮ７１６（第２のスイッチ素子）は、ソースがＧＮＤに接続され、ゲートに入力信号ＶＯＦＦが供給されている。ＮＭＯＳトランジスタＭＮ７１３（第１１のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１６のドレインに接続され、ゲートにイネーブル信号Ｅが供給されている。ＮＭＯＳトランジスタＭＮ７１２（第１２のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１３のドレインに接続され、ゲートにインバータＩＮ１を介した入力信号Ａの反転信号が供給されている。
【０１２５】
また、ＮＭＯＳトランジスタＭＮ７１４（第１３のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１６のドレインに接続され、ゲートに入力信号Ａが供給されている。ＮＭＯＳトランジスタＭＮ７１５（第１４のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１６のドレインに接続され、ドレインがＮＭＯＳトランジスタＭＮ７１４のドレインに接続され、ゲートにインバータＩＮ２を介したイネーブル信号Ｅの反転信号が供給されている。
【０１２６】
ＰＭＯＳトランジスタＭＰ７１２（第１５のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ７１２のドレインに接続されている。ＰＭＯＳトランジスタＭＰ７１４（第１６のＭＯＳトランジスタ）は、ソースがＶＤＤ２に接続され、ドレインがＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５のドレインに接続されている。そして、ＰＭＯＳトランジスタＭＰ７１２のゲートが、ＰＭＯＳトランジスタＭＰ７１４とＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５のドレインに接続され、ＰＭＯＳトランジスタＭＰ７１４のゲートが、ＰＭＯＳトランジスタＭＰ７１２とＮＭＯＳトランジスタＭＮ７１２のドレインに接続されている。
【０１２７】
また、ＮＭＯＳトランジスタＭＮ７２１（第４のスイッチ素子）は、ソースがＧＮＤに接続され、ゲートにインバータＩＮ３を介した入力信号ＶＯＦＦの反転信号が供給されている。ＮＭＯＳトランジスタＭＮ７１８（第１７のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７２１のドレインに接続され、ゲートが第１のラッチのＰＭＯＳトランジスタＭＰ７０６とＮＭＯＳトランジスタＭＮ７０６，ＭＮ７１０のドレインに接続されている。ＮＭＯＳトランジスタＭＮ７１７（第１８のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７１８のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ７１２とＮＭＯＳトランジスタＭＮ７１２のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ７１４とＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５のドレインに接続されている。
【０１２８】
また、ＮＭＯＳトランジスタＭＮ７１９（第１９のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７２１のドレインに接続され、ゲートがＰＭＯＳトランジスタＭＰ７１２とＮＭＯＳトランジスタＭＮ７１２，ＭＮ７１７のドレインに接続されている。ＮＭＯＳトランジスタＭＮ７２０（第２０のＭＯＳトランジスタ）は、ソースがＮＭＯＳトランジスタＭＮ７２１のドレインに接続され、ドレインがＰＭＯＳトランジスタＭＰ７１４とＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５およびＭＮ７１９のドレインに接続され、ゲートが第１のラッチのＰＭＯＳトランジスタＭＰ７０４とＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５およびＭＮ７０９のドレインに接続されている。
【０１２９】
そして、第２のラッチの出力信号として、ＰＭＯＳトランジスタＭＰ７１４とＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５およびＭＮ７１７のドレイン電圧が次段に出力される。
【０１３０】
次に、第１および第２のラッチからの出力を受ける２つのＭＯＳトランジスタについて説明する。ＶＤＤ２とＧＮＤ間にＰＭＯＳトランジスタＭＰ７２２（第１のＭＯＳトランジスタ）とＮＭＯＳトランジスタＭＮ７２２（第２のＭＯＳトランジスタ）が直列接続されている。ＰＭＯＳトランジスタＭＰ７２２は、ソースがＶＤＤ２に接続され、ゲートに第１のラッチの出力信号が供給されている。また、ＮＭＯＳトランジスタＭＮ７２２は、ソースがＧＮＤに接続され、ドレインがＰＭＯＳトランジスタＭＰ７２２のドレインに接続され、ゲートに第２のラッチの出力信号が供給されている。そして、出力信号Ｚとして、ＰＭＯＳトランジスタＭＰ７２２とＮＭＯＳトランジスタＭＮ７２２のドレイン電圧が出力される。
【０１３１】
次に、本実施形態の動作について説明する。入力信号ＶＯＦＦに“Ｈ”レベルが入力された場合、入力信号Ａ，Ｅの信号レベルを変換して出力信号Ｚに信号を出力するレベルシフト回路として動作する。入力信号ＶＯＦＦが“Ｈ”レベルなので、ＮＭＯＳトランジスタＭＮ７０８，ＭＮ７１６はオン状態となり、ＮＭＯＳトランジスタＭＮ７１１，ＭＮ７２１はオフ状態となる。
【０１３２】
入力信号Ａ，イネーブル信号Ｅが“Ｈ”レベルの場合を考える。第１のラッチのＮＭＯＳトランジスタＭＮ７０４，ＭＮ７０５はオフ状態となり、ＮＭＯＳトランジスタＭＮ７０６，Ｎ７０７はオン状態となる。したがって、ＮＭＯＳトランジスタＭＮ７０６のドレイン電圧はＧＮＤレベルとなり、第１のラッチの出力信号としてＧＮＤレベルの信号が次段に供給される。
【０１３３】
また、ＰＭＯＳトランジスタＭＰ７０４のゲートにＧＮＤレベル（“Ｌ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ７０４はオン状態となる。すると、ＰＭＯＳトランジスタＭＰ７０４のドレイン電圧はＶＤＤ２レベル（“Ｈ”レベル）となる。そして、ＰＭＯＳトランジスタＭＰ７０６のゲートにＶＤＤ２レベル（“Ｈ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ７０６はオフ状態となる。
【０１３４】
一方、第２のラッチのＮＭＯＳトランジスタＭＮ７１２，ＭＮ７１５はオフ状態となり、ＮＭＯＳトランジスタＭＮ７１３，ＭＮ７１４はオン状態となる。したがって、ＮＭＯＳトランジスタＭＮ７１４，ＭＮ７１５のドレイン電圧はＧＮＤレベルとなり、第２のラッチの出力信号としてＧＮＤレベルの信号が次段に供給される。
【０１３５】
また、ＰＭＯＳトランジスタＭＰ７１２のゲートにＧＮＤレベル（“Ｌ”レベル）の信号が供給され、ＰＭＯＳトランジスタＭＰ７１２はオン状態となる。すると、ＰＭＯＳトランジスタＭＰ７１２のドレイン電圧はＶＤＤ２レベル（“Ｈ”レベル）となる。ＰＭＯＳトランジスタＭＰ７１４のゲートにＶＤＤ２レベル（“Ｈ”レベル）が供給され、ＰＭＯＳトランジスタＭＰ７１４はオフ状態となる。
【０１３６】
そして、ＰＭＯＳトランジスタＭＰ７２２のゲートに、第１のラッチからＧＮＤレベル（“Ｌ”レベル）の信号が供給され、オン状態となる。一方、ＮＭＯＳトランジスタＭＮ７２２のゲートに、第２のラッチからＧＮＤレベル（“Ｌ”レベル）の信号が供給され、オフ状態となる。したがって、出力信号Ｚとして、ＶＤＤ２レベルの信号が出力される。
【０１３７】
一方、入力信号ＶＯＦＦに“Ｌ”レベルが入力された場合、入力信号ＶＯＦＦに“Ｈ”レベルを入力していた時の入力信号Ａ、イネーブル信号Ｅに応じた信号を第１および第２のラッチの出力信号に保持しているので、出力信号Ｚは“Ｈ”レベル、“Ｌ”レベル、または、ハイインピーダンスを出力し続ける。入力信号ＶＯＦＦが“Ｌ”レベルであるので、ＮＭＯＳトランジスタＭＮ７０８，ＭＮ７１６はオフ状態、ＮＭＯＳトランジスタＭＮ７１１，ＭＮ７２１はオン状態となる。
【０１３８】
この時、ＰＭＯＳトランジスタＭＰ７２２とＮＭＯＳトランジスタＭＮ７２２が共にオン状態とならないように、第２のラッチは、リセット機能付き（ＮＭＯＳトランジスタＭＮ７１８，ＭＮ７２０）となっている。第１のラッチの出力信号がＰＭＯＳトランジスタＭＰ７２２のゲートの入力信号として“Ｌ”レベルを保持した時は、第２のラッチの出力信号がＮＭＯＳトランジスタＭＮ７２２のゲートの入力信号として保持した信号を“Ｌ”レベルにリセットする。つまり、ＮＭＯＳトランジスタＭＮ７１８をオフ状態にして遮断し、ＮＭＯＳトランジスタＭＮ７２０をオン状態にしてＮＭＯＳトランジスタＭＮ７２０のドレイン電圧、すなわち、出力信号Ｑ２をＧＮＤレベル（“Ｌ”レベル）にすることで、ＮＭＯＳトランジスタＭＮ７２２への入力信号を“Ｌ”レベルの状態に設定する。
【０１３９】
したがって、ＰＭＯＳトランジスタＭＰ７２２とＮＭＯＳトランジスタＭＮ７２２は共にオン状態となることなく、出力信号Ｚは“Ｈ”レベル、“Ｌ”レベル、または、ハイインピーダンスを出力し続ける。
【０１４０】
以下、第７の実施形態の真理値表を表３に示す。表３中の“Ｘ”は、“Ｈ”または“Ｌ”である。
【０１４１】
【表３】

【０１４２】
入力信号ＶＯＦＦが“Ｌ”レベルの時に、ＶＤＤ１を切ったとすると、入力信号Ａ、イネーブル信号Ｅおよびこれらの反転信号は不安定な状態となる。しかし、ＮＭＯＳトランジスタＭＮ７０８，ＭＮ７１６はオフ状態となっているので、ＶＤＤ２からＧＮＤにスタティックリーク電流は流れない。また、ＶＤＤ１を切った場合でも、出力段のＭＯＳトランジスタは共にオンすることなく、第１および第２のラッチは保持した信号を出力し続けるので、出力信号Ｚに影響はない。
【０１４３】
よって、本実施形態は、レベルシフト機能のあるトライステートゲートとして働き、ＶＤＤ１を切っても出力信号には影響がない。また、ＶＤＤ１を切った場合に、不安定となる入力信号Ａ、イネーブル信号Ｅおよびこれらの反転信号を遮断できるので、スタティックリーク電流が流れない。また、意図的に電源電圧に差を持たせている場合はもとより、同一電圧を供給する電源の系統間での電圧にズレが生じた場合でも、スタティックリーク電流の増加を防ぐことができる。
（第８の実施の形態）
図８は、本発明の中継用マクロセルを組み込んだ半導体集積回路のブロック図である。上記に説明した実施の形態の中継用マクロセルを、回路ブロック間に組み込んでいる。
【０１４４】
回路ブロックＢ１はＶＤＤ１で動作し、回路ブロックＢ２はＶＤＤ２で動作する。そして、回路ブロックＢ１，Ｂ２間に、中継用マクロセルＴ１，Ｔ２が組み込まれている。中継用マクロセルＴ１は、ＶＤＤ２の電源系統に含まれている入力信号ＶＯＦＦ１が入力され、ＶＤＤ１からＶＤＤ２の信号レベルに変換するレベルシフト回路として動作する。また、中継用マクロセルＴ２は、ＶＤＤ１の電源系統に含まれている入力信号ＶＯＦＦ２が入力され、ＶＤＤ２からＶＤＤ１の信号レベルに変換するレベルシフト回路として動作する。そして、回路ブロック間に組み込む中継用マクロセルは、入力信号および出力信号に応じて第１〜第７の実施の形態を選択する。
【０１４５】
尚、図８の半導体集積回路は、同一チップ上に配置してもよいし、別々のチップ上に配置してもよい。別々のチップ上に配置する場合は、回路ブロックＢ１，Ｂ２の入力側または出力側に中継用マクロセルを配置すればよい。例えば、回路ブロックＢ１と中継用マクロセルＴ１が同一のチップ上に配置され、回路ブロックＢ２と中継用マクロセルＴ２が同一のチップ上に配置される。そして、中継用マクロセルＴ１からの出力信号が回路ブロックＢ２に、中継用マクロセルＴ２からの出力信号が回路ブロックＢ１に入力される。
【０１４６】
本実施の形態は、電源電圧が異なるかどうかによらず、電源系統の異なる回路ブロック間での信号のレベルシフトはもとより、同じ電源電圧でも系統間で電圧が微妙に異なってしまった場合についても、信号レベル変換され、スタティックリーク電流の増加を防ぐことができる。また、電源系統のいくつかを切って、その系統から電源供給を受けている回路ブロックの信号が不安定になっても、信号を遮断し、電源の入っている回路ブロックの動作に影響が及ぶのを防ぐことができる。
【０１４７】
【発明の効果】
本発明の中継用マクロセルを用いることにより、ある電源系統を切ってその系統から電源供給を受けている回路ブロックの信号が不安定になっても、電源の入っている回路ブロックの動作に影響がおよぶことを防ぐことができる。
【０１４８】
電源電圧が異なる回路ブロック間での信号のレベルシフトはもとより、同じ電源電圧でも系統間で電圧が微妙に異なってしまった場合についても、本発明の中継用マクロセルを用いることにより、信号レベルが変換され、スタティックリーク電流の増加を防ぐことができる。
【図面の簡単な説明】
【図１】第１の実施形態における中継用マクロセルの回路図。
【図２】第２の実施形態における中継用マクロセルの回路図。
【図３】第３の実施形態における中継用マクロセルの回路図。
【図４】第４の実施形態における中継用マクロセルの回路図。
【図５】第５の実施形態における中継用マクロセルの回路図。
【図６】第６の実施形態における中継用マクロセルの回路図。
【図７】第７の実施形態における中継用マクロセルの回路図。
【図８】本発明の中継用マクロセルを組み込んだ半導体集積回路のブロック図。
【図９】従来の半導体装置の回路図。
【図１０】従来の半導体装置の回路図。
【符号の説明】
ＭＰ１０１〜ＭＰ９０５…ＰＭＯＳトランジスタ
ＭＮ１０１〜ＭＮ９０６…ＮＭＯＳトランジスタ
Ａ、Ｄ、ＶＯＦＦ…入力信号
Ｅ…イネーブル信号
ＣＰＮ…クロック入力信号
Ｚ、Ｑ、ＱＮ…出力信号
Ｂ１、Ｂ２…回路ブロック
Ｔ１、Ｔ２…中継用マクロセル[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a relay macro cell having a level shift function arranged between circuit blocks having different power sources.
[0002]
[Prior art]
In portable devices and the like, from the viewpoint of lowering power consumption during standby, in recent years, it has become common to reduce power consumption by turning off the power of circuits that are not necessary even in CMOS semiconductor integrated circuits. This is because power consumption voltage and threshold voltage have to be lowered along with miniaturization of the semiconductor integrated circuit, and standby power consumption increases.
[0003]
General precautions such as input and output measures for circuit blocks that have been turned off, and when the power supply is divided into multiple systems, attention must be paid to the voltage difference between the power systems in order to turn off the power for each circuit block. is there.
[0004]
FIG. 9 is a circuit diagram of a conventional level shift circuit. This is a 2-input NAND circuit. Input signals A and B and their inverted signals are included in the power supply system of VDD1. The source of the NMOS transistor MN903 is connected to GND, and the inverted signal of the input signal A is supplied to the gate via the inverter IN1 (NMOS transistor MN901, PMOS transistor MP901). The NMOS transistor MN904 has a source connected to GND, a drain connected to the drain of the NMOS transistor MN903, and a gate supplied with an inverted signal of the input signal B via the inverter IN2 (NMOS transistor MN902, PMOS transistor MP902). .
[0005]
The NMOS transistor MN906 has a source connected to GND and an input signal B supplied to the gate. The source of the NMOS transistor MN905 is connected to the drain of the NMOS transistor MN906, and the input signal A is supplied to the gate.
[0006]
The PMOS transistor MP903 has a source connected to VDD2 and a drain connected to the drains of the NMOS transistors MN903 and MN904. The PMOS transistor MP905 has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN905. The gate of the PMOS transistor MP903 is connected to the drains of the PMOS transistor MP905 and the NMOS transistor MN905. The gate of the PMOS transistor MP905 is connected to the drains of the PMOS transistor MP903 and the NMOS transistors MN903 and MN904. As the output signal Z, drain voltages of the PMOS transistor MP905 and the NMOS transistor MN905 are output.
[0007]
[Problems to be solved by the invention]
However, when the power supply (VDD1) is turned off to reduce power consumption, it takes a long time for the output signal of the CMOS circuit to drop to the GND level. This is because when the power is turned off and the gate-source voltage of the MOSFET drops to about the threshold voltage, the current flowing between the source and the drain becomes very small, and the output voltage remains somewhat higher than the GND level. Tend. When a circuit block that is turned on receives such a signal as it is as an input signal, the NMOS transistor is not sufficiently turned off, leading to an increase in static leakage current.
[0008]
In FIG. 9, for example, when VDD1 is turned off when the input signal A is at “L” level, the output of the inverter IN1 falls from “H” level (VDD1 level) to GND level, and the NMOS transistor MN903 is turned off. To do. However, it may remain at a level somewhat higher than the GND level, and the NMOS transistor MN903 is not completely turned off. Therefore, a leak current flows from VDD2 to GND.
[0009]
Further, even when the power supply voltage is not intentionally changed between the systems, if the threshold voltage is lowered, there is a concern that the static leakage current increases even with a slight voltage difference between the power supply systems.
[0010]
In order to prevent such a situation, in the case of circuit blocks operating at the same potential, NAND gates and clocked inverters are used as a measure to cut off the signal from the circuit block that is turned off at the input part of the circuit block that is turned on. Although a latch or flip-flop is inserted, the circuit scale becomes large.
[0011]
Further, in the CMOS circuit, when the drain of the PMOS transistor is included in the input terminal, when the power is turned off and the potential of the PMOS source and the N well is lowered, the PN junction between the drain and the N well becomes a forward bias and a current flows. Therefore, the input impedance of the input terminal is lowered. If current flows into the input terminal, static current increases or malfunctions occur.
[0012]
An object of the present invention is to provide a relay macro cell with a level shift function that performs stable operation when a power supply that is not necessary for operation is turned off.
[0013]
[Means for Solving the Problems]
The relay macrocell according to the present invention is connected between a first power source that is a first potential, a second power source that is a second potential, and the first power source and the second power source. A first input signal having a first current path and a second current path, connected to the second power supply side of the first current path, and having a third potential or a ground potential, and the second current path. A first switch circuit controlled by a second input signal that is a potential of the second current or a ground potential; and an inverted signal of the first input signal connected to the second power supply side of the second current path; And a first level shift circuit including a second switch circuit controlled by an inverted signal of the second input signal.
[0014]
A first power source that is a first potential; a second power source that is a second potential; a first input signal that is connected to the first power source and that is a third potential or a ground potential; Between the first level shift circuit to which the inverted signal is input, the first holding circuit that holds the output of the first level shift circuit, and between the first level shift circuit and the second power supply A first switch element connected to the first holding circuit and a second switch element connected between the first holding circuit and the second power source, wherein the first switch element includes the first switch element The second switch element is controlled by an inverted signal of the second input signal.
[0015]
A first power source that is a first potential; a second power source that is a second potential; a first input signal that is connected to the first power source and that is a third potential or a ground potential; A level shift circuit to which the inverted signal is input, and a switch element connected between the level shift circuit and the second power supply and controlled by the second input signal which is the first potential or the ground potential And an output signal of the level shift circuit, the second input signal, and a clocked inverter supplied with the inverted signal.
[0016]
A first power source that is a first potential; a second power source that is a second potential; and first and second input signals that are connected to the first power source and have a third potential. A first level shift circuit to which these inverted signals are input, a first holding circuit connected to the first level shift circuit and holding an output signal of the first level shift circuit, and the first level shift circuit A second level shift circuit connected to a power source, to which the first and second input signals and their inverted signals are input, and to the first and second level shift circuits, the second level shift circuit A second holding circuit for holding an output signal of the circuit; a first switch element connected between the first level shift circuit and the second power supply; the second level shift circuit; A second switch connected to a second power source A third switch element connected between the first holding circuit and the second power supply, and a fourth switch connected between the second holding circuit and the second power supply. A switch element, a first MOS transistor of one conductivity type, the source of which is connected to the first power supply, and the output signal of the first level shift circuit or the first holding circuit is supplied to the gate; Reverse conductivity in which a source is connected to the second power supply, a drain is connected to a drain of the first MOS transistor, and an output signal of the second level shift circuit or the second holding circuit is supplied to a gate A second MOS transistor of the type, wherein the first and second switch elements are controlled by a third input signal which is the first potential or the ground potential, and the third and fourth switch elements Said It is being controlled by the inverted signal of the third input signal.
[0017]
According to the present invention, even if a signal of a circuit block receiving power supply from the power system is turned off and the signal of the circuit block becomes unstable, the operation of the circuit block that is turned on is prevented from being affected. Can do.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram of a relay macro cell according to the first embodiment. This is an enabled buffer (two-input NAND gate) having a level shift function. An inverter IN1 to which an input signal A (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an input signal VOFF between VDD2 (first potential) and GND ( The inverter IN2 is supplied with a second input signal), and the buffer is controlled by the input signal A, the input signal VOFF, and the output signals of the inverters IN1 and IN2. The input signal A and its inverted signal are included in the power supply system of VDD1, and the input signal VOFF, its inverted signal, and the output signal Z are included in the power supply system of VDD2.
[0019]
The buffer will be described. The source of the NMOS transistor MN103 (first MOS transistor) is connected to GND, and the output signal of the inverter IN1 (NMOS transistor MN101, PMOS transistor MP101) is supplied to the gate. The NMOS transistor MN104 (second MOS transistor) connected in parallel with the NMOS transistor MN103 has a source connected to GND, a drain connected to the drain of the NMOS transistor MN103, and a gate connected to the inverter IN2 (NMOS transistor MN102, PMOS transistor). MP102) output signal is supplied. The PMOS transistor MP103 (fifth MOS transistor) has a source connected to VDD2 and a drain connected to the drains of the NMOS transistor MN103 and the NMOS transistor MN104.
[0020]
The NMOS transistor MN106 (third MOS transistor) has a source connected to the GND and an input signal VOFF supplied to the gate. The NMOS transistor MN105 (fourth MOS transistor) connected in series with the NMOS transistor MN106 has a source connected to the drain of the NMOS transistor MN106 and an input signal A supplied to the gate. The PMOS transistor MP105 (sixth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN105.
[0021]
The gate of the PMOS transistor MP103 is connected to the drains of the PMOS transistor MP105 and the NMOS transistor MN105, and the gate of the PMOS transistor MP105 is connected to the drains of the PMOS transistor MP103 and the NMOS transistors MN103 and MN104. Then, the drain voltage of the PMOS transistor MP103 and the NMOS transistors MN103 and MN104 is output as the output signal Z.
[0022]
Note that the input signals supplied to the gates of the NMOS transistors MN105 and MN106 may be reversed. That is, the input signal VOFF may be supplied to the gate of the NMOS transistor MN105, and the input signal A may be supplied to the gate of the NMOS transistor MN106.
[0023]
Next, the operation of this embodiment will be described. When the “L” level is input to the input signal VOFF, the output signal Z is fixed to the “L” level. The gate of the NMOS transistor MN106 is supplied with the “L” level and is turned off. Further, the inverted signal (“H” level) of the input signal VOFF via the inverter IN2 is supplied to the gate of the NMOS transistor MN104, and the NMOS transistor MN104 is turned on. Then, the drain voltage of the NMOS transistor MN104 becomes the GND level, and a signal of the GND level is output as the output signal Z.
[0024]
Further, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP105, and the PMOS transistor MP105 is turned on. Then, the drain voltage of the PMOS transistor MP105 becomes the VDD2 level. A signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP103, and the PMOS transistor MP103 is turned off.
[0025]
Therefore, the NMOS transistor MN105 operated by the input signal A is cut off when the NMOS transistor MN106 is turned off when the input signal VOFF is at "L" level. Therefore, when the input signal VOFF is at the “L” level, the output signal Z is fixed to the GND level by turning on the NMOS transistor MN104 even if the VDD1 including the input signal A is cut off.
[0026]
Further, when the input signal VOFF is “L” level, the NMOS transistor MN104 is turned on, so that the drain of the NMOS transistor MN103 is at the GND level, and the NMOS transistor MN106 is turned off. Therefore, even if the input signal A and its inverted signal become unstable after turning off VDD1, no static leakage current flows from VDD2 to GND.
[0027]
On the other hand, when the “H” level is input to the input signal VOFF, it operates as a level shift circuit that can convert the input signal A into the signal level of the output signal Z. Since the input signal VOFF is at “H” level, the NMOS transistor MN104 is turned off and the NMOS transistor MN106 is turned on.
[0028]
When the input signal A is at the “L” level, the NMOS transistor MN103 is supplied with the inverted signal (“H” level) of the input signal A via the inverter IN1, and is turned on. Further, the “L” level is supplied to the gate of the NMOS transistor MN105, and the NMOS transistor MN105 is turned off. Then, the drain voltage of the NMOS transistor MN103 becomes the GND level, and a signal of the GND level is output as the output signal Z.
[0029]
When the input signal A is at “H” level, the inverted signal (“L” level) of the input signal A is supplied to the NMOS transistor MN103 via the inverter IN1, and the NMOS transistor MN103 is turned off. Further, the “H” level is supplied to the gate of the NMOS transistor MN105, which is turned on. Then, since the NMOS transistor MN106 and the NMOS transistor MN105 are turned on, the drain voltage of the NMOS transistor MN105 becomes the GND level. Then, since the GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP103, the PMOS transistor MP103 is turned on. Then, the drain voltage of the PMOS transistor MP103 becomes the VDD2 level. Therefore, a VDD2 level signal is output as the output signal Z.
[0030]
Therefore, when the input signal VOFF is at “H” level, the present embodiment operates as a level shift circuit.
[0031]
Therefore, the present embodiment functions as a level shift circuit and does not affect the output signal even if VDD1 is cut. In addition, when VDD1 is cut, the unstable input signal A and its inverted signal can be cut off, so that no static leakage current flows. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
[0032]
In the above description, the drain voltages of the PMOS transistor MP103 and the NMOS transistors MN103 and MN104 are output as the output signal Z, but the drain voltages of the PMOS transistor MP105 and the NMOS transistor MN105 may be output. In this case, an inverted signal level with respect to the above description is output.
[0033]
A semiconductor device for solving the same problem is disclosed in Japanese Patent Laid-Open No. 9-74348. FIG. 10 shows a circuit diagram of this semiconductor device. The inverter 101 using the low voltage power supply (VDDL) as the power supply, the booster circuit 102 using the high voltage power supply (VDDH) as the power supply, and the inverter 103 using VDDH as the power supply constitute a boost level shifter. In this booster circuit 102, a Pch transistor 110 is provided as a pull-up transistor between the VDDH power supply and the output node A, and the operation of the booster circuit 102 is performed between the VSS power supply and a point C which is a connection node of the current source. An Nch transistor 111 is provided as a switch to be controlled. The gates of the Pch transistor 110 and the Nch transistor 111 are connected to a CNT terminal through which a signal from a VDDH power supply circuit is propagated, thereby constituting a control function unit.
[0034]
When the Nch transistor 111 is turned on, the potential propagated to the IN terminal is boosted by the booster circuit 102, propagated to the OUT terminal, and functions as a boost level shifter. When the Pch transistor 110 is turned on, the VDDH potential is supplied to the inverter 103, so that the VSS potential is output to the OUT terminal. As described above, the semiconductor device of FIG. 10 cuts off the function as a boost level shifter by turning off the Nch transistor 111 and fixes the output to the OUT terminal at the VSS potential.
[0035]
However, when the Pch transistor 110 is turned on, the point A becomes the VDDH potential and becomes stable, but the point B which is the connection node of the other current source becomes unstable when the VDDL power supply is turned off.
[0036]
On the other hand, in the present invention, even when VDD1 including the input signal A is cut, the drain voltage of the NMOS transistor MN104 becomes the GND level by turning on the NMOS transistor MN104. Since the PMOS transistor MP105 is turned on, the drain voltage of the PMOS transistor MP105 is stabilized at the VDD2 level.
[0037]
Further, since the level shift function portion of the relay macrocell of the present invention is composed of a small number of MOS transistors, the area can be made smaller than that of the booster circuit 102 of FIG.
(Second Embodiment)
FIG. 2 is a circuit diagram of the relay macro cell in the second embodiment. This is a latch having a level shift function. An inverter IN1 to which an input signal D (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an input signal VOFF (in between VDD2 (first potential) and GND) The inverter IN2 to which the second input signal) is supplied and the latch controlled by the input signal D, the input signal VOFF, and the output signals of the inverters IN1 and IN2. The input signal D and its inverted signal are included in the power supply system of VDD1, and the input signal VOFF, its inverted signal, and output signals Q and QN are included in the power supply system of VDD2.
[0038]
The latch will be described. The source of the NMOS transistor MN205 (first MOS transistor) is connected to GND, and the input signal VOFF is supplied to the gate. The NMOS transistor MN203 (third MOS transistor) has a source connected to the drain of the NMOS transistor MN205 and an input signal D supplied to the gate. The source of the NMOS transistor MN204 (fourth MOS transistor) is connected to the drain of the NMOS transistor MN205, and the inverted signal of the input signal D is supplied to the gate via the inverter IN1 (NMOS transistor MN201, PMOS transistor MP201). . The PMOS transistor MP203 (fifth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN203. The PMOS transistor MP204 (sixth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN204. The gate of the PMOS transistor MP203 is connected to the drains of the PMOS transistor MP204 and the NMOS transistor MN204, and the gate of the PMOS transistor MP204 is connected to the drains of the PMOS transistor MP203 and the NMOS transistor N203.
[0039]
The NMOS transistor MN208 (second MOS transistor) has a source connected to GND, and a gate supplied with an inverted signal of the input signal VOFF via the inverter IN2 (NMOS transistor MN202, PMOS transistor MP202). The NMOS transistor MN206 (seventh MOS transistor) has a source connected to the drain of the NMOS transistor MN208 and a gate connected to the drains of the PMOS transistor MP204 and the NMOS transistor MN204. The NMOS transistor MN207 (eighth MOS transistor) has a source connected to the drain of the NMOS transistor MN208 and a gate connected to the drains of the PMOS transistor MP203 and the NMOS transistor MN203.
[0040]
As the output signal Q, drain voltages of the PMOS transistor MP204 and the NMOS transistors MN204 and MN207 are output. Further, drain voltages of the PMOS transistor MP203 and the NMOS transistors MN203 and MN206 are output as the output signal QN.
[0041]
This latch circuit turns on either the NMOS transistor MN205 or the NMOS transistor MN208 by the input signal VOFF, and outputs a signal corresponding to the input signal D when the NMOS transistor MN205 is turned on. When is turned on, the held signal is continuously output.
[0042]
Next, the operation of this embodiment will be described. When the “H” level is input to the input signal VOFF, it operates as a level shift circuit capable of converting the input signal D into the signal levels of the output signals Q and QN. Since the input signal VOFF is at “H” level, the NMOS transistor MN205 is turned on and the NMOS transistor MN208 is turned off. Therefore, output signals Q and QN corresponding to the input signal D are output.
[0043]
Consider a case where the input signal D is at “H” level. An “H” level signal is supplied to the gate of the NMOS transistor MN203, which is turned on. On the other hand, the inverted signal (“L” level) of the input signal D via the inverter IN1 is supplied to the gate of the NMOS transistor MN204, and the NMOS transistor MN204 is turned off. Then, the drain voltage of the NMOS transistor MN203 becomes the GND level, and a GND level signal is output as the output signal QN. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP204, and the PMOS transistor MP204 is turned on. The drain voltage of the PMOS transistor MP204 is at the VDD2 level, and a VDD2 level signal is output as the output signal Q. Also, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP203, and the PMOS transistor MP203 is turned off.
[0044]
Consider a case where the input signal D is at "L" level. An “L” level signal is supplied to the gate of the NMOS transistor MN203, and the NMOS transistor MN203 is turned off. On the other hand, the inverted signal (“H” level) of the input signal D via the inverter IN1 is supplied to the gate of the NMOS transistor MN204, which is turned on. Then, the drain voltage of the NMOS transistor MN204 becomes the GND level, and a GND level signal is output as the output signal Q. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP203, and the PMOS transistor MP203 is turned on. Accordingly, the drain voltage of the PMOS transistor MP203 is at the VDD2 level, and a VDD2 level signal is output as the output signal QN. Further, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP204, and the PMOS transistor MP204 is turned off.
[0045]
Therefore, when the input signal VOFF is at “H” level, the present embodiment operates as a level shift circuit corresponding to the input signal D.
[0046]
On the other hand, when the input signal VOFF changes from the “H” level to the “L” level, the held signals are continuously output as the output signals Q and QN. Since the input signal VOFF is at the “L” level, the NMOS transistor MN205 changes to the off state, and the NMOS transistor MN208 changes to the on state. Due to the potential difference between the drain node of the PMOS transistor MP203 and the NMOS transistor MN203 and the drain node of the PMOS transistor MP204 and the NMOS transistor MN204, one of the NMOS transistors MN206 and MN207 is turned on, and the drain of the NMOS transistor that is turned on The voltage is at the GND level. The drain voltage of the NMOS transistor in the off state remains at the held signal level.
[0047]
At this time, if VDD1 is cut, the input signal D becomes unstable. However, since the NMOS transistor MN205 is in the off state, no static leakage current flows from VDD2 to GND. Further, even when VDD1 is cut, the held signal is continuously output, so the output signals Q and QN are not affected.
[0048]
Therefore, this embodiment functions as a latch circuit having a level shift function, and the output signal is not affected even if VDD1 is cut. In addition, when VDD1 is cut, the input signal D that becomes unstable and its inverted signal can be cut off, so that no static leakage current flows. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
(Third embodiment)
FIG. 3 is a circuit diagram of a relay macro cell according to the third embodiment. This is a flip-flop with enable with level shift function. An inverter IN1 to which an input signal D (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an input signal VOFF (in between VDD2 (first potential) and GND) A NAND circuit to which a fourth input signal) and a clock signal CPN are supplied, an inverter IN2 to which an output signal (second input signal) of the NAND circuit is supplied between VDD2 and GND, an input signal D and a NAND circuit Master latch (first level shift circuit, first holding circuit) and slave latch (second level shift circuit, second holding circuit) controlled by the output signal of the inverter IN1 and IN2 It consists of flip-flops consisting of The input signal D and its inverted signal are included in the VDD1 power supply system, and the input signal VOFF, the clock signal CPN, these NAND logics, their inverted signals, and the output signals Q and QN are included in the VDD2 power supply system.
[0049]
The NAND circuit includes PMOS transistors MP302 and MP303 and NMOS transistors MN302 and MN303. A PMOS transistor MP302, NMOS transistor MN302, and NMOS transistor MN303 are connected in series between VDD2 and GND. The clock signal CPN is supplied to the gates of the PMOS transistor MP302 and the NMOS transistor MN302, and the input signal VOFF is supplied to the gate of the NMOS transistor MN303. A PMOS transistor MP303 is connected in parallel with the PMOS transistor MP302. The source of the PMOS transistor MP303 is connected to VDD2, the drain is connected to the drains of the PMOS transistor MP302 and the NMOS transistor MN302, and the input signal VOFF is supplied to the gate. The output signal of the NAND circuit is supplied to the NMOS transistor MN310 and the NMOS transistor MN313. Further, a signal via the inverter IN2 (NMOS transistor MN304, PMOS transistor MP304), that is, an inverted signal of the output signal of the NAND circuit is supplied to the NMOS transistor MN307 and the NMOS transistor MN316.
[0050]
Next, the master latch will be described. The source of the NMOS transistor MN307 (first MOS transistor) is connected to GND, and the inverted signal of the output signal of the NAND circuit is supplied to the gate. The source of the NMOS transistor MN305 (third MOS transistor) is connected to the drain of the NMOS transistor MN307, and the input signal D is supplied to the gate. The NMOS transistor MN306 (fourth MOS transistor) has a source connected to the drain of the NMOS transistor MN307 and a gate supplied with an inverted signal of the input signal D via the inverter IN1 (NMOS transistor MN301, PMOS transistor MP301). . The PMOS transistor MP305 (fifth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN305. The PMOS transistor MP306 (sixth MOS transistor) has a source connected to VDD2 and a drain connected to the NMOS transistor MN306. The gate of the PMOS transistor MP305 is connected to the drains of the PMOS transistor MP306 and the NMOS transistor MN306, and the gate of the PMOS transistor MP306 is connected to the drains of the PMOS transistor MP305 and the NMOS transistor MN305.
[0051]
Then, drain voltages of the PMOS transistor MP305 and the NMOS transistor MN305 and drain voltages of the PMOS transistor MP306 and the NMOS transistor NMOS306, that is, a signal corresponding to the input signal D is supplied to the slave latch of the next stage.
[0052]
Further, the source of the NMOS transistor MN310 (second MOS transistor) is connected to GND, and the output signal of the NAND circuit is supplied to the gate. The NMOS transistor MN308 (seventh MOS transistor) has a source connected to the drain of the NMOS transistor MN310 and a gate connected to the drains of the PMOS transistor MP306 and the NMOS transistor MN306. The NMOS transistor MN309 (eighth MOS transistor) has a source connected to the drain of the NMOS transistor MN310 and a gate connected to the drains of the PMOS transistor MP305 and the NMOS transistor MN305. The drain of the NMOS transistor MN308 is connected to the drains of the PMOS transistor MP305 and the NMOS transistor MN305, and the drain of the NMOS transistor MN309 is connected to the drains of the PMOS transistor MP306 and the NMOS transistor MN306.
[0053]
Next, the slave latch will be described. The source of the NMOS transistor MN313 is connected to GND, and the output signal of the NAND circuit is supplied to the gate. The source of the NMOS transistor MN311 is connected to the drain of the NMOS transistor MN313, and the drain voltage (third input signal) of the PMOS transistor MP306 and the NMOS transistors MN306 and MN309 of the preceding master latch is supplied to the gate. The source of the NMOS transistor MN312 is connected to the drain of the NMOS transistor MN313, and the drain voltages of the PMOS transistor MP305 and the NMOS transistors MN305 and MN308 of the preceding master latch are supplied to the gate. The PMOS transistor MP311 has a source connected to VDD2 and a drain connected to the NMOS transistor MN311. The PMOS transistor MP312 has a source connected to VDD2 and a drain connected to the NMOS transistor MN312. The gate of the PMOS transistor MP311 is connected to the drains of the PMOS transistor MP312 and the NMOS transistor MN312. The gate of the PMOS transistor MP312 is connected to the drains of the PMOS transistor MP311 and the NMOS transistor MN311. Here, the output signals Q and QN are output in accordance with the output signal from the master latch at the previous stage.
[0054]
The NMOS transistor MN316 has a source connected to the GND and a gate supplied with an inverted signal of the output signal of the NAND circuit. The NMOS transistor MN314 has a source connected to the drain of the NMOS transistor MN316 and a gate connected to the drains of the PMOS transistor MP312 and the NMOS transistor MN312. The NMOS transistor MN315 has a source connected to the drain of the NMOS transistor MN316, and a gate connected to the drains of the PMOS transistor MP311 and the NMOS transistor MN311. The gate of the NMOS transistor MN314 is connected to the drains of the PMOS transistor MP312 and the NMOS transistor MN312. The gate of the NMOS transistor MN315 is connected to the drains of the PMOS transistor MP311 and the NMOS transistor MN311. Then, drain voltages of the PMOS transistor MP312 and NMOS transistors MN312 and MN315 are output as the output signal Q, and drain voltages of the PMOS transistor MP311 and NMOS transistors MN311 and MN314 are output as the output signal QN.
[0055]
Next, the operation of this embodiment will be described. When “H” level is input to both the input signal VOFF and the clock input signal CPN, it operates as a level shift circuit that converts the signal level of the input signal D and reads the signal into the master latch, and is held in the slave latch. Data is output as output signals Q and QN. In this case, the output signal of the NAND circuit becomes “L” level. Therefore, the NMOS transistor MN307 and the NMOS transistor MN316 are turned on, and the NMOS transistor MN310 and the NMOS transistor MN313 are turned off.
[0056]
At this time, when the input signal D is at “H” level, the NMOS transistor MN305 is turned on and the NMOS transistor MN306 is turned off. Therefore, the drain voltage of the NMOS transistor MN305 becomes the GND level and is supplied to the NMOS transistor MN312 of the slave latch at the next stage. Then, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP306, and the PMOS transistor MP306 is turned on. Therefore, the drain voltage of the PMOS transistor MP306 becomes VDD2 level and is supplied to the NMOS transistor MN311 of the slave latch of the next stage. Further, a signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP305, and the PMOS transistor MP305 is turned off.
[0057]
When the input signal D is at “L” level, the NMOS transistor MN305 is turned off and the NMOS transistor MN306 is turned on. Therefore, the drain voltage of the NMOS transistor MN306 becomes the GND level and is supplied to the NMOS transistor MN311 of the next slave latch. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP305, and the PMOS transistor MP305 is turned on. Therefore, the drain voltage of the PMOS transistor MP305 becomes VDD2 level and is supplied to the NMOS transistor MN312 of the slave latch of the next stage. Further, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP306, and the PMOS transistor MP306 is turned off.
[0058]
In this manner, the master latch operates as a level shift circuit that reads a signal in accordance with the input signal D. In the slave latch, since the NMOS transistor MN313 is in the off state and the NMOS transistor MN312 is in the on state, the input signal D is held at the slave latch as the output signals Q and QN in either case of the “H” level or “L” level. Is output.
[0059]
On the other hand, when the “H” level is input to the input signal VOFF and the “L” level is input to the clock input signal CPN, or when the “L” level is input to the input signal VOFF, the master is used as the output signals Q and QN. • The signal held in the latch is output through the slave latch. In this case, since the output of the NAND circuit becomes “H” level, the NMOS transistors MN307 and MN316 are turned off and the NMOS transistors MN310 and MN313 are turned on.
[0060]
If VDD1 is cut here, the input signal D and its inverted signal are in an unstable state. However, since the NMOS transistor MN307 is in the off state, no static leak current flows from VDD2 to GND. Even when VDD1 is cut, the signal held in the master latch continues to be output through the slave latch, so that the output signals Q and QN are not affected. When the power supply of VDD1 is turned off, the clock supply is stopped before that.
[0061]
Therefore, the present embodiment functions as an enable flip-flop circuit having a level shift function, and even if VDD1 is cut, the output signal is not affected. In addition, when VDD1 is cut, the input signal D that becomes unstable and its inverted signal can be cut off, so that no static leakage current flows. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
(Fourth embodiment)
FIG. 4 is a circuit diagram of a relay macro cell according to the fourth embodiment. This is a clocked inverter having a level shift function. An inverter IN1 to which an input signal A (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an input signal VOFF between VDD2 (first potential) and GND ( The inverter IN2 to which the second input signal) is supplied, a level shift circuit that performs level conversion by the input signal A and the input signal VOFF, an “H” level by the input signal VOFF, its inverted signal, and the output signal of the level shift circuit , “L” level or a clocked inverter that outputs a high impedance signal. The input signal A and its inverted signal are included in the power supply system of VDD1, and the input signal VOFF, its inverted signal, and the output signal Z are included in the power supply system of VDD2.
[0062]
The level shift circuit will be described. The source of the NMOS transistor MN404 (switch element) is connected to GND, and the input signal VOFF is supplied to the gate. The source of the NMOS transistor MN402 is connected to the drain of the NMOS transistor MN404, and the input signal A is supplied to the gate. The source of the NMOS transistor MN403 is connected to the drain of the NMOS transistor MN404, and the inverted signal of the input signal A is supplied to the gate via the inverter IN1 (NMOS transistor MN401, PMOS transistor MP401). The PMOS transistor MP402 has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN402. The PMOS transistor MP403 has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MP403. The gate of the PMOS transistor MP402 is connected to the drains of the PMOS transistor MP403 and the NMOS transistor MN403, and the gate of the PMOS transistor MP403 is connected to the drains of the PMOS transistor MP402 and the NMOS transistor MN402. The drain voltages of the PMOS transistor MP403 and the NMOS transistor MN403 are supplied to the clocked inverter at the next stage.
[0063]
Next, the clocked inverter will be described. PMOS transistors MP406 and MP407 and NMOS transistors MN406 and MN407 are connected in series between VDD2 and GND. The source of the NMOS transistor MN407 is connected to GND, and the input signal VOFF is supplied to the gate. The source of the PMOS transistor MP407 is connected to VDD2, and the inverted signal of the input signal VOFF via the inverter IN2 (NMOS transistor MN405, PMOS transistor MP405) is supplied to the gate. The source of the NMOS transistor MN406 is connected to the drain of the NMOS transistor MN407, and the output signal from the level shift circuit is supplied to the gate. The source of the PMOS transistor MP406 is connected to the drain of the PMOS transistor MP407, the drain is connected to the drain of the NMOS transistor MN406, and the output signal of the level shift circuit is supplied to the gate. Then, drain voltages of the PMOS transistor MP406 and the NMOS transistor MN406 are output as the output signal Z.
[0064]
Next, the operation of this embodiment will be described. When “L” level is input to the input signal VOFF, the output signal Z is fixed to high impedance. In this case, the NMOS transistor MN407 is turned off. Further, the inverted signal (“H” level) of the input signal VOFF via the inverter IN2 is supplied to the gate of the PMOS transistor MP407, and the PMOS transistor MP407 is turned off. That is, since both the PMOS transistor MP407 and the NMOS transistor MN407 are turned off, the output signal Z of the clocked inverter becomes high impedance.
[0065]
At this time, if VDD1 is cut, the input signal A and its inverted signal are in an unstable state. However, since the NMOS transistor MN404 is in the off state, no static leak current flows from VDD2 to GND. Further, since both the PMOS transistor MP407 and the NMOS transistor MN407 are in the off state, even if an unstable output signal is supplied from the level shift circuit, the output signal Z is not affected.
[0066]
On the other hand, when the “H” level is input to the input signal VOFF, it operates as a level shift circuit that can convert the input signal A into the signal level of the output signal Z. Since the input signal VOFF is “H” level, both the PMOS transistor MP407 and the NMOS transistor MN407 of the clocked inverter are turned on. Further, since the input signal VOFF is “H” level, the NMOS transistor MN404 is turned on.
[0067]
Consider a case where the input signal A is at "L" level. At this time, the NMOS transistor MN402 is turned off and the NMOS transistor MN403 is turned on. Then, the drain voltage of the NMOS transistor MN403 becomes the GND level, and a GND level signal is output from the level shift circuit.
[0068]
Further, the GND level (“L” level) is supplied to the gate of the PMOS transistor MP402, the PMOS transistor MP402 is turned on, and the drain voltage of the PMOS transistor MP402 is at the VDD2 level. The PMOS transistor MP403 is supplied with the VDD2 level ("H" level) and is turned off.
[0069]
Since the output signal (“L” level) from the level shift circuit is supplied to the gates of the PMOS transistor MP406 and the NMOS transistor MN406, the PMOS transistor MP406 is turned on and the NMOS transistor MN406 is turned off. Therefore, a VDD2 level signal is output as the output signal Z.
[0070]
Consider a case where the input signal A is at “H” level. The NMOS transistor MN402 is turned on, and the NMOS transistor MN403 is turned off. Then, the drain voltage of the NMOS transistor MN402 becomes the GND level. Then, the GND level (“L” level) is supplied to the gate of the PMOS transistor MP403, and the PMOS transistor MP403 is turned on. Therefore, the drain voltage of the PMOS transistor MP403 becomes the VDD2 level, and the VDD2 level signal is output from the level shift circuit. Further, the VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP402, which is turned off.
[0071]
Since the output signal (“H” level) from the level shift circuit is supplied to the gates of the PMOS transistor MP406 and the NMOS transistor MN406, the PMOS transistor MP406 is turned off and the NMOS transistor MN406 is turned on. Therefore, a GND level signal is output as the output signal Z.
[0072]
Therefore, when the input signal VOFF is at “H” level, it operates as a level shift circuit capable of converting the input signal A into the signal level of the output signal Z.
[0073]
Therefore, this embodiment functions as a clocked inverter having a level shift function, and even if VDD1 is cut, the output signal is not affected. In addition, when VDD1 is cut, the unstable input signal A and its inverted signal can be cut off, so that no static leakage current flows. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
(Fifth embodiment)
FIG. 5 is a circuit diagram of a relay macro cell according to the fifth embodiment. This is a tri-state gate having a level shift function. An inverter IN1 to which an input signal A (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an input signal VOFF between VDD2 (first potential) and GND ( The second input signal) is supplied with the inverter IN2, the input signal A, the input signal VOFF, the two differential circuits controlled by the output signals of the inverters IN1 and IN2, and the output signals of these differential circuits. It consists of two controlled MOS transistors. The input signal A and its inverted signal are included in the power supply system of VDD1, the input signal VOFF and its inverted signal, and the two differential outputs and the output signal Z are included in the power supply system of VDD2.
[0074]
The first differential circuit (first level shift circuit) will be described. The source of the NMOS transistor MN504 (third MOS transistor) is connected to GND, and the input signal VOFF is supplied to the gate. The source of the NMOS transistor MN503 (fourth MOS transistor) is connected to the drain of the NMOS transistor MN504, and the inverted signal of the input signal A is supplied to the gate via the inverter IN1 (NMOS transistor MN501, PMOS transistor MP501). . The NMOS transistor MN505 (first MOS transistor) has a source connected to GND and an input signal A supplied to the gate. The NMOS transistor MN506 (second MOS transistor) has a source connected to GND, a drain connected to the drain of the NMOS transistor MN505, and a gate connected to the input signal VOFF via the inverter IN2 (NMOS transistor MN502, PMOS transistor MP502). An inverted signal is supplied.
[0075]
Also, the PMOS transistor MP503 (fifth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN503. The PMOS transistor MP505 (sixth MOS transistor) has a source connected to VDD2 and a drain connected to the drains of the NMOS transistor MN505 and the NMOS transistor MN506. The gate of the PMOS transistor MP503 is connected to the drains of the PMOS transistor MP505 and NMOS transistors MN505 and MN506, and the gate of the PMOS transistor MP505 is connected to the drains of the PMOS transistor MP503 and NMOS transistor MN503. The drain voltages of the PMOS transistor MP505 and NMOS transistors MN505 and MN506 are output to the next stage.
[0076]
Next, the second differential circuit (second level shift circuit) will be described. The source of the NMOS transistor MN507 (the ninth MOS transistor) is connected to GND, and an inverted signal of the input signal A is supplied to the gate via the inverter IN1. The NMOS transistor MN508 (tenth MOS transistor) has a source connected to GND, a drain connected to the drain of the NMOS transistor MN507, and a gate supplied with an inverted signal of the input signal VOFF via the inverter IN2. The NMOS transistor MN510 (the eleventh MOS transistor) has a source connected to the GND and an input signal VOFF supplied to the gate. The NMOS transistor MN509 (the twelfth MOS transistor) has a source connected to the drain of the NMOS transistor MN510 and an input signal A supplied to the gate.
[0077]
The PMOS transistor MP507 (13th MOS transistor) has a source connected to VDD2 and a drain connected to the drains of the NMOS transistors MN507 and MN508. The PMOS transistor MP509 (fourteenth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN509. The gate of the PMOS transistor MP507 is connected to the drains of the PMOS transistor MP509 and the NMOS transistor MN509, and the gate of the PMOS transistor MP509 is connected to the drains of the PMOS transistor MP507 and the NMOS transistors MN507 and MN508. The drain voltages of the PMOS transistor MP509 and NMOS transistor MN509 are output to the next stage.
[0078]
Next, two MOS transistors that receive outputs from the first and second differential circuits will be described. A PMOS transistor MP511 (eighth MOS transistor) and an NMOS transistor MN511 (seventh MOS transistor) are connected in series between VDD2 and GND. The source of the NMOS transistor MN511 is connected to GND, and the output signal from the first differential circuit is supplied to the gate. The PMOS transistor MP511 has a source connected to VDD2, a drain connected to the drain of the NMOS transistor MN511, and a gate supplied with an output signal from the second differential circuit. Then, drain voltages of the PMOS transistor MP511 and the NMOS transistor MN511 are output as the output signal Z.
[0079]
Note that the input signals supplied to the gates of the NMOS transistors MN503 and MN504 may be reversed. That is, the input signal VOFF may be supplied to the gate of the NMOS transistor MN503, and the inverted signal of the input signal A may be supplied to the gate of the NMOS transistor MN504. Similarly, the input signal VOFF may be supplied to the gate of the NMOS transistor MN509, and the input signal A may be supplied to the gate of the NMOS transistor MN510.
[0080]
Next, the operation of this embodiment will be described. When “L” level is input to the input signal VOFF, the output signal Z is fixed to high impedance. The NMOS transistor MN504 of the first differential circuit is turned off, and the NMOS transistor MN506 is turned on. Therefore, the drain voltage of the NMOS transistor MN506 is at the GND level, and a signal at the GND level is output from the first differential circuit.
[0081]
Further, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP503, and the PMOS transistor MP503 is turned on. Then, the drain voltage of the PMOS transistor MP503 becomes the VDD2 level, the VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP505, and the PMOS transistor MP505 is turned off.
[0082]
On the other hand, the NMOS transistor MN508 of the second differential circuit is turned on, and the NMOS transistor MN510 is turned off. Therefore, the drain voltage of the NMOS transistor MN508 is at the GND level. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP509, and the PMOS transistor MP509 is turned on. Then, the drain voltage of the PMOS transistor MP509 becomes the VDD2 level, and the VDD2 level signal is output from the second differential circuit. Further, a signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP507, and the PMOS transistor MP507 is turned off.
[0083]
The NMOS transistor MN511 is supplied with a GND level signal from the first differential circuit and is turned off. On the other hand, the PMOS transistor MP511 is supplied with a VDD2 level signal from the second differential circuit and is turned off. Since both are turned off, the output signal Z becomes high impedance.
[0084]
Therefore, the NMOS transistors MN503 and MN509 operated by the input signal A are cut off when the NMOS transistors MN504 and MN510 are turned off when the input signal VOFF is “L” level. Therefore, when the input signal VOFF is “L” level, even if VDD1 including the input signal A is cut, the NMOS transistors MN506 and MN508 are turned on, so that the output signal supplied to the next-stage MOS transistor is The first differential circuit is fixed to the “L” level, and the second differential circuit is fixed to the “H” level.
[0085]
When the input signal VOFF is “L” level, the NMOS transistors MN506 and MN508 are turned on, so that the drains of the NMOS transistors MN505 and MN507 are at the GND level, and the NMOS transistors MN504 and MN510 are turned off. . Therefore, even if the input signal A and its inverted signal become unstable after turning off VDD1, no static leakage current flows from VDD2 to GND.
[0086]
When the “H” level is input to the input signal VOFF, it operates as a level shift circuit that can convert the input signal A into the signal level of the output signal Z. The NMOS transistor MN504 of the first differential circuit is turned on, and the NMOS transistor MN506 is turned off. Further, the NMOS transistor MN508 of the second differential circuit is turned off, and the NMOS transistor MN510 is turned on.
[0087]
Consider a case where the input signal A is at "L" level. The NMOS transistor MN505 of the first differential circuit is turned off, and the NMOS transistor MN503 is turned on. Accordingly, both the NMOS transistors MN503 and MN504 are turned on, so that the drain voltage of the NMOS transistor MN503 is at the GND level. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP505, and the PMOS transistor MP505 is turned on. Then, the drain voltage of the PMOS transistor MP505 becomes the VDD2 level, and the VDD2 level signal is output from the first differential circuit. Further, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP503, and the PMOS transistor MP503 is turned off.
[0088]
The NMOS transistor MN507 of the second differential circuit is turned on, and the NMOS transistor MN509 is turned off. Therefore, the drain voltage of the NMOS transistor MN507 is at the GND level. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP509, and the PMOS transistor MP509 is turned on. Then, the drain voltage of the PMOS transistor MP509 becomes the VDD2 level, and the VDD2 level signal is output from the second differential circuit. Further, a signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP507, and the PMOS transistor MP507 is turned off.
[0089]
The NMOS transistor MN511 is turned on when a signal of VDD2 level is supplied from the first differential circuit. On the other hand, the PMOS transistor MP511 is supplied with a VDD2 level signal from the second differential circuit and is turned off. Therefore, a GND level signal is output as the output signal Z.
[0090]
Consider a case where the input signal A is at “H” level. The NMOS transistor MN503 of the first differential circuit is turned off, and the NMOS transistor MN505 is turned on. Therefore, the drain voltage of the NMOS transistor MN505 is at the GND level, and a signal at the GND level is output from the first differential circuit. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP503, and the PMOS transistor MP503 is turned on. Then, the drain voltage of the PMOS transistor MP503 becomes the VDD2 level. A signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP505, and the PMOS transistor MP505 is turned off.
[0091]
The NMOS transistor MN507 of the second differential circuit is turned off, and the NMOS transistor MN509 is turned on. Therefore, since both the NMOS transistors MN509 and MN510 are turned on, the drain voltage of the NMOS transistor MN509 is at the GND level, and a signal at the GND level is output from the second differential circuit.
[0092]
Further, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP507, and the PMOS transistor MP507 is turned on. Then, the drain voltage of the PMOS transistor MP507 becomes the VDD2 level. A signal of VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP509, and the PMOS transistor MP509 is turned off.
[0093]
The NMOS transistor MN511 is supplied with a GND level signal from the first differential circuit and is turned off. On the other hand, the PMOS transistor MP511 is turned on when the GND level signal is supplied from the second differential circuit. Therefore, a VDD2 level signal is output as the output signal Z.
[0094]
The truth table in the fifth embodiment is shown in Table 1 below.
[0095]
[Table 1]

[0096]
Therefore, when the input signal VOFF is at “H” level, the present embodiment operates as a level shift circuit.
[0097]
Therefore, this embodiment functions as a tri-state gate having a level shift function, and the output signal is not affected even if VDD1 is cut. In addition, when VDD1 is cut, the unstable input signal A and its inverted signal can be cut off, so that no static leakage current flows. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
(Sixth embodiment)
FIG. 6 is a circuit diagram of a relay macro cell according to the sixth embodiment. This is a combination of two latches having a level shift function and a clocked inverter. An inverter IN1 to which an input signal A (first input signal) is supplied between VDD1 (third potential) and GND (second potential) and an inverter IN2 to which an enable signal E (third input signal) is supplied An inverter IN3 to which an input signal VOFF (second input signal) is supplied between VDD2 (first potential) and GND, two latches controlled by these signals and their inverted signals, and an output of this latch It consists of a clocked inverter controlled by a signal. The input signal A and the enable signal E and their inverted signals are included in the power supply system of VDD1, and the input signal VOFF, its inverted signal, and the output signal Z are included in the power supply system of VDD2.
[0098]
The first latch (first level shift circuit, first holding circuit) outputs a signal corresponding to the input signal A. The source of the NMOS transistor MN606 (first MOS transistor) is connected to GND, and the input signal VOFF is supplied to the gate. The source of the NMOS transistor MN604 (third MOS transistor) is connected to the drain of the NMOS transistor MN606, and the input signal A is supplied to the gate. The source of the NMOS transistor MN605 (fourth MOS transistor) is connected to the drain of the NMOS transistor MN606, and the inverted signal of the input signal A is supplied to the gate via the inverter IN1 (NMOS transistor MN601, PMOS transistor MP601). . The PMOS transistor MP604 (fifth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN604. The PMOS transistor MP605 (sixth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN605. The gate of the PMOS transistor MP604 is connected to the drains of the PMOS transistor MP605 and NMOS transistor MN605, and the gate of the PMOS transistor MP605 is connected to the drains of the PMOS transistor MP604 and NMOS transistor MN604.
[0099]
The source of the NMOS transistor MN609 (second MOS transistor) is connected to GND, and the inverted signal of the input signal VOFF via the inverter IN3 (NMOS transistor MN603, PMOS transistor MP603) is supplied to the gate. The NMOS transistor MN607 (seventh MOS transistor) has a source connected to the drain of the NMOS transistor MN609, a drain connected to the drains of the PMOS transistor MP604 and the NMOS transistor MN604, and a gate connected to the drains of the PMOS transistor MP605 and the NMOS transistor MN605. It is connected. The NMOS transistor MN608 (eighth MOS transistor) has a source connected to the drain of the NMOS transistor MN609, a drain connected to the drains of the PMOS transistor MP605 and the NMOS transistor MN605, and a gate connected to the drains of the PMOS transistor MP604 and the NMOS transistor MN604. It is connected.
[0100]
Then, the drain voltages of the PMOS transistor MP605 and the NMOS transistors MN605 and MN608 are output to the subsequent clocked inverter as the output signal of the first latch.
[0101]
The second latch outputs a signal corresponding to the enable signal E. The source of the NMOS transistor MN612 is connected to GND, and the input signal VOFF is supplied to the gate. The source of the NMOS transistor MN610 is connected to the drain of the NMOS transistor MN612, and the enable signal E is supplied to the gate. The source of the NMOS transistor MN611 is connected to the drain of the NMOS transistor MN612, and the inverted signal of the enable signal E is supplied to the gate via the inverter IN2 (NMOS transistor MN602, PMOS transistor MP602).
[0102]
The PMOS transistor MP610 has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN610. The PMOS transistor MP611 has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN611. The gate of the PMOS transistor MP610 is connected to the drains of the PMOS transistor MP611 and the NMOS transistor MN611, and the gate of the PMOS transistor MP611 is connected to the drains of the PMOS transistor MP610 and the NMOS transistor MN610.
[0103]
Further, the source of the NMOS transistor MN615 is connected to GND, and the inverted signal of the input signal VOFF via the inverter IN3 is supplied to the gate. The NMOS transistor MN613 has a source connected to the drain of the NMOS transistor MN615, a drain connected to the drains of the PMOS transistor MP610 and the NMOS transistor MN610, and a gate connected to the drains of the PMOS transistor MP611 and the NMOS transistor MN611. The NMOS transistor MN614 has a source connected to the drain of the NMOS transistor MN615, a drain connected to the drains of the PMOS transistor MP611 and the NMOS transistor MN611, and a gate connected to the drains of the PMOS transistor MP610 and the NMOS transistor MN610.
[0104]
Then, as the output signal of the second latch, the drain voltages of the PMOS transistor MP611 and the NMOS transistors MN611 and MN614 are output to the subsequent clocked inverter. Further, the drain voltage of the PMOS transistor MP610 and the NMOS transistors MN610 and MN613 is output to the clocked inverter at the subsequent stage as an inverted signal of the output signal of the second latch.
[0105]
The clocked inverter will be described. PMOS transistors MP616, MP617 and NMOS transistors MP616, MN617 are connected in series between VDD2 and GND. The source of the PMOS transistor MP617 is connected to VDD2, and the inverted signal of the output signal from the second latch is supplied to the gate. The source of the NMOS transistor MN617 is connected to GND, and the output signal from the second latch is supplied to the gate. The source of the PMOS transistor MP616 is connected to the drain of the PMOS transistor MP617, and the output signal from the first latch is supplied to the gate. The NMOS transistor MN616 has a source connected to the drain of the NMOS transistor MN617, a drain connected to the drain of the PMOS transistor MP616, and a gate supplied with an output signal from the first latch. As the output signal Z, drain voltages of the PMOS transistor MP616 and the NMOS transistor MN616 are output.
[0106]
Next, the operation of this embodiment will be described. When the “H” level is input to the input signal VOFF, it operates as a level shift circuit that converts the signal levels of the input signal A and the enable signal E and outputs a signal to the output signal Z. Since the input signal VOFF is “H” level, the NMOS transistor MN606 and the NMOS transistor MN612 are turned on, and the NMOS transistor MN609 and the NMOS transistor MN615 are turned off.
[0107]
Consider a case where the input signal A is at “H” level. The NMOS transistor MN604 of the first latch is turned on, and the NMOS transistor MN605 is turned off. Therefore, the drain voltage of the NMOS transistor MN604 is at the GND level. Then, a GND level (“L” level) signal is supplied to the gate of the PMOS transistor MP605, and the PMOS transistor MP605 is turned on. Then, the drain voltage of the PMOS transistor MP605 becomes the VDD2 level, and is output to the clocked inverter at the next stage as the output signal of the first latch. Further, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP604, and the PMOS transistor MP604 is turned off.
[0108]
When the enable signal E is at the “H” level, the second latch operates in the same manner. The VDD2 level (“H” level) signal is output as the output signal of the second latch, and the GND level ( The “L” level signal is supplied to the clocked inverter at the next stage.
[0109]
At this time, since the NMOS transistors MN616 and MN617 are turned on, the clocked inverter outputs a signal of GND level (“L” level) as the output signal Z.
[0110]
Consider a case where the input signal A is at "L" level. The NMOS transistor MN604 is turned off and the NMOS transistor MN605 is turned on. Therefore, the drain voltage of the NMOS transistor MN605 becomes the GND level and is output to the clocked inverter at the next stage. Then, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP604, and the PMOS transistor MP604 is turned on. Then, the drain voltage of the PMOS transistor MP604 becomes the VDD2 level, the VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP605, and the PMOS transistor MP605 is turned off.
[0111]
At this time, since the PMOS transistors MP616 and MP617 are turned on, the clocked inverter outputs a signal of VDD2 level (“H” level) as the output signal Z.
[0112]
When the enable signal E is at “L” level, a signal at GND level (“L” level) is output from the second latch, and a signal at VDD2 level (“H” level) is output as an inverted signal of the output signal. It is supplied to the clocked inverter at the next stage.
[0113]
At this time, since both the PMOS transistor MP617 and the NMOS transistor MN617 are turned off, the clocked inverter outputs a high impedance signal as the output signal Z.
[0114]
On the other hand, when the “L” level is input to the input signal VOFF, the NMOS transistors MN606 and MN612 are turned off and the NMOS transistors MN609 and MN615 are turned on. Since the first latch and the second latch hold signals corresponding to the input signal A and the enable signal E when the “H” level is input to the input signal VOFF, the signals are output even when VDD1 is cut. The signal Z continues to output “H” level (VDD2 level), “L” level (GND level), or high impedance.
[0115]
The truth table in the sixth embodiment is shown in Table 2 below. “X” in Table 2 is “H” or “L”.
[0116]
[Table 2]

[0117]
If VDD1 is cut when the input signal VOFF is at "L" level, the input signal A, the enable signal E and their inverted signals are in an unstable state. However, since the NMOS transistors MN606 and MN612 are in the off state, no static leakage current flows from VDD2 to GND. Even when VDD1 is turned off, the first and second latches continue to output the held signals, so there is no effect on the output signals of these two latches and their inverted signals.
[0118]
Therefore, this embodiment functions as a clocked inverter having a level shift function, and even if VDD1 is cut, the output signal is not affected. In addition, since the input signal A, the enable signal E, and their inverted signals that become unstable when VDD1 is cut off, the static leak current does not flow. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted. (Seventh embodiment)
FIG. 7 is a circuit diagram of a relay macrocell according to the seventh embodiment. This is a tri-state gate having two latches having a level shift function. An inverter IN1 to which an input signal A (first input signal) is supplied between VDD1 (third potential) and GND (second potential), and an inverter to which an enable signal E (second input signal) is supplied IN2, an inverter IN3 to which an input signal VOFF (third input signal) is supplied between VDD2 (first potential) and GND, two latches controlled by these input signals and their inverted signals, and this latch It is composed of two MOS transistors controlled by the output signal. The input signals A and E and their inverted signals are included in the VDD1 power supply system, and the input signal VOFF, its inverted signal, two latches, and the output signal Z are included in the VDD2 power supply system.
[0119]
The first latch (first level shift circuit, first holding circuit) will be described. The source of the NMOS transistor MN708 (first switch element) is connected to GND, and the input signal VOFF is supplied to the gate. The NMOS transistor MN704 (third MOS transistor) has a source connected to the drain of the NMOS transistor MN708 and a gate supplied with an inverted signal of the input signal A via the inverter IN1 (NMOS transistor MN701, PMOS transistor MP701). . In the NMOS transistor MN705 (fourth MOS transistor), the source is connected to the drain of the NMOS transistor MN708, the drain is connected to the drain of the NMOS transistor MN704, and the gate is connected to the inverter IN2 (NMOS transistor MN702, PMOS transistor MP702). An inverted signal of the enable signal E is supplied.
[0120]
The NMOS transistor MN707 (fifth MOS transistor) has a source connected to the drain of the NMOS transistor MN708 and an enable signal E supplied to the gate. The source of the NMOS transistor MN706 (sixth MOS transistor) is connected to the drain of the NMOS transistor MN707, and the input signal A is supplied to the gate.
[0121]
The PMOS transistor MP704 (seventh MOS transistor) has a source connected to VDD2 and a drain connected to the drains of the NMOS transistors MN704 and MN705. The PMOS transistor MP706 (eighth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN706. The gate of the PMOS transistor MP704 is connected to the drains of the PMOS transistor MP706 and NMOS transistor MN706, and the gate of the PMOS transistor MP706 is connected to the drains of the PMOS transistor MP704 and NMOS transistors MN704 and MN705.
[0122]
The NMOS transistor MN711 (third switch element) has a source connected to the GND and a gate supplied with an inverted signal of the input signal VOFF via the inverter IN3 (NMOS transistor MN703, PMOS transistor MP703). The NMOS transistor MN709 (the ninth MOS transistor) has a source connected to the drain of the NMOS transistor MN711, a drain connected to the drains of the PMOS transistor MP704 and the NMOS transistors MN704 and MN705, and gates connected to the PMOS transistor MP706 and the NMOS transistor MN706. Connected to the drain. The NMOS transistor MN710 (tenth MOS transistor) has a source connected to the drain of the NMOS transistor MN711, a drain connected to the drains of the PMOS transistor MP706 and the NMOS transistor MN706, and a gate connected to the PMOS transistor MP704 and the NMOS transistors MN704 and MN705. Connected to the drain.
[0123]
Then, the drain voltages of the PMOS transistor MP706 and NMOS transistors MN706 and MN710 are output to the next stage as the output signal of the first latch.
[0124]
Next, the second latch (second level shift circuit, second holding circuit) will be described. The source of the NMOS transistor MN716 (second switch element) is connected to GND, and the input signal VOFF is supplied to the gate. The source of the NMOS transistor MN713 (the eleventh MOS transistor) is connected to the drain of the NMOS transistor MN716, and the enable signal E is supplied to the gate. The source of the NMOS transistor MN712 (the twelfth MOS transistor) is connected to the drain of the NMOS transistor MN713, and the inverted signal of the input signal A via the inverter IN1 is supplied to the gate.
[0125]
The NMOS transistor MN714 (the 13th MOS transistor) has a source connected to the drain of the NMOS transistor MN716 and an input signal A supplied to the gate. The NMOS transistor MN715 (fourteenth MOS transistor) has a source connected to the drain of the NMOS transistor MN716, a drain connected to the drain of the NMOS transistor MN714, and a gate supplied with an inverted signal of the enable signal E via the inverter IN2. ing.
[0126]
The PMOS transistor MP712 (fifteenth MOS transistor) has a source connected to VDD2 and a drain connected to the drain of the NMOS transistor MN712. The PMOS transistor MP714 (sixteenth MOS transistor) has a source connected to VDD2 and a drain connected to the drains of the NMOS transistors MN714 and MN715. The gate of the PMOS transistor MP712 is connected to the drains of the PMOS transistor MP714 and NMOS transistors MN714 and MN715, and the gate of the PMOS transistor MP714 is connected to the drains of the PMOS transistor MP712 and NMOS transistor MN712.
[0127]
The NMOS transistor MN721 (fourth switch element) has a source connected to the GND and a gate supplied with an inverted signal of the input signal VOFF via the inverter IN3. The NMOS transistor MN718 (17th MOS transistor) has a source connected to the drain of the NMOS transistor MN721, and a gate connected to the drains of the PMOS transistor MP706 and NMOS transistors MN706 and MN710 of the first latch. The NMOS transistor MN717 (18th MOS transistor) has a source connected to the drain of the NMOS transistor MN718, a drain connected to the drains of the PMOS transistor MP712 and the NMOS transistor MN712, and a gate connected to the PMOS transistor MP714 and the NMOS transistors MN714 and MN715. Connected to the drain.
[0128]
The NMOS transistor MN719 (19th MOS transistor) has a source connected to the drain of the NMOS transistor MN721 and a gate connected to the drains of the PMOS transistor MP712 and NMOS transistors MN712 and MN717. The NMOS transistor MN720 (the twentieth MOS transistor) has a source connected to the drain of the NMOS transistor MN721, a drain connected to the drains of the PMOS transistor MP714 and NMOS transistors MN714, MN715, and MN719, and a gate connected to the PMOS of the first latch. The transistor MP704 and NMOS transistors MN704, MN705 and MN709 are connected to the drains.
[0129]
Then, as the output signal of the second latch, the drain voltages of the PMOS transistor MP714 and the NMOS transistors MN714, MN715 and MN717 are output to the next stage.
[0130]
Next, two MOS transistors that receive outputs from the first and second latches will be described. A PMOS transistor MP722 (first MOS transistor) and an NMOS transistor MN722 (second MOS transistor) are connected in series between VDD2 and GND. The source of the PMOS transistor MP722 is connected to VDD2, and the output signal of the first latch is supplied to the gate. The NMOS transistor MN722 has a source connected to the GND, a drain connected to the drain of the PMOS transistor MP722, and a gate supplied with the output signal of the second latch. Then, drain voltages of the PMOS transistor MP722 and the NMOS transistor MN722 are output as the output signal Z.
[0131]
Next, the operation of this embodiment will be described. When the “H” level is input to the input signal VOFF, it operates as a level shift circuit that converts the signal levels of the input signals A and E and outputs a signal to the output signal Z. Since the input signal VOFF is “H” level, the NMOS transistors MN708 and MN716 are turned on, and the NMOS transistors MN711 and MN721 are turned off.
[0132]
Consider a case where the input signal A and the enable signal E are at “H” level. The NMOS transistors MN704 and MN705 of the first latch are turned off, and the NMOS transistors MN706 and N707 are turned on. Therefore, the drain voltage of the NMOS transistor MN706 becomes the GND level, and the GND level signal is supplied to the next stage as the output signal of the first latch.
[0133]
Further, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP704, and the PMOS transistor MP704 is turned on. Then, the drain voltage of the PMOS transistor MP704 becomes the VDD2 level (“H” level). Then, a VDD2 level (“H” level) signal is supplied to the gate of the PMOS transistor MP706, and the PMOS transistor MP706 is turned off.
[0134]
On the other hand, the NMOS transistors MN712 and MN715 of the second latch are turned off, and the NMOS transistors MN713 and MN714 are turned on. Therefore, the drain voltages of the NMOS transistors MN714 and MN715 are at the GND level, and the GND level signal is supplied to the next stage as the output signal of the second latch.
[0135]
Further, a signal of GND level (“L” level) is supplied to the gate of the PMOS transistor MP712, and the PMOS transistor MP712 is turned on. Then, the drain voltage of the PMOS transistor MP712 becomes VDD2 level ("H" level). The VDD2 level (“H” level) is supplied to the gate of the PMOS transistor MP714, and the PMOS transistor MP714 is turned off.
[0136]
Then, a signal of the GND level (“L” level) is supplied from the first latch to the gate of the PMOS transistor MP722 to be turned on. On the other hand, a signal of the GND level (“L” level) is supplied from the second latch to the gate of the NMOS transistor MN722, and the NMOS transistor MN722 is turned off. Therefore, a VDD2 level signal is output as the output signal Z.
[0137]
On the other hand, when the “L” level is input to the input signal VOFF, the signals corresponding to the input signal A and the enable signal E when the “H” level is input to the input signal VOFF are the first and second latches. Therefore, the output signal Z continues to output “H” level, “L” level, or high impedance. Since the input signal VOFF is at the “L” level, the NMOS transistors MN708 and MN716 are turned off and the NMOS transistors MN711 and MN721 are turned on.
[0138]
At this time, the second latch has a reset function (NMOS transistors MN718 and MN720) so that both the PMOS transistor MP722 and the NMOS transistor MN722 are not turned on. When the output signal of the first latch holds the “L” level as the input signal of the gate of the PMOS transistor MP722, the output signal of the second latch holds the signal held as the input signal of the gate of the NMOS transistor MN722 as “L”. “Reset to level. That is, the NMOS transistor MN718 is turned off to be cut off, the NMOS transistor MN720 is turned on, and the drain voltage of the NMOS transistor MN720, that is, the output signal Q2 is set to the GND level (“L” level), thereby the NMOS transistor MN722. The input signal to is set to the “L” level state.
[0139]
Accordingly, both the PMOS transistor MP722 and the NMOS transistor MN722 are not turned on, and the output signal Z continues to output “H” level, “L” level, or high impedance.
[0140]
The truth table of the seventh embodiment is shown in Table 3 below. “X” in Table 3 is “H” or “L”.
[0141]
[Table 3]

[0142]
If VDD1 is cut when the input signal VOFF is at "L" level, the input signal A, the enable signal E and their inverted signals are in an unstable state. However, since the NMOS transistors MN708 and MN716 are in the off state, no static leakage current flows from VDD2 to GND. Even when VDD1 is turned off, both the output stage MOS transistors are not turned on, and the first and second latches continue to output the held signals, so the output signal Z is not affected.
[0143]
Therefore, this embodiment functions as a tri-state gate having a level shift function, and the output signal is not affected even if VDD1 is cut. In addition, since the input signal A, the enable signal E, and their inverted signals that become unstable when VDD1 is cut off, the static leak current does not flow. Further, it is possible to prevent an increase in static leakage current not only when the power supply voltage is intentionally different but also when the voltage between the power supply systems supplying the same voltage is shifted.
(Eighth embodiment)
FIG. 8 is a block diagram of a semiconductor integrated circuit incorporating the relay macrocell of the present invention. The relay macrocell according to the embodiment described above is incorporated between circuit blocks.
[0144]
The circuit block B1 operates at VDD1, and the circuit block B2 operates at VDD2. Relay macrocells T1 and T2 are incorporated between circuit blocks B1 and B2. The relay macrocell T1 operates as a level shift circuit that receives the input signal VOFF1 included in the power supply system of VDD2 and converts the signal level from VDD1 to VDD2. The relay macrocell T2 operates as a level shift circuit that receives the input signal VOFF2 included in the power supply system of VDD1 and converts the signal level from VDD2 to VDD1. The relay macro cell to be incorporated between the circuit blocks selects the first to seventh embodiments according to the input signal and the output signal.
[0145]
Note that the semiconductor integrated circuit of FIG. 8 may be arranged on the same chip or on different chips. When disposing on separate chips, a relay macro cell may be disposed on the input side or output side of the circuit blocks B1 and B2. For example, the circuit block B1 and the relay macro cell T1 are arranged on the same chip, and the circuit block B2 and the relay macro cell T2 are arranged on the same chip. The output signal from the relay macro cell T1 is input to the circuit block B2, and the output signal from the relay macro cell T2 is input to the circuit block B1.
[0146]
In this embodiment, regardless of whether the power supply voltage is different, not only the level shift of the signal between circuit blocks of different power supply systems but also the case where the voltage is slightly different between systems even with the same power supply voltage. The signal level is converted, and an increase in static leakage current can be prevented. In addition, even if some of the power supply systems are turned off and the signal of the circuit block receiving power supply from that system becomes unstable, the signal is interrupted and the operation of the circuit block that is turned on is affected. Can be prevented.
[0147]
【The invention's effect】
By using the macro cell for relay of the present invention, even if the signal of the circuit block receiving power supply from the power system becomes unstable, the operation of the circuit block that is turned on is affected. Can be prevented.
[0148]
The signal level is converted by using the relay macro cell of the present invention not only for the level shift of the signal between circuit blocks with different power supply voltages but also for the case where the voltage is slightly different between systems even with the same power supply voltage. Thus, an increase in static leakage current can be prevented.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a relay macro cell according to a first embodiment.
FIG. 2 is a circuit diagram of a relay macro cell according to a second embodiment.
FIG. 3 is a circuit diagram of a relay macro cell according to a third embodiment.
FIG. 4 is a circuit diagram of a relay macro cell according to a fourth embodiment.
FIG. 5 is a circuit diagram of a relay macro cell according to a fifth embodiment.
FIG. 6 is a circuit diagram of a relay macro cell according to a sixth embodiment.
FIG. 7 is a circuit diagram of a relay macro cell according to a seventh embodiment.
FIG. 8 is a block diagram of a semiconductor integrated circuit incorporating the relay macrocell of the present invention.
FIG. 9 is a circuit diagram of a conventional semiconductor device.
FIG. 10 is a circuit diagram of a conventional semiconductor device.
[Explanation of symbols]
MP101 to MP905 ... PMOS transistors
MN101 to MN906 ... NMOS transistors
A, D, VOFF ... Input signal
E ... Enable signal
CPN ... Clock input signal
Z, Q, QN ... Output signal
B1, B2 ... circuit block
T1, T2 ... Macro cell for relay

Claims (19)

A first power source that is a first potential;
A second power source that is a second potential;
Having a first current path and a second current path connected between the first power supply and the second power supply, connected to the second power supply side of the first current path; A first switch circuit controlled by a first input signal that is a third potential or a ground potential and a second input signal that is the first potential or the ground potential; and the first switch circuit of the second current path. A first level shift circuit which is connected to the power source side of the first input signal and includes a second switch circuit controlled by an inverted signal of the first input signal and an inverted signal of the second input signal;
A relay macrocell comprising: The first switch circuit includes:
A one-conductivity-type first MOS transistor having a source connected to the second power supply and a gate supplied with the first input signal;
A source having a source connected to the second power source, a drain connected to the drain of the first MOS transistor, and a gate having the second input signal supplied to the gate; The relay macrocell according to claim 1, wherein the relay macrocell is a relay macrocell. The second switch circuit includes:
A third MOS transistor of one conductivity type, the source of which is connected to the second power supply and the inverted signal of the second input signal is supplied to the gate;
The fourth MOS transistor having one conductivity type, the source of which is connected to the drain of the third MOS transistor and the inverted signal of the first input signal is supplied to the gate of the third MOS transistor. 3. The macro cell for relay according to 1 or 2. The first current path is:
The first switch circuit;
A fifth MOS of reverse conductivity type having a source connected to the first power supply, a drain connected to the drains of the first and second MOS transistors, and a gate connected to the drain of the fourth MOS transistor Composed of transistors,
The second current path is:
The second switch circuit;
A reverse-conductivity type second source having a source connected to the first power supply, a drain connected to the drain of the fourth MOS transistor, and a gate connected to the drains of the first, second and fifth MOS transistors. The relay macrocell according to claim 3, wherein the relay macrocell is composed of six MOS transistors. A first output signal line connected to the first current path;
A third current path and a fourth current path connected between the first power supply and the second power supply, and connected to the second power supply side of the third current path; The first input signal is connected to the third switch circuit controlled by the inverted signal of the first input signal and the second input signal, and to the second power supply side of the fourth current path. A second level shift circuit comprising: a fourth switch circuit controlled by an inverted signal of the second input signal;
A second output signal line connected to the fourth current path;
A seventh MOS transistor of one conductivity type having a source connected to the second power supply and a gate connected to the first output signal line;
An eighth MOS transistor of reverse conductivity type having a source connected to the first power supply, a drain connected to the drain of the seventh MOS transistor, and a gate connected to the second output signal line;
5. The relay macro cell according to claim 1, further comprising a third output signal line connected to drains of the seventh and eighth MOS transistors. The third switch circuit includes:
A first conductivity type ninth MOS transistor having a source connected to the second power supply and a gate supplied with an inverted signal of the first input signal;
And a tenth MOS transistor of one conductivity type having a source connected to the second power supply, a drain connected to the drain of the ninth MOS transistor, and a gate supplied with the second input signal. The relay macro cell according to claim 5, wherein the relay macro cell is a relay macro cell. The fourth switch circuit includes:
An eleventh MOS transistor of one conductivity type whose source is connected to the second power supply and whose gate is supplied with the inverted signal of the second input signal;
7. The twelfth MOS transistor of one conductivity type, the source of which is connected to the drain of the eleventh MOS transistor and the first input signal is supplied to the gate of the eleventh MOS transistor. The macro cell for relay described. The third current path is:
The third switch circuit;
A reverse conductivity type thirteenth MOS having a source connected to the first power supply, a drain connected to the drains of the ninth and tenth MOS transistors, and a gate connected to the drain of the twelfth MOS transistor Consisting of transistors,
The fourth current path is:
The fourth switch circuit;
A reverse-conductivity type first electrode having a source connected to the first power supply, a drain connected to the drain of the twelfth MOS transistor, and a gate connected to the drains of the ninth, tenth and thirteenth MOS transistors. 8. The relay macro cell according to claim 7, comprising 14 MOS transistors. A first power source that is a first potential;
A second power source that is a second potential;
A first level shift circuit which is connected to the first power supply and receives a first input signal which is a third potential or a ground potential and an inverted signal thereof;
A first holding circuit for holding an output of the first level shift circuit;
A first switch element connected between the first level shift circuit and the second power supply;
A second switch element connected between the first holding circuit and the second power supply;
The first switch element is controlled by a second input signal that is the first potential or the ground potential,
The second switch element is controlled by an inverted signal of the second input signal,
The relay macrocell, wherein the second switch element is turned on when the first switch element is turned off. A third input signal that is connected to the first power supply and receives the third potential or the ground potential, and a second level shift circuit that receives the inverted signal;
A second holding circuit for holding the output of the second level shift circuit;
A third switch element connected between the second level shift circuit and the second power supply;
A fourth switch element connected between the second holding circuit and the second power source;
The third switch element is controlled by the second input signal;
The fourth switch element is controlled by an inverted signal of the second input signal,
The relay macrocell according to claim 9, wherein when the third switch element is in an off state, the fourth switch element is in an on state. The second input signal is:
11. The relay macro cell according to claim 9, wherein the relay macro cell is an output signal of a NAND circuit that receives a clock signal and a fourth input signal that is the first potential or the ground potential. The third input signal is:
12. The relay macro cell according to claim 10, wherein the relay macro cell is an output signal of the first level shift circuit or the first holding circuit. The clocked inverter to which the output signals of the first and second level shift circuits or the output signals of the first and second holding circuits are supplied is provided. Macro cell for relay. The first switch element includes:
A one-conductivity-type first MOS transistor having a source connected to the second power supply, a drain connected to the first level shift circuit, and a gate supplied with the second input signal;
The second switch element is
A one-conductivity-type second MOS transistor having a source connected to the second power supply, a drain connected to the first holding circuit, and a gate supplied with an inverted signal of the second input signal; 14. The relay macro cell according to claim 9, wherein the relay macro cell is a relay macro cell. The first level shift circuit includes:
A third MOS transistor of one conductivity type whose source is connected to the drain of the first MOS transistor and whose first input signal is supplied to the gate;
A first conductivity type fourth MOS transistor having a source connected to a drain of the first MOS transistor and a gate supplied with an inverted signal of the first input signal;
A reverse-conductivity-type fifth MOS transistor having a source connected to the first power supply, a drain connected to the drain of the third MOS transistor, and a gate connected to the drain of the fourth MOS transistor;
A reverse conductivity type sixth MOS having a source connected to the first power supply, a drain connected to the drain of the fourth MOS transistor, and a gate connected to the drains of the third and fifth MOS transistors Composed of transistors,
The first holding circuit includes:
One conductivity source connected to the drain of the second MOS transistor, drain connected to the drains of the third and fifth MOS transistors, and gate connected to the drains of the fourth and sixth MOS transistors A seventh MOS transistor of the type;
One conductivity source connected to the drain of the second MOS transistor, drain connected to the drains of the fourth and sixth MOS transistors, and gate connected to the drains of the third and fifth MOS transistors 15. The relay macrocell according to claim 14, wherein the relay macrocell is composed of an eighth type MOS transistor. A first power source that is a first potential;
A second power source that is a second potential;
A level shift circuit connected to the first power supply and to which a first input signal which is a third potential or a ground potential and an inverted signal thereof are input;
A switch element connected between the level shift circuit and the second power supply and controlled by a second input signal which is the first potential or the ground potential;
A relay macrocell comprising: an output signal of the level shift circuit; the second input signal; and a clocked inverter supplied with the inverted signal. A first power source that is a first potential;
A second power source that is a second potential;
A first level shift circuit connected to the first power supply, to which first and second input signals having a third potential and the inverted signals thereof are input;
A first holding circuit connected to the first level shift circuit and holding an output signal of the first level shift circuit;
A second level shift circuit connected to the first power source, to which the first and second input signals and their inverted signals are input;
A second holding circuit connected to the first and second level shift circuits and holding an output signal of the second level shift circuit;
A first switch element connected between the first level shift circuit and the second power supply;
A second switch element connected between the second level shift circuit and the second power source;
A third switch element connected between the first holding circuit and the second power source;
A fourth switch element connected between the second holding circuit and the second power source;
A one-conductivity-type first MOS transistor having a source connected to the first power supply and a gate supplied with an output signal of the first level shift circuit or the first holding circuit;
Reverse conduction in which a source is connected to the second power supply, a drain is connected to a drain of the first MOS transistor, and an output signal of the second level shift circuit or the second holding circuit is supplied to a gate A second MOS transistor of the type,
The first and second switch elements are controlled by a third input signal that is the first potential or the ground potential,
The relay macrocell according to claim 3, wherein the third and fourth switch elements are controlled by an inverted signal of the third input signal. The first to fourth switch elements are:
18. The relay macrocell according to claim 17, wherein the relay macrocell is a reverse conductivity type MOS transistor having a source connected to the second power supply and a gate supplied with the third input signal or an inverted signal thereof. The first level shift circuit includes:
A third MOS transistor of reverse conductivity type, the source of which is connected to the first switch element and the gate of which is supplied with the inverted signal of the first input signal;
A reverse-conduction type fourth MOS transistor having a source connected to the first switch element, a drain connected to the drain of the third MOS transistor, and a gate supplied with an inverted signal of the second input signal When,
A reverse-conductivity-type fifth MOS transistor having a source connected to the first switch element and a gate supplied with the second input signal;
A reverse conductivity type sixth MOS transistor having a source connected to a drain of the fifth MOS transistor and a gate supplied with the first input signal;
A seventh MOS transistor of one conductivity type having a source connected to the first power supply, a drain connected to the drains of the third and fourth MOS transistors, and a gate connected to the drain of the sixth MOS transistor A transistor,
A first conductivity type first source having a source connected to the first power source, a drain connected to the drain of the sixth MOS transistor, and a gate connected to the drains of the third, fourth and seventh MOS transistors. 8 MOS transistors,
The first holding circuit includes:
A source connected to the third switch element, a drain connected to the drains of the third, fourth and seventh MOS transistors, and a gate connected to the drains of the sixth and eighth MOS transistors A ninth conductivity type MOS transistor;
A source connected to the third switch element, a drain connected to the drains of the sixth and eighth MOS transistors, and a gate connected to the drains of the third, fourth and seventh MOS transistors A conductive type tenth MOS transistor;
The second level shift circuit includes:
An eleventh MOS transistor of a reverse conductivity type having a source connected to the second switch element and a gate supplied with the second input signal;
A reverse-conductivity-type twelfth MOS transistor having a source connected to a drain of the eleventh MOS transistor and a gate supplied with an inverted signal of the first input signal;
A reverse conduction type thirteenth MOS transistor having a source connected to the second switch element and a gate supplied with the first input signal;
A reverse-conductivity-type fourteenth MOS transistor having a source connected to the second switch element, a drain connected to the drain of the thirteenth MOS transistor, and a gate supplied with an inverted signal of the second input signal When,
Fifteenth MOS transistor of one conductivity type having a source connected to the first power supply, a drain connected to the drain of the twelfth MOS transistor, and a gate connected to the drains of the thirteenth and fourteenth MOS transistors. A transistor,
One conductivity type first source connected to the first power supply, drain connected to the drains of the thirteenth and fourteenth MOS transistors, and gate connected to the drains of the twelfth and fifteenth MOS transistors. Composed of 16 MOS transistors,
The second holding circuit includes:
A reverse conductivity type seventeenth MOS transistor having a source connected to the fourth switch element and a gate connected to the drains of the sixth and eighth MOS transistors;
The source is connected to the drain of the seventeenth MOS transistor, the drain is connected to the drains of the twelfth and fifteenth MOS transistors, and the gate is connected to the drains of the thirteenth, fourteenth and sixteenth MOS transistors. A reverse conductivity type 18th MOS transistor;
A source connected to the fourth switch element, a drain connected to the drains of the thirteenth, fourteenth and sixteenth MOS transistors, and a gate connected to the drains of the twelfth and fifteenth MOS transistors A nineteenth conductivity type MOS transistor;
A reverse conductivity type having a source connected to the fourth switch element, a drain connected to the drain of the nineteenth MOS transistor, and a gate connected to the drains of the third, fourth and seventh MOS transistors. 19. The relay macrocell according to claim 17 or 18, comprising a twentieth MOS transistor.

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