KR100210734B1 - Logic and lever converter and semiconductor device - Google Patents

Abstract

It is an object of the present invention to simplify the construction and minimize the number of gates.

The pMOS transistor 3 and the nMOS transistor, which operate under a low power supply voltage and whose output terminals of the inverter 23 to which the reset signal Vr is supplied and the inverter 24 to which the input signal Va is supplied, operate under high power voltages, respectively. It is connected to the gate of 54. The pMOS transistor 3 is connected in series with the nMOS transistor 54. After the pMOS transistor 3 is turned on, the nMOS transistor 54 is turned off, and the output signal line 25 is precharged, the charge on the output signal line 25 is maintained while the pMOS transistor 3 is almost turned off. The characteristics of the pMOS transistor 3 are determined so that charge replenishment for leakage is sufficiently performed, and so that the through current when the nMOS transistor 54 is next turned on is as small as possible.

Description

Logic and Level Translation Circuits and Semiconductor Devices

1 is a principle configuration diagram of the logic and level conversion circuit of the present invention.

2 is a level conversion circuit diagram and timing chart of a first embodiment of the present invention.

3 is an AND and level conversion circuit diagram and timing chart of a second embodiment of the present invention.

4 is a diagram showing an end and level change circuit and an address decoder using the same according to the third embodiment of the present invention.

5 (a) and 5 (b) are conventional level conversion circuit diagrams.

6 (a) and 6 (b) are conventional end and level conversion circuit diagrams.

* Explanation of symbols for main parts of the drawings

3,3A, 3B: pMOS transistors 23,24,29,81 84: inverter

50: level conversion circuit 51, 61, 71: first logic circuit

54,641,642: nMOS transistors

60,70,701 704: end and level conversion circuit 64: nMOS circuit

The present invention relates to a logic and level conversion circuit in which a logic circuit and a level conversion circuit for converting a logic level of a low power supply voltage into a logic level of a high power voltage are combined, and a semiconductor device including the same.

Due to the high integration of semiconductor integrated circuits, circuit elements are miniaturized, and power supply voltages are lowered to ensure reliability of the miniaturized circuit elements and to lower power consumption. However, lowering the voltage is disadvantageous in speeding up the operation. Further, in the semiconductor memory device, for example, since the voltage decreases as charge passes through the transfer gate between the bit line and the memory cell, sufficient voltage cannot be written to the memory cell due to the low voltage. For this reason, the high voltage is used only in the necessary portion by providing the boost circuit in the semiconductor integrated circuit, thereby achieving both high speed operation and high reliability and low power consumption.

In such a semiconductor integrated circuit, circuits as shown in Figs. 5A, 5B, 6A, and 6B are used.

The level conversion circuit 10 shown in FIG. 5 (a) includes a first logic circuit 11 operating under a voltage between the first power supply line Vdd and a ground line, for example, 3.3V, and a first power supply line ( And a second logic circuit 12 operating under a voltage, for example, 5.0V, between the second power supply line Vpp and a ground line having a higher potential than Vdd). The nMOS transistors 13 and 14 of the second logic circuit 12 may be turned on / off at the output of the first logic circuit 11, but the MOS transistors 17 and 18 of the second logic circuit 12 may be the first. The through current flows because the high level output of the logic circuit 11 cannot completely turn it off.

Therefore, when the potential Vi is low level and the nMOS transistor 13 is on and the nMOS transistor 14 is off, the low level of the drain of the nMOS transistor 13 is supplied to the gate of the pMOS transistor 18 to supply the pMOS transistor 18. Is turned on, the high level of the drain of the nMOS transistor 14 is supplied to the gate of the pMOS transistor 17, the pMOS transistor 17 is turned off, and the potential Vo is made low. When the potential Vi is at a high level, the on / off of the nMOS transistors 13 and 14 and the pMOS transistors 17 and 18 are reversed from the above, and the potential Vo is at a high level.

In the level conversion circuit shown in FIG. 5 (b), the dynamic operation buffer circuit 20 is connected to the front end of the level conversion circuit 10. As shown in FIG. The gates of the pMOS transistors 21 and nMOS transistors 22 are supplied with a signal inverting the reset signal Vr to the inverter 23 and a signal inverting the input signal Va to the inverter 24, respectively.

In the stand-by state, the reset signal Vr and the input signal Va are at a high level, the pMOS transistor 21 is turned on, the nMOS transistor 22 is turned off, the signal line 25 is precharged, and the potential Vi thereof is increased. It is at a high level.

Transferring to the operating state, the reset signal Vr transitions to the low level and the pMOS transistor 21 is turned off. In this state, in order to prevent the charge Vi on the signal line 25 from leaking out and the potential Vi decreases, the potential Vi is switched by connecting the pMOS transistor 26 between the first power supply line Vdd and the signal line 25. The signal inverted by (27) is supplied to the gate of the transistor 26 by pMOS.

When the input signal va becomes low level, the nMOS transistor 22 is turned on, the charge on the signal line 25 is discharged to the ground line side, and the potential Vi becomes low level. At this time, though the through current flows from the pMOS transistor 26 to the nMOS transistor 22, in order to reduce the through current, the on resistance of the pMOS transistor 26 is increased.

The negative logic and level converting circuit shown in FIG. 6 (a) connects the dynamic-operated AND circuit 30 to the front end of the level converting circuit 10. The AND circuit 30 has a configuration in which an nMOs transistor 28 and an inverter 29 are added to the buffer circuit 20 of FIG. 5 (b). The electric charge precharged on the signal line 25 is discharged to the ground line side through the nMOS transistors 22 and 28 only when the input signals Va and Vb are simultaneously at the low level.

In the negative logic and level conversion circuit shown in FIG. 6 (b), the statically operated AND circuit 40 is connected to the front end of the level conversion circuit 10. The AND circuit 40 turns on the nMOS transistors 22 and 28 when the input signals va and Vb are at the same low level, and turns off the pMOS transistors 21A and 21B, respectively. The potential Vi becomes low level, and in other cases, the pMOS transistors 21A and 21B are turned on and the potential Vi becomes high level.

The circuits shown in Figs. 5 (b), 6 (a) and 6 (b) all have a large number of circuit elements, which is against the demand for high integration. In addition, since the number of gates from the input to the output is large, the signal propagation delay time becomes long.

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a logic and level conversion circuit and a semiconductor device having a simple configuration and a small number of gates.

1 shows the principle construction of the present invention.

In the logic and level conversion circuit of the first invention, the first logic circuit 1 operates under a voltage between the first high potential side power supply line Vdd and a low potential side power supply line, for example, a ground line, and corresponds to a signal input terminal. The second high potential side power supply line Vpp supplied with the output signal of the first logic circuit 1 and supplied with a potential higher than the potential of the first high potential side power supply line Vdd with the low potential side power supply line. In the logic and level conversion circuit having the second logic circuit 2 operating under a voltage between the second logic circuit 2, the source is connected to the second high potential side power supply line Vpp, and the gate The output signal of the first logic circuit 1 is supplied to the pMIS transistor 3 having an output signal line connected to a drain, and is connected between the output signal line and the low potential side power supply line, and corresponds to an input terminal. The output of the first logic circuit 1 Class nMIS that (n-channel Metal-Insulator Semiconductor) has a circuit (4).

In Fig. 1, 5 is a booster circuit, which boosts the potential of the first high potential side power supply line Vdd to generate a potential of the second high potential side power supply line Vpp, and may be an external circuit.

In the above configuration, when the pMIS transistor 3 is turned on by the first logic circuit 1 and the nMIS circuit 4 is turned off, the potential Vo of the output signal line becomes high level, and the first logic circuit 1 When the pMIS transistor 3 is almost off, and the nMIS circuit 4 is turned on, the potential Vo of the output signal line becomes low level.

According to this first invention, since the gate of the pMIS transistor 3 is driven to the output of the first logic circuit 1 having a power supply voltage lower than that of the second logic circuit 2, as shown in FIG. The effect that the same level conversion circuit is unnecessary, the structure is simple, and the number of gates is reduced is mentioned.

In the first aspect of the first invention, the pMIS transistor 3 has a threshold potential almost equal to the potential supplied to the first high potential side power supply line Vdd.

According to this first aspect, after the pMIS transistor 3 is turned on and the nMIS circuit 4 is turned off and the output signal line is precharged, the pMIS transistor 3 is almost turned off to charge leakage on the output signal line. Charge replenishment is performed sufficiently, and it becomes possible to satisfy the condition that the through current when the nMIS circuit 4 is turned on next is as small as possible.

In the second aspect of the first invention, for example, as shown in FIG. 1, the nMIs circuit is an nMIS transistor 54, and the first logic circuit has an output terminal connected to the gate of the pMIS transistor 3. The first inverter 23 and the output terminal have a second inverter 24 connected to the gate of the nMIS transistor 54.

According to this second aspect, it has a simple configuration with a small number of circuit elements, and functions as the conventional level conversion circuit shown in FIG. 5 (b). In addition, the signal propagation delay time is shortened because the number of gate stages from input to output is small. Moreover, since there is no feedback operation by cross connection like the level conversion circuit 10 of FIG. 5 (b), the operation is high speed.

In the third aspect of the first invention, for example, as shown in FIG. 3, the nMIS circuit is a circuit in which a first nMIS transistor 641 and a second nMIS transistor 642 are connected in series. (1) includes a first inverter 23 having an output terminal connected to the gate of the pMIS transistor 3, a second inverter 24 having an output terminal connected to the gate of the first nMIS transistor 641, and an output terminal. The third inverter 29 is connected to the gate of the second nMIS transistor 642.

In this third aspect, the output signal line 25 is precharged and the input signal Va of the second inverter 24 and the input signal Vb of the third inverter 29 with the pMIS transistor 3 almost off. ) Becomes low level at the same time, the nMIS transistors 641 and 642 are turned on so that the charge on the output signal line 25 is discharged to the ground line side, and the potential Vo becomes low level.

When the input signal Va of the second inverter 24 is set to the low level before the input signal Vb of the third inverter 29 transitions to the low level, the output signal line (i.e., the capacitance of the first nMIS transistor 641) is reduced. Since the precharge charge on 25 flows to the nMIS transistor 641 side and a part thereof leaks, when the pMIS transistor 3 is completely turned off, the output signal line 26 of the output signal line 26 as shown by a dashed line in FIG. The potential Vo falls.

However, since the pMIS transistor 3 is almost off, electric charge is supplemented on the output signal line 25, so that the potential Vo is kept constant. At this time, since the second nMIS transistor 642 is off, the through current can be ignored.

Accordingly, the third aspect has a simple configuration with a small number of circuit elements, and functions as the conventional circuit shown in FIG. 6 (a). In addition, the signal propagation delay time is shortened because the number of gate stages from the input to the output is small. Moreover, since there is no feedback operation by cross connection like the level conversion circuit 10 of Fig. 6A, the operation is high speed.

In the fourth aspect of the first invention, for example, as shown in FIG. 4, the nMIS circuit is a circuit in which the first nMIS transistor 641 and the second nMIS transistor 642 are connected in series, and the pMIS transistor is formed in the fourth aspect. The first pMIS transistor 3A and the second pMIS transistor 3B are connected in parallel, and the first logic circuit has an output terminal having a gate of the first pMIS transistor 3A and a gate of the first pMIS transistor 641. And a second inverter 29 connected to the gate of the second pMIS transistor 3B and the gate of the second nMIS transistor 642.

The semiconductor device of the second invention has any one of the above logic and level conversion circuits.

The semiconductor memory device of the third invention has an address decoder having the logic and level conversion circuits of the third or fourth aspect.

The third and fourth aspects of the noli and level converting circuits have the advantage that the configuration is simple, but the first nMIS transistor 641 and the second nMIS transistor 642 are on and the pMIS transistors 3, 3A, 3B. Has a drawback that some through current flows when the condition is almost off. However, when this logic and level conversion circuit is used for the address decoder, the rate at which this condition is satisfied is very small, so that the through current is very small as a whole, and the above-mentioned drawbacks of the logic and level conversion circuit are negligible. In other respects, the advantages of logic and level conversion circuits of simple configuration are retained, so that the semiconductor memory device having the address decoder of this configuration is excellent in practicality.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing.

[First Embodiment]

2 shows a dynamically operated level conversion circuit 50 of the first embodiment of the logic and level conversion circuit according to the present invention. The first logic circuit 51 and the nMOS transistor 54 are examples of configurations of the first logic circuit 1 and the nMIS circuit 4 of FIG.

The first logic circuit 51 operates under a power supply voltage between the first power supply line Vdd, for example, 3.3V, a ground line.

The first logic circuit 51 is composed of an inverter 23 and an inverter 24, and output terminals of the inverters 23 and 24 are connected to gates of the pMOS transistor 3 and the nMOS transistor 54, respectively. The reset signal Vr and the input signal Va are supplied to the input terminals of the inverters 23 and 24, respectively. The source of the pMOS transistor 3 is connected to the second power supply line Vpp, and the drain thereof is connected to the signal line 25. The second power supply line Vpp has a higher potential than the first power supply line Vdd, for example, 5.0V. The nMOS transistor 54 is connected between the signal line 25 and the ground line.

2B is a timing chart showing the operation of the level conversion circuit 50. As shown in FIG.

In the standby state, the reset signal Vr and the input signal Va are at a high level, the pMOS transistor 3 is turned on, the nMOS transistor 54 is turned off, and the signal line 25 is precharged. It is at a high level.

When it moves to the operating state, the reset signal Vr transitions to the low level and the pMOS transistor 3 is almost turned off. Since the charge on the signal line 25 leaks, and the charge is supplemented from the second power supply line Vpp to the signal line 25 through the pMOS transistor 3, the drop in the potential Vo is prevented.

When the input signal Va is at the low level, the nMOS transistor 54 is turned on to discharge the charge on the signal line 25 to the ground line side, and the power supply Vo is at the low level. Since the pMOS transistor 3 is almost off, some through current flows from the pMOS transistor 3 to the nMOS transistor 54.

The pMOS transistor 3 is characterized in such a manner that the above-mentioned charge replenishment is sufficiently performed, and also satisfies the condition that the through current is as small as possible. This condition depends on the difference between the potential Vpp and the potential Vdd, the wiring capacitance and the leakage of the signal line 25, but usually the threshold potential of the pMOS transistor 3 is equal to the first power source potential Vdd or the first power source potential ( It is satisfied that the design parameters of (gate width) / (gate length) are slightly lower than Vdd).

In this way, if the characteristics of the pMOS transistor 3 are determined, the level conversion circuit 50 achieves the same function as the conventional circuit shown in FIG. 5 (b).

The level conversion circuit 50 has a smaller number of circuit elements, a simpler configuration, and a smaller number of gate stages from an input to an output than two conventional circuits, resulting in a shorter signal propagation delay time. In the level conversion circuit 10 of FIG. 5 (b), the operation is slowed by the feedback by the cross connection, but the operation is high because the level conversion circuit 50 does not have such feedback.

Second Embodiment

3 shows a negative dynamically active AND and level conversion circuit 60 of a second embodiment of a logic and level conversion circuit according to the present invention. The first logic circuit 61 and the nMOS circuit 64 are examples of configurations of the first logic circuit 1 and the nMIS circuit 4 of FIG. 1, respectively.

In the nMOS circuit 64, an nMOS transistor 641 and an nMOS transistor 642 are connected in series between a signal line 25 and a ground line. The output terminals of the inverters 24 and 29 of the first logic circuit 61 are connected to the gates of the nMOS transistors 641 and 642, respectively.

The difference is the same configuration as that of the level conversion circuit 50 in FIG. 2 (a).

FIG. 3B is a timing chart showing the operation of the AND and level conversion circuit 70. As shown in FIG.

When the signal line 25 is precharged and the input signals Va and Vb are simultaneously at the low level while the pMOS transistor 3 is almost off, the nMOS transistors 641 and 642 are turned on, and the charge on the signal line 25 is reduced. The electric potential VO becomes low level by discharging to the ground line side.

If the input signal Va is brought to the low level before the input signal Vb transitions to the low level, the precharge charge on the signal line 25 flows to the nMOS transistor 641 side by a capacitive component of the nMOS transistor 641. Since the pMOS transistor 3 is completely off, the potential Vo drops as shown by the dashed-dotted line in the third (b).

However, since the pMOS transistor 3 is almost off, electric charge is supplemented on the signal line 25, and the potential Vo is kept constant. At this time, since the nMOS transistor 642 is off, the through current can be ignored.

Thus, the end and level conversion circuit 60 achieves the same function as the conventional circuit shown in FIG. 6 (a).

The AND and level conversion circuits 60 clearly have fewer circuit elements than the conventional circuits, are simpler in construction, and have fewer gate stages from the input to the output, thereby shortening the signal propagation delay time. In addition, in the level conversion circuit 10 of FIG. 6 (a), the operation is slowed down by the feedback by the cross connection, but the operation is high because the AND and level conversion circuits 60 do not have such feedback.

Third Embodiment

4 (a) shows a negative logic operation type end and level conversion circuit 70 of the third embodiment of the logic and level conversion circuit according to the present invention. The first logic circuit 71 and the nMOS circuit 64 are examples of the configuration of the first logic circuit 1 and the nMIS circuit 4 of FIG. In this AND and level conversion circuit 70, the pMOS transistor 3A and the pMOS transistor 3B are connected in parallel.

The first logic circuit 71 is composed of an inverter 24 and an inverter 29, and an output terminal of the inverter 24 is connected to gates of the pMOs transistors 3A and nMOS transistors 641, The output terminal is connected to the gates of the pMOS transistor 3B and the nMOS transistor 642.

In the AND and level conversion circuit 70, when the input signals Va and Vb are at the low level at the same time, the nMOS transistors 641 and 642 are turned on, and the pMOS transistors 3A and 3B are almost turned off so that the signal line 25 The potential Vo is at a low level. In other cases, the pMOS transistor 3A or the pMOS transistor 3B is turned on and the potential Vo is at a high level.

Since it is a static operation type, it is preferable to make the current as small as possible when the pMOS transistor 3A or the pMOS transistor 3B is almost turned off.

4 (b) shows the address decoder 80. As shown in FIG. In the figure, * marks indicate inversion of logical values. Word line (WO Since W3) is relatively long and the wiring capacity is large, it is necessary to make the high level potential higher than the first power supply line Vdd for high speed operation. Thus, the address decoder 80 has an AND and level conversion circuit 701 having the same configuration as that of the AND and level conversion circuit 70. 704). End and level conversion circuit 701 Since 704 is negative logic, each of the inverters 81 has its output stage. 84) is connected. Inverter (81 84 is a CMOS inverter using the second power supply line Vpp. Inverter (81 At the output terminal of 84, a word line (WO) W3) is connected.

Word line (WO Since W3) is almost at potential Vpp at a high level, high-speed operation is possible.

The AND and level conversion circuits 60 have the advantage of being simpler in construction than the conventional circuit of FIG. 6 (b). It has the drawback that a through current flows. However, when the AND and level conversion circuits 70 are used for the address decoder 80, it is understood that the through current flows through the AND and level conversion circuits 701. Since only one of the lines 704 is provided, the through current is slightly reduced as a whole so that the above-described drawbacks of the end and level conversion circuits 70 are negligible.

In other respects, since the benefits of the end and level conversion circuits 70 are maintained, the address decoder 80 of this configuration is excellent in practicality. The larger the number of address input bits of the address decoder 80, the greater this advantage and the smaller the drawback.

In addition, various modifications are included in this invention.

For example, the end and level conversion circuit 701 of FIG. 4 (b). As 704, the same effects as described above can be obtained even when the AND and level conversion circuits 60 in FIG. 3A are used. In addition, various circuits can be considered as 4 of FIG.

Claims (7)

A first logic circuit operating under a voltage between a first high potential side power supply line and a low potential side power supply line, and an output signal of the first logic circuit is supplied to a signal input terminal, the signal being higher than a potential of the first high potential side power supply line; A logic and level converting circuit having a second logic circuit operating under a voltage between a second high potential side power supply line to which a low leak is supplied and the low potential side power supply line, wherein the second logic circuit is a source of the second logic circuit. An input terminal connected between a pMIS transistor connected to a high potential power supply line, a output signal of the first logic circuit to a gate, and an output signal line connected to a drain, the output signal line, and the low potential side power supply line; And an nMIS circuit (4) to which an output of the first logic circuit is supplied. 2. The logic and level converting circuit as claimed in claim 1, wherein the pMIS transistor has a threshold potential substantially equal to a potential supplied to the first high potential side power supply line. 3. The nMIS circuit (4) according to claim 2, wherein the nMIS circuit (4) is an nMIS transistor, and the first logic circuit includes a first inverter having an output terminal connected to the gate of the pMIS transistor, and an output terminal connected to the gate of the nMIS transistor. A logic and level conversion circuit having two inverters. 3. The nMIS circuit (4) according to claim 2, wherein the nMIS circuit (4) is a circuit in which a first nMIS transistor and a second nMIS transistor are connected in series, and the first logic circuit includes a first inverter having an output terminal connected to a gate of the pMIS transistor, and an output terminal. And a second inverter connected to the gate of the first nMIS transistor, and an output terminal of the third inverter connected to the gate of the second nMIS transistor. 3. The nMIS circuit (4) according to claim 2, wherein the nMIS circuit (4) is a circuit in which a first nMIS transistor and a second nMIS transistor are connected in series, and the pMIS transistor has a first pMIS transistor and a second pMIS transistor connected in parallel. The first logic circuit includes a first inverter having an output terminal connected to a gate of the first pMIS transistor and a gate of the first nMIS transistor, and an output terminal connected to a gate of the second pMIS transistor and a gate of the second nMIS transistor. And a second inverter. The semiconductor device which has a logic and a level conversion circuit as described in any one of Claims 1-5. A semiconductor memory device, which has an address decoder having a logic and level conversion circuit as set forth in claim 4 or 5.