KR20000043182A - High voltage generator - Google Patents

Abstract

PURPOSE: A high voltage generator is provided to effectively perform an action even at a low voltage by increasing a high voltage pumping level up to three times of outer power voltage. CONSTITUTION: A capacitor within a pre charge device is discharged and a capacitor is charged by a pulse control signal of logic-high level. The potentials of a first and a second pre charge node are converted low and high. An NMOS transistor is turned to pre charge the first pre charge node as an outer power voltage level. In initializing a third boosting node as a Vext-Vt level, the NMOS transistor inside a level-up device(50) is turned on. The outer source voltage is supplied to the third boosting node, and the potential of the third boosting node keeps a 2Vest-Vt level. The pumping device(30) increases the potential of a first boosting node up to a 3Vest-Vt level by receiving a ring oscillator output signal of logic high level.

Description

High voltage generator

The present invention relates to a high voltage generator used to generate a high voltage higher than the power supply voltage in a semiconductor memory device, and more particularly, to generate a high potential of two or more levels (about 3 times) of the external power supply voltage by improving pumping efficiency. By making this possible, the present invention relates to a high voltage generator that can be adopted in the next generation low power DRAM.

In general, a high voltage (Vpp) pulse generated by a high voltage generator maintains a potential level of Vcc + Vt or more to compensate for a threshold voltage (Vt) loss of a transistor. It is widely used in the field of memory circuits, especially word line drivers, bit line isolation circuits and data output buffers.

FIG. 1 is a circuit diagram of a conventional high voltage generator. The first and second circuits are shown in accordance with potential states of pulse control signals osc and / osc generated at a constant period from a ring oscillator (not shown). Precharge means (10) for selectively precharging one of the precharge nodes (A1, B1) to an external power supply voltage level (Vext); Power supply means for selectively turning on according to the potential state of the first and second precharge nodes A1 and B1 to supply an external power supply voltage Vext to the first and second boosting nodes A and B. 20; Pumping means (30) for pumping potentials of the first and second boosting nodes (A, B) to a predetermined potential level (2Vext) in accordance with the potential state of the pulse control signals (osc, / osc); Switching is controlled in accordance with the potential state of the pulse control signals (osc, / osc) is provided with a high voltage output means 40 for selectively outputting the potential of the pumped boosting node at a high voltage.

In the case of the same figure, the precharge means 10 includes inverters I1 and I2 for receiving the complementary potential values of the pulse control signals osc and / osc and inverting them respectively; Capacitors (C1, C2) for varying the potentials of the first and second precharge nodes (A1, B1) by charging and discharging operations according to output stage values of the inverters (I1, I2); NMOS transistors MN1 and MN2 diode-connected between an external power supply voltage Vext applying end and the first and second precharge nodes A1 and B1, respectively; The NMOS transistors MN1 and MN2 are connected in parallel to each other, and each gate terminal includes NMOS transistors MN3 and MN4 connected in a cross-coupled structure with the first and second precharge nodes A1 and B1. It is configured by.

The power supply means 20 is connected between an external power supply voltage Vext and the first and second boosting nodes A and B, respectively, and gates of the first and second precharges are respectively connected. And NMOS transistors MN5 and MN6 connected to nodes A1 and B1.

In addition, the pumping means 30 includes a plurality of inverters (I3 and I4, I5 and I6) connected in series for receiving a complementary potential value (osc./osc) of the pulse control signal, respectively, for a predetermined time delay; And capacitors C3 and C4 connected to the output terminals of the inverters I4 and I6.

The high voltage output means 40 includes NMOS transistors MN7 and MN8 diode-connected between an external power supply voltage Vext and a first boosting node A and B, respectively; PMOS connected between the first and second boosting nodes A and B and the high voltage output terminal N1, respectively, and a gate coupled to the first and second boosting nodes A and B in a cross-coupled structure. The transistors MP1 and MP2 are provided.

The high voltage generator according to the prior art having the above-described configuration, first, selectively charges and discharges the capacitors C1 and C2 according to the output signals osc and / osc of the ring oscillator (not shown) which are input with opposite phases. As a result, the potential levels of the first and second precharge nodes A1 and A2 maintain the complementary logic level.

First, when the potential level of the ring oscillator output signal osc is assumed to be 'logic high', the capacitor C2 in the precharge means 10 is charged so as to 'logic high' the second precharge node B1. To level.

Since the second precharge node B1 having the 'logic high' level is connected to the gate terminal of the NMOS transistor MN3 in a cross-coupled structure, the NMOS transistor MN3 is turned on and consequently the first precharge node B1. The charge node A1 is precharged to the external power supply voltage level Vext.

Thereafter, the NMOS transistor MN5 in the power supply means 20 is selectively turned on by the first precharge node A1 precharged to the external power supply voltage Vext level, so that the first boosting node ( A) is primarily pumped to the external power supply voltage (Vext) level.

Thereafter, the pumping means 30 receives a ring oscillator output signal osc having a 'logic high' level to pump the potential of the first boosting node A having the external power supply voltage Vext level to 2Vext level. .

On the other hand, the pumping means 31 for receiving the logic low level / osc signal receives the PMOS transistor MP1 as the switching element because the capacitor C4 is discharged to make the second boosting node B low. ) Is turned on, and the 2Vext voltage of the first boosting node A is output at a high voltage.

The pulse control signal osc generated at a constant period from the ring oscillator

Even in the 'logic low' level, a voltage of 2 Vext level is output to the final high voltage Vpp output terminal N1 by changing only the current path by the same operation.

In the conventional technology of outputting a high voltage higher than a predetermined potential by an external power supply voltage Vext by the operation, the maximum value of the high voltage Vext is equal to the external power supply voltage in view of the loss of the threshold voltage (Vt) of the cell. This characteristic is less than twice that of Vext), but this characteristic is not a problem in current DRAM operation using 3.3V voltage, but the threshold potential of the cell transistor in DRAM design using a lower external voltage to reduce power consumption in the future is increased. Since it becomes relatively larger than the driving voltage Vcc, a higher level of high voltage generation is required.

In particular, since the NMOS transistor in the memory cell has the smallest dimension and is used with a back bias applied, it has much larger threshold potential loss than the NMOS transistor of the peripheral circuit having no body-effect, and also has a forward integration degree. As is increased, the distance between elements is further reduced, so that the threshold potential loss is further increased.

As described above, in preparation for the increase in the threshold potential loss of the cell transistor due to the increase in integration, a low voltage operation requires a high voltage generator capable of pumping the supply voltage to a high potential level higher than 2Vext.

Accordingly, the present invention has been made to meet the above-mentioned problems and demands, and an object of the present invention is to increase the high and low voltage popping levels to three times the external power supply voltage, thereby enabling a high voltage generator to perform an effective operation even at a low voltage. To provide.

In order to achieve the above object, the high voltage generator according to the present invention selectively selects one of the first and second precharge nodes according to the potential state of the pulse control signal generated at a constant period from the ring oscillator. Precharge means for precharging with;

Level-up means for selectively leveling up the potential of one of the first and second boosting nodes to a level of 2Vext in accordance with the potential state of the first and second precharge nodes and the potential state of the pulse control signal;

Pumping means for pumping the potential of the selectively leveling-up boosting node by Vext in accordance with the potential state of the pulse control scene;

Switching is controlled according to the potential state of the pulse control signal, characterized in that it comprises a high voltage output means for outputting the potential of the pumping boosting node to a high voltage.

1 is a circuit diagram of a conventional high voltage generator

2 is a circuit diagram of a high voltage generator according to the present invention.

3 is a comparison result of the simulation result while applying the external power supply voltage 1.5V and 2.0V for the high voltage generator shown in FIGS.

<Description of the symbols for the main parts of the drawings>

10: precharge means 20: power supply means

30, 31: pumping means 40: high voltage output means

50: level-up means

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a high voltage generator according to an embodiment of the present invention, in which a first and a second are generated according to potential states of pulse control signals osc and / osc generated at a constant period from a ring oscillator (not shown). Precharge means (10) for selectively precharging one of the precharge nodes (A1, B1) to an external power supply voltage level (Vext); The potential of one of the first and second boosting nodes A2 and B2 is changed according to the potential state of the first and second precharge nodes A1 and B1 and the potential state of the pulse control signals osc and / osc. Level-up means (50) for selectively leveling up to a level of 2Vext; Pumping means (30) for pumping a potential of the selectively leveling-up boosting node to a predetermined potential level (3Vext) according to the potential state of the pulse control signals (osc, / osc); Switching is controlled according to the potential state of the pulse control signals (osc, / osc) and has a high voltage output means 40 for outputting the potential of the pumping boosting node to a high voltage (Vpp).

Detailed configuration of the precharge means 10, the pumping means 30 and the high voltage output means 40 is the same as shown in Figure 1, the detailed description thereof will be omitted, the level-up means 50 ) Only in detail.

In the case of the same figure, the level-up means 50 includes respective inverters I3 and I4 for receiving and inverting complementary potential values osc and / osc of the pulse control signal, respectively; Capacitors C3 and C4 for varying the potentials of the third and fourth boosting nodes A2 and B2 by charge / discharge operations according to the output values of the inverters I3 and I4; NMOS transistors MN5 and MN6 diode-connected between an external power supply voltage Vext applying end and each of the third and fourth boosting nodes A2 and B2; Each of the NMOS transistors MN7 and MN8 connected in parallel to each of the diode-connected NMOS transistors MN5 and MN6 and to which the second and first precharge nodes B1 and A1 are applied to their respective gate ends. Wow; A diode is connected between each of the third and fourth boosting nodes A2 and B2 and each of the first and second boosting nodes A and B connected to an output terminal of each of the pumping means 30 and 31, respectively. However, each of the NMOS transistors MN9 and MN10 to which an external power supply voltage Vext is applied is provided.

Hereinafter, the operation of the high voltage generator according to the present invention having the above configuration will be described in detail.

Also in this case, the following description will be made on the assumption that the pulse control signal osc generated at a constant period from the ring oscillator is at the logic high level.

On the contrary, even when the pulse control signal osc is at the logic low level, only the transfer path is changed, and the same operation generates a high voltage Vpp having the same potential level (about 3 Vext) at the output terminal. Please note in advance.

First, the capacitor C1 in the precharge means 10 is discharged by the logic high level pulse control signal osc, and at the same time, the capacitor C2 is charged to charge the first and second precharge nodes A1. , B1) is shifted to 'low' and 'high', respectively. Accordingly, the NMOS transistor MN3 is turned on to precharge the first precharge node A1 to the external power supply voltage Vext level.

At this time, by applying the back bias voltage of the NMOS transistor MN9, which is transferred to the diode type in the level-up means 50, to the external power supply voltage Vext, an increase in the threshold voltage Vt can be prevented, and During power-up, the initial voltages of the first and third boosting nodes A and A2 are raised to the Vext-Vt level through a pn junction between the main body, the drain, and the source, and thus the NMOS transistor MN9. The two diode-type NMOS transistors (MN5 and MN11) connected to both sides via the following functions play the following roles.

By designing a P-Well for the NMOS transistor MN9 in the level-up means 50 in the N-Well for the PMOS transistors MP1 and MP2 in the high voltage output means 40, the N- A high voltage Vpp is applied to the well and a bias of the external power supply voltage Vext is applied to the P-Well. Thus, when the high voltage Vpp does not rise to the external power supply voltage Vext level, the P-Well and The forward bias is applied to the junction between the N-Wells to increase the initial voltage of the high voltage Vpp to a potential level smaller by the built-in potential of the junction than the external power supply voltage Vext. If Vpp) increases above the external power supply voltage (Vext), it becomes reverse bias and acts as a simple capacitor.

Accordingly, in the state where the third boosting node A2 is initialized to the Vext-Vt level, the level-up means for applying the first precharge node A1 of the external power supply voltage Vext level to the gate end ( As the NMOS transistor MN7 in 50 is turned on, the external power supply voltage Vext is supplied to the third boosting node A2, and as a result, the potential of the third boosting node A2 is maintained at a level of 2Vext-Vt. Done.

Thereafter, the pumping means 30 receives a ring oscillator output signal osc of 'logic high' level and charges the electric potential of the first boosting node A having the 2Vext-Vt level with the charge of the pumping capacitor C5. It is pumped up to 3Vext-Vt level.

On the other hand, the pumping means (31) receiving the / osc signal of the 'logic low' level, because the capacitor (C6) is discharged to make the second boosting node (B) 'low level', the high voltage output means (40) As the PMOS transistor MP1 as the switching element is turned on, the 3Vext-Vt voltage of the first boosting node A is output via the high voltage output terminal N1.

3 is a diagram illustrating a comparison result of applying the external power supply voltage of 1.5V and 2.0V, respectively, for the high voltage generator shown in FIGS. 1 and 2, and (a) and (c) according to the present invention. The output waveforms of the high voltage generator are shown, and (b) and (d) show the output waveforms of the high voltage generator conventionally used.

As can be seen from the drawing, in the case of the high voltage generator used for the same time, the pumping effect of applying the supply voltage of 1.5V is almost as shown in (d), whereas in the high voltage generator according to the present invention, The waveform of (c) shows that a certain pumping effect is obtained even at a low supply voltage.

As described above, according to the high voltage generator according to the present invention, the pumping efficiency of the external power supply voltage is increased to generate a high voltage that is punctured to 3Vext-Vt level, thereby effectively operating in a low power memory device. .

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (5)

Precharge means for selectively precharging one of the first and second precharge nodes to an external power supply voltage level Vext according to the potential state of the pulse control signal generated at a predetermined period from the ring oscillator; Level-up means for selectively leveling up the potential of one of the first and second boosting nodes to a level of 2Vext in accordance with the potential state of the first and second precharge nodes and the potential state of the pulse control signal; Pumping means for pumping the potential of the selectively leveling-up boosting node by Vext in accordance with the potential state of the pulse control scene; And a high voltage output means for controlling switching according to a potential state of the pulse control signal to selectively output a potential of a pumped boosting node at a high voltage. The method of claim 1, The precharge means includes: first and second inverters for receiving and inverting complementary potential values of the pulse control signal, respectively; First and second capacitors for varying potentials of the first and second precharge nodes by charging and discharging operations according to output values of the first and second inverters; First and second NMOS transistors diode-connected between an external power supply voltage supply terminal and the first and second precharge nodes, respectively; A high voltage connected to the first and second NMOS transistors in parallel, and each of the gate terminals includes third and fourth NMOS transistors connected in a cross-coupled structure with the first and second precharge nodes; generator. The method of claim 1, The level-up means includes: first and second inverters for receiving and inverting complementary potential values of the pulse control signal, respectively; First and second capacitors varying potentials of the third and fourth boosting nodes by charge and discharge operations according to output values of the first and second inverters; First and second NMOS transistors diode-connected between an external power supply voltage supply stage and each of the third and fourth boosting nodes; Third and fourth NMOS transistors connected in parallel to each of the first and second NMOS transistors, and the second and first precharge nodes applied to respective gate ends thereof; And fifth and sixth NMOS transistors diode-connected between each of the third and fourth boosting nodes and each of the first and second boosting nodes, and to which an external power supply voltage is applied to a bulk stage. High voltage generator. The method of claim 1, The pumping means comprises: a plurality of inverters connected in series for receiving a complementary potential value of the pulse control signal and delaying a predetermined time; And a capacitor connected to the output terminal of the inverter. The method of claim 1, The high voltage output means includes: first and second NMOS transistors diode-connected between an external power supply voltage applying stage and the first and second boosting nodes, respectively; A first and second PMOS transistors connected between the first and second boosting nodes and a high voltage output terminal, respectively, and each gate terminal is connected to the first and second boosting nodes in a cross-coupled structure. High voltage generator.