JP2990160B1 - Voltage generation circuit - Google Patents

Abstract

A power consumption is reduced by eliminating the need to use a continuous pulse as an input signal, and operation is possible even on a P-type substrate. An input signal IN is connected between a capacitance transistor C1 and an input terminal of an input terminal TIN and an input terminal of C1.
A delay element DL1 for delaying D, and a power supply V
A P-channel transistor P1 whose drain is connected to the output terminal of C1 and whose gate receives an inverted signal of the input signal IND, and whose source is connected to the output terminal of C1 and whose drain is connected to the ground GND and whose gate is input to the gate Signal I
A P-channel transistor P2 receiving the supply of ND, discharging the charge of C1 in response to the transition of the input signal IND from H level to L level,
In response to the transition of the potential of the input terminal of the
Generates a negative voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage generating circuit, and more particularly to a voltage generating circuit for generating an internal voltage such as a negative voltage in a CMOS LSI.

[0002]

2. Description of the Related Art A voltage generating circuit of this kind is used, for example, for generating a negative voltage to be supplied to the gate of an N-channel transistor for interrupting a power supply current.

The conventional first voltage generating circuit uses a continuous pulse as an input signal to generate a desired negative voltage. In recent years, devices with low power consumption have been desired due to the spread of portable devices. To achieve this, it is important to reduce the leakage current during standby and reduce power consumption. Therefore, when a conventional negative voltage generation circuit is used, power consumption of a clock driver or the like that operates by continuous pulses has been a problem.

Referring to FIG. 5 which shows a circuit diagram of a conventional first voltage generating circuit, this conventional first voltage generating circuit has:
A capacitance transistor C1 in which the drain, source and back gate of a P-channel transistor are commonly connected to form one electrode, the gate is the other electrode, and a depletion layer is used to form a capacitor, and the drain is supplied with an input signal IN.
01, a P-channel transistor P101 having a diode connected and the other end connected to the ground GND and one end connected to the gate of the capacitance transistor C101, and a back gate connected to the power supply VDD, respectively, and a diode-connected one end connected to the gate of the capacitance transistor C101. Connected to the power supply VDD and output signal OU from the other end
And P102 for outputting T.

Next, the operation of the conventional first voltage generating circuit will be described with reference to FIG.
A pulse-like input signal IN that alternately takes the power supply VDD level and the ground GND potential 0 V (GND level) is input. When the level of the input signal IN is the level of the power supply VDD, capacitive coupling to the node ND1 on the output side of the capacitance transistor C101 is not performed. Therefore, the level of node ND1 is maintained at a level lower than threshold voltage Vt of transistor P101.

Next, when the level of the input signal IN becomes the GND level, the level of the node ND1 becomes (Vt-VD) due to the capacitive coupling of the capacitance transistor C101.
D). Further, upon receiving a voltage level loss corresponding to the threshold voltage Vt of the transistor P102, (−VDD +
2Vt) as an output signal OUT.

In this conventional first voltage generating circuit, the output negative voltage becomes shallow when the power supply voltage is low due to the voltage level loss of the threshold voltage Vt of the two P-channel transistors P101 and P102, and in particular, VDD. <2Vt,
Generation of a negative voltage becomes impossible. When VDD <2Vt, a channel is not formed below the gate of the capacitance transistor C101, so that the circuit operation efficiency is reduced.

Japanese Patent Application Laid-Open No. 6-19700 discloses a first conventional voltage generating circuit in which a disadvantage of the first conventional voltage generating circuit is eliminated by reducing a voltage level loss caused by a threshold voltage of a transistor.
Referring to FIG. 6 which shows a circuit diagram of a conventional second voltage generating circuit described in Japanese Patent Laid-Open No. 3 (1993) -313, this conventional second voltage generating circuit has a P-type power supply having a source connected to a power supply VDD and a gate connected to an input terminal TIN. A channel transistor P101;
An N-channel transistor N101 having a gate connected to the gate of the transistor P101 and a drain connected to the drain of the transistor P101;
An inverter IV101 connected to IN, a capacitance transistor C101 having one end comprising a common connection of the drain and source of the P-channel transistor connected to an input terminal of the inverter IV101 and the other end comprising a gate connected to the source of the transistor N101, and a drain connected to An N-channel transistor N having a gate connected to the ground GND and a drain connected to the drains of the transistors P101 and N101, and a source connected to the source of the transistor N101.
102 and a diode-connected one end of a transistor N1.
01 and a capacitor C10 having one end connected to the output terminal TOUT and one end connected to the output terminal TOUT and the other end connected to the ground.
2 is provided.

[0009] Among the above components, the transistor N10
2 functions to set the upper limit of the voltage of the node ND2 to the reference voltage 0V, and the transistors P101 and N101
A gate voltage supply circuit for controlling the gate voltage level of the transistor N102 is formed. Note that the capacitance of the capacitance transistor C101 is the same as that of the transistor N101,
It is set to be sufficiently larger than the gate capacitance and the junction capacitance of N102.

Next, the operation of the second conventional voltage generating circuit will be described with reference to FIG. 6 and FIG. 7 showing the waveforms of respective parts in a time chart.
In the case of the D level (period T1), the transistor P101 is on and the transistor N101 is off. As a result, the voltage level of the node ND1 becomes the level of the power supply VDD, and this voltage VDD is supplied to the gate of the transistor N102. At this time, the GND level is applied to the capacitance transistor C101 by the inverter IV1.
Since the power supply VDD level inverted at 01 is supplied,
No capacitive coupling to node ND2 is performed. Therefore, node ND2 is pulled to and held at the ground GND level by transistor N102. At this time, the output signal OUT is also held at the GND level (0 V).

Next, when the input signal IN transitions from the GND level to the power supply VDD level (period T2), the transistor P101 switches off and the transistor N101 switches on. As a result, the voltage level of node ND1 drops, and accordingly, transistor N10
Since the gate voltage of No. 2 also drops to the GND level, it switches to the off state. However, as described above, since the capacitance of the capacitance transistor C101 is sufficiently large, the node ND2 is held at the GND level at this time, and the output signal OUT is also held at the GND level.

Next, the level of the power supply VDD of the input signal IN is inverted after a delay by the inverter IV1, whereby the level of the node ND3 on the input side of the capacitance transistor C101 transitions from the power supply VDD to the ground GND level. As a result, the capacitance transistor C1
Due to the coupling capacitance of 01, the node ND2 drops from the GND level to the negative power supply voltage -VDD level. At this time, since the transistor N101 is in the ON state, the voltage level of the node ND1 drops from the GND level to the negative power supply voltage −VDD level and becomes the same level as the node ND2. Therefore, transistor N102 is stably held in the off state, and leakage of negative power supply voltage -VDD from node ND2 is prevented.

A node ND2 is connected to an output terminal TOUT via a diode-connected transistor P102.
, The charge stored in the capacitor C102 is drawn out by the capacitance transistor C101. As a result, the output signal OUT decreases from the GND level to the negative voltage level.

When the voltage level of node ND2 is lower than the substrate potential by the threshold voltage of the PN junction or more, a forward current flows between the substrate and the diffusion layer of transistors N101 and N102, and the substrate potential decreases.

Here, even if the voltage level of the node ND2 rises again, the transistor P102 operates as a diode, so that the output signal OUT is maintained at the negative voltage level as it is pulled out by the capacitance transistor C101.

By repeating the above operations of the periods T1 and T2, the negative voltage level of the output signal OUT becomes the smaller of the threshold voltage Vt of the transistor P102 and the threshold voltage Vpnt of the PN junction. Determined by
(−VDD + Vt) or (−VDD + Vpnt).

However, when this conventional second voltage generating circuit is formed on a P-type substrate, the N-channel transistors N101 and N102 generally form an N-type well on the P-type substrate, and Are source or drain electrodes. In this case, these N-channel transistors N
When a negative voltage is applied to the source or the drain of the transistors 101 and N102, a leak current occurs in which the negative voltage leaks to the P-type substrate, and there is a problem that only a weak negative voltage can be generated.

[0018]

The above-described first and second voltage generating circuits use a continuous pulse as an input signal and generate a desired negative voltage. Therefore, a clock driver for supplying the continuous pulse is used. There is a drawback that it increases power consumption.

The first conventional voltage generating circuit generates a desired negative voltage by using a capacitance transistor for inputting an input signal and two diode-connected P-channel transistors connected to the output side of the capacitance transistor. Therefore, when the voltage level loss of the threshold voltage of these two P-channel transistors is superimposed, the output negative voltage decreases when the power supply voltage is low. If it is lower than twice, there is a disadvantage that it is impossible to generate a negative voltage.

When the power supply voltage is lower than twice the threshold voltage, a channel is not formed under the gate of the capacitance transistor, so that there is a disadvantage that the circuit operation efficiency is reduced.

The conventional second voltage generating circuit which solves the drawbacks of the conventional first voltage generating circuit by reducing the voltage level loss due to the threshold voltage of the transistor is used on a P-type substrate. Then, a negative voltage is applied to the source or the drain of the N-channel transistor, and the negative voltage escapes to the P-type substrate. As a result, there is a disadvantage that leakage occurs and only a weak negative voltage can be generated.

An object of the present invention is to reduce the power consumption by eliminating the need to use a continuous pulse as an input signal, to operate on a P-type substrate, and to eliminate a loss due to the threshold voltage of a transistor. Is to provide.

[0023]

Means for Solving the Problems] voltage generating circuit of the first invention, in the voltage generating circuit for generating an internal voltage for the internal circuit of the semiconductor integrated circuit being supplied with power supply voltage, MOS
Transistor drain and source and back gate
Depletion with one electrode and the gate as the other electrode
A capacitor having a predetermined capacitance value is formed using the layer, and the drain is formed.
And a capacitance element connected to the output terminal of the gate and the first terminal as a second terminal, connected to the delay time delay preset input signal between said first terminal of said capacitance element and the input terminal A delay element, a source connected to the power supply and a drain connected to the second of the capacitance element.
Wherein the first MOS transistor Ru supplied with the inverted signal of the input signal to each connected gate terminals, to be connected to the reference power supply potential a predetermined drain the source to the second terminal gates of Receiving the input signal
A second MOS transistor that holds the charge of the capacitance element accumulated between the first level in response to the transition of the input signal from the first level to the second level, and Generating the internal voltage having a polarity opposite to that of the power supply and an absolute value substantially equal to the power supply voltage in response to a transition of the potential of the first terminal to the second level after a lapse of time. Things.

The voltage generating circuit of the second invention, in the voltage generating circuit for generating an internal voltage for the internal circuit of the semiconductor integrated circuit being supplied with power supply voltage, the MOS transistor de
Connect the rain and source and back gate in common and
A capacitor having a predetermined capacitance value is formed by using an electrode, a gate as the other electrode, and a depletion layer, and the drain is used as a first terminal.
A first capacitance element connected to the output terminal as a second terminal , and an input terminal connected in series between the input terminal and the first terminal of the first capacitance element to delay the input signal by a predetermined delay. first to the time delay, the second delay element, the Ru supplied with the inverted signal of the input signal respectively connected to a gate to said second terminal of said first capacitance element and a drain of the source to the power supply 1 MOS
A transistor, a second MOS transistor having a source connected to a second terminal of the first capacitance element and a drain connected to a reference power supply having a predetermined potential, and an inverter for inverting an output of the second delay element When the OR circuit for outputting an input logic signal takes the logical sum of the output signal of the input signal and the inverter, a predetermined conductivity type MOS
Transistor drain and source and back gate
Depletion with one electrode and the gate as the other electrode
A capacitor having a predetermined capacitance value is formed using the layer, and the drain is formed.
A second capacitance element having a first terminal and a gate connected to the gate of the second transistor as a second terminal ; and an output terminal of the logic circuit and a first terminal of the second capacitance element. A third delay element connected in series between the input logic signal and the input logic signal for delaying the input logic signal by a predetermined delay time;
A third MOS transistor of the source Ru supplied with the inverted signal of the input signal to the second respectively connected gate terminal of said second capacitance element to drain to the power supply, the source second capacitance respectively connected to drain to the reference power source to the second terminal of element
A fourth MOS transistor, the charges of the first and second capacitance elements being accumulated between the first level in response to the transition of the input signal from a first level to a second level. holding the first, the absolute value in opposite polarity to the power supply in response to a transition to the second level of the potential of the first terminal of said first capacitance element after the second delay time Generating the internal voltage substantially equal to the power supply voltage and responding to the transition of the potential of the first terminal of the second capacitance element to the second level after the lapse of the third delay time; A voltage having a polarity opposite to that of the power supply and an absolute value substantially equal to the power supply voltage is supplied to the gate of the MOS transistor.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1 which is a circuit diagram partially showing an embodiment of the present invention, a voltage generating circuit 1 according to the present embodiment shown in FIG. The power supply current cutoff circuit 3 including a logic portion, which is an internal circuit of a semiconductor integrated circuit incorporating the negative voltage generation circuit 1, is connected to the output side.

The input terminal of the negative voltage generating circuit 1 is the input terminal T.
An inverter IV1 connected to IN, a delay element DL1 having an input terminal connected to the input terminal TIN, a drain, a source, and a back gate of a P-channel transistor commonly connected to each other to form one electrode and a gate to the other electrode and a depletion layer. And the drain is connected to the delay element DL1.
, A source and a back gate connected to the power supply VDD, a gate connected to the output terminal of the inverter IV1, a drain connected to the gate of the capacitance transistor C1, and an output signal OD output from the drain. P-channel type M
An OS transistor P1 is connected to a power supply VD by connecting a source to a drain of the transistor P1, a gate to an input terminal, and a back gate to a power supply
And a P-channel MOS transistor P2 having a drain connected to D and a ground GND, respectively.

The power supply current cutoff circuit 3 is a logic section 31 which is an internal circuit which performs a predetermined logic operation in response to the supply of the input signal INL and outputs an output signal OL, and has a drain connected to the ground side of the logic section 21 and a source connected to the logic section 21. An N-channel transistor N31 connected to the ground GND and receiving at its gate the output signal OD of the voltage generation circuit 1;

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 showing the waveforms of respective parts in a time chart. The input terminal TIN of the voltage generating circuit 1
An H-level input signal IND is supplied. In this case, the transistor P1 is turned on in response to the supply of the L level voltage inverted by the inverter IV1 to the gate, and the transistor P2 is turned off in response to the supply of the input signal IND to the gate at the H level. . At this time, the charge corresponding to the voltage (VDD-Vt) obtained by subtracting the threshold voltage Vt of the transistor P1 from the voltage level of the power supply VDD is stored in the capacitance transistor C1 via the transistor P1. Therefore, output signal OD of node ND3
Becomes H level.

Next, when the input terminal transitions from the H level to the L level, the transistor P1 is turned off, and the transistor P2 is turned on.
The output signal OD is in the vicinity of the L level, that is, (0V + V
The potential drops until t).

Next, after the delay time of the delay element DL1, the input potential of the capacitance transistor C1 changes from H level to L level. In response to this transition, the potential on the output side of the capacitance transistor C1, that is, the potential of the output signal OD changes to a potential lower than the L level, that is, (-VDD + 2Vt) due to the coupling capacitance of the capacitance transistor C1.

In the power supply current cutoff circuit 3, during the normal operation of the logic section 21, an H level output signal OD corresponding to the H level of the input signal IND of the negative voltage generation circuit 1 is supplied to the gate of the transistor N21. It turns on.
Next, when the logic unit 31 is on standby, the negative voltage generation circuit 1 changes the input signal IND to the L level, and outputs the negative voltage of the output signal OD in response to the L level of the input signal IND. In response to the supply of the negative voltage output signal OD to the gate, the transistor N31 completely blocks the leakage current from the logic unit 21. This makes it possible to suppress the leakage at the time of standby.

As described above, the conventional first and second voltage generating circuits need to supply continuous pulses, and the clock driver or the like, which is a supply source of the continuous pulses, causes an increase in power consumption. On the other hand, the voltage generating circuit according to the present embodiment can generate a desired negative voltage only by one level transition from the H level to the L level, and can operate with low power consumption.

Further, the voltage generation circuit of the present embodiment
Since it is composed only of the channel type MOS transistor, there is no leak path to the P-type substrate at a negative potential, and therefore, there is no problem in forming the transistor on the P-type substrate. Also, a device such as a silicon-on-insulator (SOI) structure that cannot take a well potential can be configured.

Next, a second embodiment of the present invention will be described with reference to FIG. Is different from the above-described first embodiment of the present embodiment in that a negative voltage generating circuit 1A having capacitance transistors C1 and C21 instead of the negative voltage generating circuit 1 is shown in FIG. , 2 in a two-stage negative voltage generating circuit.

The negative voltage generation circuit 1A includes an inverter IV1, a transistor P1, a capacitance transistor C1, and an inverter IV1, which are common to the negative voltage generation circuit 1 of the first embodiment.
In addition to the delay element DL1, a delay element DL2 having an input terminal connected to the output terminal of the delay element DL1, a source connected to the drain of the transistor P1, a back gate connected to the power supply VDD, a drain connected to the ground GND, and a negative voltage connected to the gate. A P-channel MOS transistor P2A supplied with the output OD2 of the generation circuit 2; and outputs an output signal OD1 from a common drain connection point of the transistors P1 and P2A.

The negative voltage generating circuit 2 includes an inverter IV21, a transistor P21, a capacitance transistor C21, a delay element DL21, and a transistor P22 similar to the corresponding components of the negative voltage generating circuit 1 of the first embodiment. In addition to the above, the input terminal is connected to a negative voltage generation circuit 1
A logical sum of the input signal IND and the output signal of the inverter IV22, and the output terminal of the inverter IV22 connected to the output terminal of the delay element DL2 of A.
, An input terminal of the inverter IV21, and a two-input OR circuit G21 connected to a common connection point of the gate of the transistor P22, and outputs an output signal OD2 from a common connection point of the drains of the transistors P21 and P22.

Next, the operation of the present embodiment will be described with reference to FIG. 3 and FIG. 4 showing the waveforms of respective parts in a time chart. In the first embodiment, as described above, the threshold value of the transistor P2 is set. Due to the voltage level loss corresponding to the value voltage Vt, the potential of the capacitance transistor C1 becomes (0 V
+ Vt), the negative voltage level of the output signal OD becomes (−VDD + 2Vt), and therefore, the threshold voltage 2Vt for two transistors
Voltage level loss. In the present embodiment, a first voltage is supplied to the gate input voltage of the transistor P2 to completely eliminate the voltage level loss corresponding to the threshold voltage Vt.
The circuit configuration uses two negative voltage generation circuits 1A and 2 having the same configuration as the negative voltage generation circuit 1 of the embodiment.

Referring to FIG. 4, when the level of input signal IND transitions from the H level to the L level, negative voltage output circuit OD2 is generated by negative voltage generation circuit 2, and this output signal OD2 is supplied to the negative voltage generation circuit. 1A is supplied to the gate of the transistor P2A (node ND5). Thereby, transistor P2A can output 0 V as output signal OD1 (node ND6) without voltage level loss of threshold voltage Vt. At this time, the electric charge of the capacitance transistor C1 is equivalent to the power supply VDD, and the loss of the threshold voltage Vt of the transistor P2 in the first embodiment can be improved.

Further, this allows the capacitance transistor C1 to push down the power supply VDD from 0 V, and to output (-VDD) as the output signal OD1. Therefore, a loss corresponding to the threshold value of 2 Vt of the transistor in the first embodiment can be improved.

As described above, the voltage generating circuit according to the present embodiment has the effects of reducing the power consumption of the voltage generating circuit according to the first embodiment and being capable of being formed on a P-type substrate. Voltage level loss can be completely eliminated by the threshold voltage.

[0041]

As described above, the voltage generating circuit according to the first aspect of the present invention includes a capacitance element, a delay element for delaying an input signal, a source connected to a power supply, and a drain connected to an output terminal of the capacitance element. A first transistor having a gate supplied with an inverted input signal, and a second transistor having a source connected to an output terminal of the capacitance element and a drain connected to a reference power supply, and having a gate supplied with the input signal.
And discharges the charge of the capacitance element in response to the transition of the input signal from the H level to the L level, and responds to the transition of the potential of the input side terminal to the L level after the elapse of the delay time. Since a negative voltage having a voltage substantially equal to the power supply voltage is generated, a desired negative voltage can be generated only by one transition from the H level to the L level of the input signal, and the operation can be performed with low power consumption. is there.

Further, since it is constituted only by P-channel type MOS transistors, there is no leakage path to the P-type substrate at a negative potential, so that it can be formed on the P-type substrate, and it can be formed on the SOI structure. There is an effect that a device that cannot take the well potential can be configured.

Further, the voltage generating circuit according to the second invention uses the two stages of the voltage generating circuit according to the first invention to supply a negative voltage to the gate of the second transistor so that the first voltage is reduced.
In addition to the above effects of the invention, there is an effect that the voltage level loss can be completely eliminated by the threshold voltage of this transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage generation circuit according to the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the voltage generation circuit according to the present embodiment.

FIG. 3 is a circuit diagram illustrating a voltage generating circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart illustrating an example of an operation in the voltage generation circuit according to the present embodiment.

FIG. 5 is a circuit showing an example of a conventional first voltage generation circuit.

FIG. 6 is a circuit illustrating an example of a second conventional voltage generating circuit.

FIG. 7 is a time chart showing an example of an operation in a conventional second voltage generation circuit.

[Explanation of symbols]

1, 2, 1A Negative voltage generation circuit 3 Power supply current cutoff circuit 31 Logic section C1, C2, C101 Capacitance transistor DL1, DL2, DL21 Delay element G21 OR circuit IV1, IV21, IV22 Inverter P1, P2, P2A, P21, P22, P101, P1
02, N31, N101, N102 Transistor

Claims (5)

(57) [Claims] 1. A voltage generating circuit for receiving a power supply voltage and generating an internal voltage for an internal circuit of a semiconductor integrated circuit, comprising: a drain and a source of a MOS transistor;
And the gate to the other electrode.
A capacitor having a predetermined capacitance value is formed using a depletion layer, and the drain is formed.
And a capacitance element connected to the gate and the in the first terminal to the second output terminal as a terminal, a predetermined delay time to connect with the input signal between the input terminal and the first terminal of the capacitance element wherein a delay element for delaying a first MOS transistor Ru supplied with the inverted signal of the input signal to the gate respectively connected to the drain of the source to the power source to the second terminal of the capacitance element, a source first and a second MOS transistor Ru supplied with the input signal to the gate respectively connected to <br/> reference power source of a predetermined potential and the drain 2 of the terminal, first the first level of the input signal in response to a transition to the second level of the potential of the first terminal after the elapse of retaining charge the delay time of the capacitance element that has accumulated during the first level Serial voltage generating circuit, characterized in that the absolute value opposite polarity to the response power transition to the second level occurs substantially equal the internal voltage and the power supply voltage. 2. The MOS transistor and the first and second MOS transistors
2. The voltage generation circuit according to claim 1, wherein the second MOS transistor is a P-channel type MOS transistor. 3. The voltage generating circuit according to claim 1, further comprising an inverter that outputs the inverted signal in response to the supply of the input signal. 4. A voltage generating circuit for receiving a power supply voltage and generating an internal voltage for an internal circuit of a semiconductor integrated circuit, comprising: a drain and a source of a MOS transistor;
And the gate to the other electrode.
A capacitor having a predetermined capacitance value is formed using a depletion layer, and the drain is formed.
A first capacitance element having an input as a first terminal and a gate as a second terminal connected to the output terminal; and an input signal connected in series between the input terminal and the first terminal of the first capacitance element. First and second delay elements for respectively delaying a predetermined delay time, a source being connected to the power supply, a drain being connected to the second terminal of the first capacitance element, and an inverted signal of the input signal being connected to the gate. a first MOS transistor Ru supplied with, and connected to the reference power supply of a predetermined potential and a drain to the second terminal of said first capacitance element source
A second MOS transistor, and an inverter for inverting the output of said second delay element, and an OR circuit for outputting an input logic signal takes the logical sum of the output signal of the input signal and the inverter, a predetermined conductivity type MOS transistor drain and source and
And the back gate are connected in common to make one electrode
A depletion layer is used as the other electrode to form a capacitor having a predetermined capacitance value.
Wherein the drain is a first terminal and the gate is a second terminal
As the second transistor connected to the gate of the second transistor.
A third delay element connected in series between an output terminal of the logic circuit and a first terminal of the second capacitance element to delay the input logic signal by a predetermined delay time; a third MOS transistor drain Ru supplied with the inverted signal of the input signal to the second respectively connected gate terminal of said second capacitance element to the power supply, the source second capacitance element fourth MO of the drain to the second terminal of the connected to the reference power supply
An S- transistor, wherein the charge of the first and second capacitance elements accumulated between the first level in response to the transition of the input signal from a first level to a second level is held. The first,
In response to a transition of the potential of the first terminal of the first capacitance element to the second level after a lapse of a second delay time, the polarity is opposite to the power supply and the absolute value is substantially equal to the power supply voltage. The second MOS transistor is responsive to a transition of the potential of the first terminal of the second capacitance element to the second level after the generation of the internal voltage and the lapse of the third delay time.
A voltage generating circuit for supplying a voltage having a polarity opposite to that of the power supply and an absolute value substantially equal to the power supply voltage to a gate of the transistor. 5. The voltage generation circuit according to claim 1, wherein the potential of the reference power supply is a ground potential.