JP2000339981A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a latch up when a power source is supplied by delaying an operation start timing of a first power source generation circuit from an operation start timing of a second power source generation circuit with using as an input signal, an output signal of a voltage sensing circuit which detects a voltage level of an external power source when the power source is supplied and generates a signal for inverting a logic. SOLUTION: After an external power source 5 is supplied, a voltage sensing circuit 3 holds an output to 'L' until a voltage level of the external power source 5 becomes a predetermined value, and turns the output to 'H' when the voltage level becomes the predetermined value. A delay circuit 4 turns the output to 'H' a predetermined time later in response to the output 'H' of the voltage sensing circuit 3. A VDD generation circuit 1 starts operating upon receipt of the output 'H' of the delay circuit 4. A voltage level of the VDD generation circuit 1 connected to a P+ diffusion layer 9 of a PMOS transistor is prevented from being higher than a voltage level of a VPP generation circuit 2 connected to an N type substrate 11 via an N+ diffusion layer 8, and a latch up can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having an N-type substrate of a PMOS transistor and a P + diffusion layer in which a source is formed. The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit having a CMOS structure, in order to prevent latch-up between an NMOS transistor and a PMOS transistor, a reverse bias is applied to a PN junction that separates the transistors from each other. Separation from each other has been done. FIG. 13 is a schematic cross-sectional view showing the structure and power supply connection of the CMOS inverter circuit. As shown in FIG.
P-Wel for providing an NMOS transistor on
l139 is formed. On an N-type substrate 143 for providing a PMOS transistor, P + diffusion layers forming regions of a source 141 and a drain 142 are respectively formed. Normally, the source 141 is connected to an external power supply (hereinafter, referred to as VCC) or an internal power supply (hereinafter, referred to as VDD). The N-type substrate 143 is connected to VCC or VDD via the N + diffusion layer 140 and has a positive potential applied. on the other hand,
In the P-Well 139, an N + diffusion layer forming a source 137 and a drain 136 region is formed. Usually, the source 137 is connected to GND. P-Well1
39 is connected to VSS via a P + diffusion layer 138, but in a DRAM, this P-Well 139 is connected to Vss.
Connected to the BB generation circuit 132, a negative potential is applied.
With the above configuration, the P-Well 139 and the N-type substrate 143
A zero bias or reverse bias is applied to the PN junction between them to prevent latch-up that may occur between the PMOS and the NMOS.

One of the semiconductor integrated circuits is a semiconductor memory device. The semiconductor memory device includes a core unit including a memory cell array and a peripheral unit including a control circuit and a decode circuit. In the core part, VSS
, A back bias power supply (hereinafter, referred to as VBB), an internal operation power supply VDD, and a boosted power supply (hereinafter, referred to as VPP) having a higher voltage level than VDD for boosting the word line in some cases. The diffusion layers to which these power supplies are connected are laid out while securing an isolation region based on design rules. In a semiconductor memory device, a ratio of a core circuit to a chip area is high, but this ratio tends to be higher with an increase in capacity.

Therefore, for example, in a sense amplifier driver included in a core portion, a transistor structure is used in which VDD is connected to a P + diffusion layer forming a source of a PMOS transistor and VPP is connected to the substrate via an N + diffusion layer. Thus, an increase in the layout area due to the securing of the separation region is suppressed as much as possible. FIG. 14 is a schematic sectional view of an integrated circuit having the above structure. This integrated circuit is shown in FIG.
The structure is almost the same as that of the integrated circuit described above, and the same elements as those in FIG. The difference from the integrated circuit of FIG. 13 is that the boosted power supply VPP generated by the VPP generation circuit 144 is connected to the N + diffusion layer 140 instead of the internal power supply VDD.

FIG. 15 shows a current mirror differential amplifier circuit generally used as a VDD generating circuit. In the figure, 15 is a reference potential generating circuit, and 16, 17, and 18 are PM
OS transistors, 19, 20, and 21 are NMOS transistors, and 24 is an internal power supply VDD. An external power supply VCC is connected to the gate of the NMOS transistor 21.
A reference voltage generating circuit is connected to the gate of the S transistor 19. Here, when the voltage level of the internal power supply 24 becomes lower than the reference potential generated by the reference potential generation circuit 15 due to the operation of the internal circuit, the NMOS transistor 1
9, the VGS of the PMOS transistor 18 increases, and the charge is supplied to the internal power supply 24. On the other hand, when the voltage level of the internal power supply 24 becomes higher than the reference potential, the PMOS transistors 16 and 17
The gate voltage level becomes lower. Therefore, the voltage level of the gate of the PMOS transistor 18 increases, and the supply of charges to the internal power supply 24 is suppressed. In this way,
The voltage level of the internal power supply VDD is kept constant.

[0006]

In the semiconductor integrated circuit having the structure shown in FIG. 14, the N + diffusion layer 1 is in a steady state.
The voltage level of VPP connected to N-type substrate 143 via 40 is higher than the voltage level of VDD connected to the diffusion layer forming source 141 of the PMOS transistor, and a reverse bias is applied to this PN junction. ing. However, when the power supply is turned on and the voltage level of the external power supply VCC is low, the voltage level of VPP may not be sufficiently increased, and there is a possibility that reverse bias does not occur.

FIG. 16 shows VCC and VD when the power is turned on.
Operation waveforms of D and VPP are shown as a timing chart. When power is turned on, VPP rises first (t = t
0), and then VDD rises (t = t1). VP
In the process where the voltages of P and VDD reach the steady level, P +
When the voltage level of VDD connected to the diffusion layer 141 is
A state occurs where the voltage level of VPP connected to N-type substrate 143 via N + diffusion layer 140 exceeds the potential potential of the PN junction and becomes higher (t = t2).
Then, the PN junction becomes conductive, causing latch-up.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor integrated circuit capable of preventing latch-up when power is turned on.

[0009]

A semiconductor integrated circuit according to the present invention comprises a first power supply generating circuit for generating a first power supply, and a second power supply for generating a second power supply having a higher voltage level than the first power supply. A first power supply is connected to a P + diffusion layer forming the source of the PMOS transistor, and a second power supply is connected to the N-type substrate of the PMOS transistor via the N + diffusion layer. I do. A voltage detection circuit for detecting a voltage level of an external power supply at power-on and generating a signal whose logic is inverted, and an output signal of the voltage detection circuit as an input signal thereof, and an operation start timing of the first power supply generation circuit is determined. A delay circuit for delaying the operation start timing of the second power supply generation circuit.

A semiconductor integrated circuit according to a second aspect of the present invention includes a first power supply generating circuit for generating a first power supply and a second power supply generating circuit for generating a second power supply having a higher voltage level than the first power supply. It is assumed that the first power supply is connected to a P + diffusion layer forming the source of the PMOS transistor. A voltage detection circuit that detects a voltage level of an external power supply at power-on and generates a signal whose logic is inverted; a delay circuit that generates a delay signal of time Δt using an output signal of the voltage detection circuit as an input signal; A switch circuit that receives an output of the delay circuit as an input, and that switches one of the first power supply and the second power supply to be connected to the N-type substrate of the PMOS transistor via the N + diffusion layer; The switch circuit is configured to be switched based on an output signal of the circuit.

A semiconductor integrated circuit according to a third aspect of the present invention includes a first power supply generating circuit for generating a first power supply and a second power supply generating circuit for generating a second power supply having a voltage level higher than the first power supply. It is assumed that the first power supply is connected to the P + diffusion layer forming the source of the PMOS transistor, and the second power supply is connected to the N-type substrate of the PMOS transistor via the N + diffusion layer. A first voltage detection circuit detects a voltage level of an external power supply at power-on and generates a signal whose logic is inverted, and a second voltage detection circuit detects a voltage level of a second power supply and generates a signal whose logic is inverted. It further includes a voltage detection circuit, and a control circuit that starts operation of the first power supply generation circuit based on an output signal of the first voltage detection circuit and the second voltage detection circuit.

A semiconductor integrated circuit according to a fourth aspect of the present invention includes a first power supply generating circuit for generating a first power supply and a second power supply generating circuit for generating a second power supply having a voltage level higher than the first power supply. It is assumed that the first power supply is connected to a P + diffusion layer forming the source of the PMOS transistor. And a first voltage detection circuit for detecting a voltage level of the external power supply at power-on and generating a signal whose logic is inverted;
A second voltage detection circuit for detecting a voltage level of the power supply of the second power supply and generating a signal whose logic is inverted, a control circuit using output signals of the first voltage detection circuit and the second voltage detection circuit as input signals, and a control circuit A switch circuit that switches an output signal to the input signal and connects one of the first power supply and the second power supply to the N-type substrate of the PMOS transistor via the N + diffusion layer; The circuit is
It is configured to output a signal for switching the switch circuit based on output signals of the first voltage detection circuit and the second voltage detection circuit.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the third or fourth aspect, the detection level of the second voltage detection circuit is a voltage level based on an external power supply.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the third or fourth aspect, the detection level of the second voltage detection circuit is set to a voltage level based on a voltage serving as a reference potential of the first power supply. .

According to a seventh aspect of the present invention, a semiconductor integrated circuit includes a first power supply generating circuit for generating a first power supply and a second power supply generating circuit for generating a second power supply having a higher voltage level than the first power supply. A first power supply is connected to a first P + diffusion layer forming the source of the first PMOS transistor, and a second power supply is connected to the substrate of the first PMOS transistor via the first N + diffusion layer It is assumed that the configuration is as follows. And a second P + diffusion layer for generating a third power supply having the same voltage level as the first power supply and forming a source of the second PMOS transistor formed on a substrate different from the first PMOS transistor And a third power supply generating circuit connected to the second N + diffusion layer, and a first power supply generating circuit for detecting a voltage level of the third power supply at power-on and generating a signal whose logic is inverted.
A voltage detection circuit, a second voltage detection circuit that detects a voltage level of the second power supply and generates a signal whose logic is inverted, and output signals of the voltage first voltage detection circuit and the second voltage detection circuit as input signals. And a control circuit that outputs a signal for controlling the first power supply generation circuit, wherein the first power supply generation circuit is configured to start operating based on an output signal of the control circuit.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the seventh aspect, the detection level of the second voltage detection circuit is based on the third power supply generated by the third power supply generation circuit.

[0017]

FIG. 1 shows a PMOS integrated circuit according to a first embodiment of the present invention.
1 is a schematic block diagram including a schematic cross-sectional view of a transistor.
In the figure, reference numeral 1 denotes a VDD generating circuit, which is connected to a P + diffusion layer forming a source 9. Reference numeral 2 denotes a VPP generation circuit, which is connected to an N-type substrate 11 via an N + diffusion layer 8. The output of the voltage detection circuit 3 is input to the VDD generation circuit 1 via the delay circuit 4. The voltage detection circuit 3 is connected to an external power supply 5. Reference numeral 6 denotes an input to the gate of the PMOS transistor, and reference numeral 7 denotes an output from the drain 10.

FIG. 2 shows V in the first embodiment of the present invention.
2 shows a circuit configuration of the DD generation circuit 1. The VDD generating circuit of FIG. 2 has substantially the same configuration as the circuit of FIG. 15, and the same elements are denoted by the same reference numerals and description thereof will be omitted. The difference is that the external power supply V
The output of the delay circuit 4 of FIG.
Is applied. That is, the operation of the VDD generation circuit 1 can be controlled by the output signal of the delay circuit 4.

FIG. 3 is a diagram for explaining the operation of the above embodiment.
7 is a timing chart showing operation waveforms of VCC, VDD, VPP, and / POR at the time of power-on. Note that / POR is a signal whose logic is inverted from “L” to “H” when the voltage level of the external power supply VCC is detected.

External power supply VCC is turned on (t = 0)
Thereafter, until the voltage level of VCC reaches a predetermined voltage level, the output of the voltage detection circuit 3 holds “L”, and the output of the delay circuit 4 having the output of the voltage detection circuit 3 as an input signal is also output. “L” is held. Therefore, the NMOS transistor 21 of the VDD generating circuit shown in FIG. 2 has its gate at "L" and is in the OFF state, so that the VDD generating circuit is in the operation stopped state. At t = t0, VPP rises. Thereafter, when the VCC level rises and reaches a predetermined detection level, the output of the voltage detection circuit 3 changes from “L” to “H” (t
= T2). The output of the delay circuit 4 changes from “L” to “H” after a lapse of time Δt in response to the output of the voltage detection circuit 3, and VD
The gate of the NMOS transistor 21 in the D generation circuit 1 becomes “H”, and the VDD generation circuit 1 starts operating (t = t3).

As described above, the voltage detection circuit 3 and the delay circuit 4
Is provided to control the operation start timing of the VDD generation circuit 1 so that the PMOS transistor P
The voltage level of VDD connected to + diffusion layer 9 does not become higher than the voltage level of VPP connected to the N-type substrate via N + diffusion layer 8. Therefore, latch-up at the time of power-on can be prevented.

The delay time in the delay circuit 4 may be set in accordance with the rising characteristics of the VDD generation circuit 1 and the VPP generation circuit 2 when the power is turned on.

FIG. 4 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a second embodiment of the present invention, including a schematic sectional view of a PMOS transistor. In the figure,
Reference numeral 25 denotes a VDD generating circuit,
+ Connected to the diffusion layer. A switch circuit 29 selectively connects the VDD generation circuit 25 and the VPP generation circuit 26 to the N + diffusion layer 33. The output of the delay circuit 28 is applied to the switch circuit 29, and based on the output, N
The power supply connected to + diffusion layer 33 is switched. The output of the voltage detection circuit 27 is connected to the delay circuit 28.

In this configuration, the switch circuit 29 uses the output of the delay circuit 28 to control the external power supply VCC when the power is turned on.
Until the voltage reaches a predetermined voltage level, the operation is performed to connect VDD to the N-type substrate 36 via the N + diffusion layer 33. After VCC reaches a predetermined voltage level, switch circuit 29 is switched by the output of delay circuit 28 to connect VPP to N-type substrate 36 via N + diffusion layer 33. Accordingly, the voltage level of the P + diffusion layer 34 of the PMOS transistor does not become higher than the voltage level of the N-type substrate 36 at the time of power-on, so that latch-up at the time of power-on can be prevented.

FIG. 5 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a third embodiment of the present invention, including a schematic sectional view of a PMOS transistor. In the figure, reference numeral 41 denotes a VDD generating circuit, which is connected to a source 50 of a PMOS transistor. Reference numeral 42 denotes a VPP generation circuit, which is connected to an N-type substrate 52 via an N + diffusion layer 49 of a PMOS transistor. Reference numeral 43 denotes a VCC voltage detection circuit 43 and reference numeral 44 denotes a VPP voltage detection circuit 44, and their outputs are connected to a control circuit 45. The output of the control circuit 45 is input to the VDD generation circuit 41.

FIG. 6 shows a circuit example of the voltage detection circuit 44.
In the figure, 55 and 56 are PMOS transistors, 57 and
58 is an NMOS transistor and 59 is an inverter. The gate of the PMOS transistor 55 has an external power supply V
CC60 is connected, and VPP61 is connected to the source. The gate of the PMOS transistor 56 is VS
The gate and drain of the NMOS transistor 57 are connected to the gate of the NMOS transistor 58. Immediately after power-on, the NMOS transistor 5
7 and 58 are OFF and the PMOS transistor 56 is ON, the output signal 63 is "L". The voltage level of VPP gradually increases with time, and when the voltage level reaches “VCC + Vtp”, the PMOS transistor 55 turns on. As a result, when the voltage level of the gates of the NMOS transistors 57 and 58 becomes higher than the threshold value, the NMOS transistors 57 and 58
N, a current flows between VCC and VSS via the PMOS transistor 56 and the NMOS transistor 58. Here, Vtp is the threshold voltage of the PMOS transistor 55. At this time, the PMOS transistor 56 and the NMO
When the voltage level of the node A becomes lower than the switching level of the inverter 59 due to the resistance division of the S transistor 58, the output signal 63 becomes “H”. That is, the voltage detection circuit 44 holds “L” until the voltage level of VPP reaches the voltage level of “VCC + Vtp” with reference to the external power supply VCC when the power is turned on, and “VC”
When the signal reaches “C + Vtp”, a signal that changes from “L” to “H” is output.

FIG. 7 shows an example of a circuit diagram of the control circuit 45. In the figure, 65, 66, and 67 are NAND circuits,
8, 69 are input signals, and 70 is an output signal. NAND
Signals 68 and 69 are input to the circuit 65, and the output 71 of the NAND circuit 65 and the output 72 of the NAND circuit 67 are
The configuration is such that a signal 69 and an output signal 70 are input to the D circuit 66 and the NAND circuit 67 is input to the D circuit 66. As the input signal 68, the output of the voltage detection circuit 44 is the input signal 6
As 9, the output of the voltage detection circuit 43 is applied.

FIG. 8 is a timing chart showing the behavior of VCC, VDD, VPP and / POR when the power is turned on.

The external power supply VCC is turned on (t = 0), and V
Until the voltage level of CC reaches the predetermined voltage level, the output of the voltage detection circuit 43 holds “L”, so that the input signal of the control circuit 45 is also “L”. That is, since the outputs of the NAND circuits 65 and 67 both become “H”, the output of the control circuit 45 becomes “L” regardless of the output of the voltage detection circuit 44 of VPP, and
The output 72 of the circuit 67 latches the "H" state. That is, the VDD generation circuit 41 does not operate, and VDD remains at the “L” level.

Here, when the VCC level rises and reaches a predetermined detection level, the output of the voltage detection circuit 43 changes from "L" to "H" (t = t2), and the output signal of this voltage detection circuit 43 becomes Input signal 6 of control circuit 45 to be connected
9 becomes "H". At this time, the N + diffusion layer 49
When the VPP level connected to the substrate 52 is lower than the predetermined voltage level, the output of the voltage detection circuit 44 remains "L", so that the output 71 of the NAND circuit 65 also holds "H" and the control is performed. The output of the circuit 45 remains “L” and the VDD generation circuit 41 holds the operation stopped state. When the VPP level increases with time and reaches a predetermined voltage level (t = t4), the output of the voltage detection circuit 44, that is, the input signal 68 of the control circuit 45 changes from “L” to “H”.
As a result, the output 71 of the NAND circuit 65 becomes “H” →
Since the output becomes “L”, the output of the control circuit 45 becomes “L” →
It becomes “H”, and the VDD generating circuit starts operating. In the control circuit 45, when the output signal 70 changes from “L” to “H”, the output 72 of the NAND circuit 67 latches “L”, so that the output signal 70 holds “H”.

As described above, the voltage level of VPP is detected, and after the VPP level reaches the predetermined voltage level,
By operating the DD generation circuit, the PMO
Since the voltage level of the P + diffusion layer 50 forming the source of the S transistor does not become higher than the voltage level of the N-type substrate 52, latch-up at the time of power-on can be prevented. Here, in the voltage detecting circuit of FIG. 6, the reference potential generator 15 used in the VDD generating circuit shown in FIG.
(Hereinafter, the potential is referred to as VREF),
The detection level of PP is “VREF + Vtp”. As described above, the VP determining the operation start timing of the VDD generating circuit is determined.
The voltage detection level of P is VCC, VDD,
The optimum level can be set in consideration of the rising characteristics of VPP.

FIG. 9 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a fourth embodiment of the present invention, including a schematic sectional view of a PMOS transistor. In the figure,
A VDD generating circuit 75 is connected to the P + diffusion layer 85 forming the source of the PMOS transistor. 8
0 is a switch circuit, and the VDD generation circuit 75 and VPP
The generation circuit 76 is selectively connected to the N + diffusion layer 84 through the N + diffusion layer 84.
Connected to the shaped substrate 87. The output of the control circuit 79 is applied to the switch circuit 80, and the power supply connected to the N + diffusion layer 33 is switched based on the output. Reference numeral 77 denotes a voltage detection circuit of the external power supply VCC, and reference numeral 78 denotes a VPP voltage detection circuit, the outputs of which are connected to the control circuit 79.
As the voltage detection circuit 78, a circuit similar to that of FIG. 6 can be used. Further, as the control circuit 79, a circuit similar to that of FIG. 7 can be used.

With the above-described structure, when the power supply is turned on, the N + type substrate 87 has N + diffusion until the external power supply VCC reaches a predetermined voltage level and VPP reaches a predetermined voltage level. The control circuit 79 operates so that VDD is connected via the layer 84. After VCC has reached a predetermined voltage level and VPP has reached a predetermined voltage level, VPP is connected to N-type substrate 87 via N + diffusion layer 84. Therefore, it is possible to prevent the latch-up caused when the voltage level of the P + diffusion layer 85 forming the source of the PMOS transistor becomes higher than the voltage level of the N-type substrate 87 when the power is turned on.

As described above, the circuit examples of the VPP voltage detection circuit and the control circuit are shown in FIGS. 6 and 7. However, the circuit configuration is not limited to the above configuration as long as the same effects can be obtained.

By the way, since VPP is generally used as a boosting power source for a word line, a desired voltage level is given by a threshold voltage of a memory cell transistor being Vtmc.
It is expressed as “VDD + Vtmc”. FIG.
A circuit example of a voltage detection circuit capable of obtaining a detection level of “DD + Vtmc” will be described. In the figure, 91 and 92 are P
MOS transistors, 93, 94, 95, 96 and 97 are NMOS transistors, and 98 and 99 are inverters. The internal power supply V
DD is VP at the drain of the NMOS transistor 95.
P is connected. VDD or VCC is connected to the gate of the NMOS transistor 93. Also,
The gate and drain of the PMOS transistor 91 are short-circuited and connected to the gate of the PMOS transistor 92, and N
The gate and drain of the MOS transistor 94 are short-circuited and connected to the gate of the NMOS transistor 96. Further, the output of the inverter 98 is fed back to the NMOS transistor 97 so as to have a hysteresis characteristic.

Here, the NMOS transistor 93 has a wide gate width and is used as a resistance component. NM
The OS transistor 95 is a transistor having the same threshold value Vtmc as the memory cell transistor. In a steady state, a DC voltage is applied between VDD and VSS via a PMOS transistor 91 and NMOS transistors 93 and 94.
A current flows, and the potential of the node P is VDD−Vtp,
The potential of the node N is Vtn. Vtn is NMO
This is the threshold voltage of the S transistor 94. Where P
Assuming that the threshold values of the MOS transistors 91 and 92 are equal and the threshold values of the NMOS transistors 94 and 96 are also equal, the NMOS transistor 96 is always ON. When the voltage level of VPP is lower than “VDD + Vtmc”, the NMOS transistor 95 is turned off, and the node A is connected to the VS via the NMOS transistor 96.
S is discharged, and the output 142 becomes “L”.
On the other hand, when the voltage level of VPP becomes equal to or higher than “VDD + Vtmc”, the NMOS transistor 95 and the PMOS transistor 92 are turned on, and a current flows between VPP and GND. When the voltage level of the node A becomes higher than the switching level of the inverter 98 due to the resistance division between VPP and GND, the output 100 becomes “H”. That is, in this voltage detection circuit, the voltage level of VPP is “VDD + Vt”.
When the voltage level of VPP is higher than “VDD + Vtmc”, “H” is output.

When the VPP level is low, the VPP generation circuit operates in response to the output "L" of the voltage detection circuit and supplies electric charge to the VPP node. Since the output of the detection circuit becomes “H”, the VPP generation circuit stops operating,
The supply of charges to the VPP node is stopped.

The VPP generation circuit is composed of an oscillation circuit and a pump circuit. If an external power supply VCC is used as the power supply of the oscillation circuit, the VPP generation circuit is directly affected by the voltage fluctuation of the VCC, and therefore has stable characteristics. In order to obtain this, it is preferable to use the internal power supply VDD. Here, the VPP generation circuit and the voltage detection circuit use the internal power supply VDD as a reference potential for the operation power supply and the detection level.
The DD generation circuit operates. Therefore, V
If the start of the operation of the DD generation circuit is delayed, the voltage detection circuit and the VPP circuit using VDD as a power supply when the power is turned on may not operate normally.

FIG. 11 is a block diagram showing the configuration of the fifth embodiment of the present invention which also solves the above problems. P + diffusion layers 114 and 115 are formed on an N-type substrate 116.
Is formed, and an N-type substrate 11 is formed.
6, in the N-Well 122, a P + diffusion layer 119,
A PMOS transistor including the transistor 120 is formed,
The N-Well 122 and the N-type substrate 116 have different potentials. Reference numeral 105 denotes a VDDA generation circuit.
It is connected to the P + diffusion layer 114 of the MOS transistor 1. Reference numeral 106 denotes a VPP generation circuit, and the N + diffusion layer 11
3 is connected to the N-type substrate 116. Reference numeral 107 denotes a VDDB generating circuit,
+ Diffusion layer 120 and N-Well 122 (N + diffusion layer 1).
21). 108 is a voltage detection circuit of VPP, 109 is a voltage detection circuit of VDDB,
These outputs are input to the control circuit 110. The output of the control circuit 110 is connected to the VDDA generation circuit 105.
Note that the VDDA generation circuit 105 is provided with the VDDB generation circuit 10.
This is the same configuration as FIG. The voltage detection circuit 108 has the same configuration as that of FIG.
A configuration similar to that described above can be used.

FIG. 12 is a timing chart showing each power supply waveform in this embodiment. In the figure, / PO
R (VDD) is an output of the voltage detection circuit 109, which detects the voltage level of VDDB when the power is turned on to “L” →
This signal is "H". At the beginning after the power is turned on, the voltage level of VPP does not have a sufficient voltage level with respect to VDDB serving as the reference potential, so that the output of voltage detection circuit 108 is “L” and the output of control circuit 110 is "And the VDDA generation circuit 105 is in an operation stop state. As the time elapses, the voltage level of VPP increases, and when the voltage level reaches “VDD + Vtmc” (t = t
3), the output of the voltage detection circuit 108 becomes “H”, the output of the control circuit 110 also becomes “H”, the VDDA generation circuit 105 starts operating, and VDDA starts to rise.

As described above, when turning on the power,
, Then VDDB rises, and then VPP
Rises to detect that the voltage level of VPP has reached a predetermined voltage level based on VDDB, and then the VDDA generation circuit 105 starts operating.
N-type substrate 116 of MOS transistor 1 and P + diffusion layer 1
Latch-up caused by conduction of the PN junction between the fourteen can be prevented, and an optimum VPP voltage level can be obtained. Moreover, by providing the VDDB generation circuit 107 separately from the VDDA generation circuit 105, it is possible to avoid a problem related to the operation of the VPP generation circuit 106 caused by delaying the operation start of the VDDA generation circuit 105.

In the first to fourth embodiments, a transistor having a structure in which a P-Well is formed on an N-type substrate is used. In the fifth embodiment, an N-W transistor is formed on an N-type substrate.
Although the description has been given of the transistor having the twin well structure in which the well is formed, the twin well in which the p-well is formed on the p-type substrate or the deep p (n) -well is formed first on the n (p) type substrate. , Its deep P (N) -We
The same effect can be obtained also in a transistor having a triple well structure in which an N (P) -Well is formed in an 11 region.

[0043]

According to the first and third aspects of the present invention, when the power is turned on, the N-type of the PMOS transistor is set via the N + diffusion layer.
After the voltage level of VPP connected to the substrate is established, VPP connected to the P + diffusion layer of the PMOS transistor is established.
Since the DD is generated, it is possible to prevent latch-up which may occur when the voltage level of the P + diffusion layer of the PMOS transistor and the voltage level of the N-type substrate are reversed when the power is turned on.

According to the second and fourth to sixth aspects of the present invention, when the power supply is turned on, VCC reaches a predetermined voltage level, and
Until the VPP level reaches a predetermined voltage level, P
The same VDD as that of the P + diffusion layer is connected to the N-type substrate of the MOS transistor via the N + diffusion layer, and after the voltage level of VPP is sufficiently established, VPP is connected to the N-type substrate via the N + diffusion layer. So that when power is turned on,
It is possible to prevent latch-up which may be caused by reversing the voltage level of the + diffusion layer and the voltage level of the N-type substrate.

Further, according to the seventh and eighth aspects, VD
Two D generating circuits are provided, and after the VPP level becomes sufficiently high based on the output level of the second VDD generating circuit,
Since the first VDD generating circuit connected to the P + diffusion layer is operated, the voltage level of VDD connected to the P + diffusion layer when the power is turned on and the VPP connected to the N-type substrate via the N + diffusion layer Latch-up, which may occur due to the reversal of the voltage level of the current, can be prevented. In addition, there is an effect that an optimum VPP voltage level can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a first embodiment of the present invention, including a schematic sectional view of a PMOS transistor;

FIG. 2 is a circuit diagram of a VDD generation circuit in the embodiment of FIG.

FIG. 3 is a timing chart showing operation waveforms of main parts in the embodiment of FIG. 1;

FIG. 4 is a block diagram including a schematic cross-sectional view of a PMOS transistor, showing a configuration of a main part of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a third embodiment of the present invention, including a schematic sectional view of a PMOS transistor;

FIG. 6 is a circuit diagram of a voltage detection circuit in the embodiment of FIG.

FIG. 7 is a circuit diagram of a control circuit in the embodiment of FIG.

8 is a timing chart showing operation waveforms of main parts in the embodiment of FIG.

FIG. 9 is a block diagram including a schematic cross-sectional view of a PMOS transistor, showing a configuration of a main part of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing another example of the voltage detection circuit.

FIG. 11 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit according to a fifth embodiment of the present invention, including a schematic cross-sectional view of a PMOS transistor.

FIG. 12 is a timing chart showing operation waveforms of main parts in the embodiment of FIG. 11;

FIG. 13 is a block diagram showing a power supply connection of each diffusion layer including a schematic cross-sectional view of a CMOS inverter in a conventional example.

FIG. 14 is a block diagram showing a power supply connection of each diffusion layer including a schematic sectional view of a CMOS inverter in another conventional example.

FIG. 15 is a circuit diagram of a VDD generation circuit used in the conventional example of FIGS. 13 and 14;

16 is a timing chart showing operation waveforms of main parts in the conventional example of FIG.

[Explanation of symbols]

 Reference Signs List 1 VDD generation circuit 2 VPP generation circuit 3 Voltage detection circuit 4 Delay circuit 5 External power supply 8 N + diffusion layer 9 P + diffusion layer 11 N-type substrate 29 Switch circuit 43, 44 Voltage detection circuit 45 Control circuit 80 Switch circuit 105 VDD generation circuit A 107 VDD generation circuit B

Claims (8)

[Claims] A first power supply generating circuit for generating a first power supply; and a second power supply generating circuit for generating a second power supply having a higher voltage level than the first power supply. Are connected to a P + diffusion layer forming a source of a PMOS transistor, and the second power supply is connected to a PMO
A semiconductor integrated circuit connected to the N-type substrate of the S transistor, further comprising a voltage detection circuit for detecting a voltage level of an external power supply at power-on to generate a signal whose logic is inverted, and an output signal of the voltage detection circuit. A semiconductor integrated circuit, comprising: a delay circuit that, as an input signal, delays the operation start time of the first power generation circuit from the operation start time of the second power generation circuit. 2. A power supply, comprising: a first power supply generating circuit for generating a first power supply; and a second power supply generating circuit for generating a second power supply having a voltage level higher than the first power supply. Is a semiconductor integrated circuit connected to a P + diffusion layer forming a source of a PMOS transistor, further comprising: a voltage detection circuit for detecting a voltage level of an external power supply at power-on to generate a signal whose logic is inverted; A delay circuit for generating a delay signal of time Δt using an output signal of the circuit as an input signal, and an output of the delay circuit as an input, and providing one of the first power supply and the second power supply with an N + diffusion layer And a switch circuit that is switched to be connected to the N-type substrate of the PMOS transistor through the switch. The switch circuit is configured to be switched based on an output signal of the delay circuit. Conductor integrated circuit. 3. A power supply, comprising: a first power supply generating circuit for generating a first power supply; and a second power supply generating circuit for generating a second power supply having a voltage level higher than the first power supply. Are connected to a P + diffusion layer forming a source of a PMOS transistor, and the second power supply is connected to a PMO
A semiconductor integrated circuit connected to the N-type substrate of the S transistor, further comprising: a first voltage detection circuit for detecting a voltage level of an external power supply at power-on to generate a signal whose logic is inverted; A second voltage detection circuit that detects a voltage level and generates a signal whose logic is inverted, and starts the first power generation circuit based on an output signal of the first voltage detection circuit and the second voltage detection circuit. A semiconductor integrated circuit, comprising: a control circuit. 4. A power supply comprising: a first power supply generating circuit for generating a first power supply; and a second power supply generating circuit for generating a second power supply having a higher voltage level than the first power supply. Is a semiconductor integrated circuit connected to a P + diffusion layer forming a source of a PMOS transistor, further comprising: a first voltage detection circuit for detecting a voltage level of an external power supply at power-on to generate a signal whose logic is inverted; A second voltage detection circuit that detects a voltage level of a second power supply and generates a signal whose logic is inverted, a control circuit that uses output signals of the first voltage detection circuit and the second voltage detection circuit as input signals, An output signal of the control circuit is used as an input signal, and one of the first power supply and the second power supply is switched to be connected to an N-type substrate of a PMOS transistor via an N + diffusion layer. A control circuit, wherein the control circuit includes the first voltage detection circuit and the second voltage detection circuit.
A semiconductor integrated circuit for outputting a signal for switching the switch circuit based on an output signal of a voltage detection circuit. 5. The detection level of the second voltage detection circuit is:
5. The semiconductor integrated circuit according to claim 3, wherein the voltage level is based on an external power supply. 6. A detection level of the second voltage detection circuit,
5. The semiconductor integrated circuit according to claim 3, wherein the voltage level is based on a voltage serving as a reference potential of the first power supply. 7. A first power supply, comprising: a first power supply generation circuit for generating a first power supply; and a second power supply generation circuit for generating a second power supply having a voltage level higher than that of the first power supply. Is connected to a first P + diffusion layer forming a source of a first PMOS transistor, and the second power supply is connected to a substrate of the first PMOS transistor via a first N + diffusion layer. Circuit, further comprising a third voltage source having the same voltage level as the first power supply.
And a second P + diffusion layer and a second N + forming a source of a second PMOS transistor formed on a different substrate from the first PMOS transistor.
A third power supply generation circuit connected to the diffusion layer, a first voltage detection circuit for detecting a voltage level of the third power supply when power is turned on and generating a signal whose logic is inverted, and a voltage of the second power supply A second voltage detection circuit for detecting a level to generate a signal whose logic is inverted, and controlling the first power supply generation circuit by using output signals of the voltage first voltage detection circuit and the second voltage detection circuit as input signals. A semiconductor integrated circuit, comprising: a control circuit that outputs a signal; wherein the first power generation circuit starts operating based on an output signal of the control circuit. 8. The detection level of the second voltage detection circuit is:
8. The semiconductor integrated circuit according to claim 7, wherein a third power generated by said third power generating circuit is used as a reference.