JPH11186887A - Delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the delay circuit with small dependence of a delay time on a power supply voltage. SOLUTION: A P channel MOS transistor(TR) 1 connects between an intermediate node N82 in inverters 81-84 and a capacitor 85 and an N channel MOS TR 3 connects between the node N82 and a capacitor 86. Then a level VCC or GND of an input node N80 is shifted by a threshold voltage of a MOS TR 2 or 4 and the shifted level is given to a gate of the MOS TRS 1, 3. Although drive capability of MOS TRs in the inverters 81-84 is increased more as a power supply VCC increases more, because the effect of the capacitors 85, 86 is increased, a delay time in the delay circuit is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a delay circuit,
In particular, the present invention relates to a delay circuit that delays a signal that is input to an input node and changes from a first power supply potential to a second power supply potential at a certain time by a predetermined time and outputs the delayed signal to an output node.

[0002]

2. Description of the Related Art Conventionally, a delay circuit for delaying an input signal by a predetermined time and outputting the same is provided in a semiconductor integrated circuit device such as a DRAM and an SRAM. The delay circuit is used, for example, to adjust the timing of signal transmission.

FIG. 16 is a circuit diagram showing a configuration of a conventional delay circuit. Referring to FIG. 16, this delay circuit includes inverters 81 to 8 of even-numbered stages (four stages in the figure) connected in series.
4 and capacitors 85 and 86 connected between the power supply potential VCC line and the ground potential GND line and the output node N82 of the second-stage inverter 82, respectively.

[0004] An inverter 81 is connected between a power supply potential VCC line and a ground potential GND line in series.
Channel MOS transistor 87 and N-channel MO
S transistor 88 is included. The gates of the MOS transistors 87 and 88 are commonly connected to form the input node N80 of the inverter 81, and the node between the MOS transistors 87 and 88 becomes the output node N81 of the inverter 81.
The back bias (well potential) of P channel MOS transistor 87 is ground potential GND or a constant negative potential, and the back bias of N channel MOS transistor 88 is power supply potential VCC.

When input signal VI is at "L" level (ground potential G
ND) rises to the "H" level (power supply potential VCC), P-channel MOS transistor 87 is turned off, N-channel MOS transistor 88 is turned on, and output node N81 changes from the "H" level to the "L" level. Discharged. Conversely, when input signal VI falls from "H" level to "L" level, P-channel MOS transistor 87 is turned on and N-channel MOS transistor 88 is turned off, so that output node N81 changes from "L" level. Charged to "H" level. The configurations and operations of other inverters 82 to 84 are the same as those of inverter 81.

The input node N80 of the first inverter 81
, That is, the level of the input signal VI is inverted,
The levels of output nodes N81 to N84 of inverters 81 to 84 are sequentially inverted. The level of the output node N84 of the final-stage inverter 84 becomes the output signal VO. Inverter 83 plays a role in shaping the signal waveform dull by capacitors 85 and 86, and inverter 84 provides input signal VI.
And the output signal V4.

As shown in FIG. 17A, the capacitor 85 is formed of a P-channel MOS transistor formed on the surface of an N-type well 90 of a semiconductor substrate. The source 91 and the drain 92 of the P-channel MOS transistor are both connected to the power supply potential VCC line, and the gate 94 is connected to the output node N82 of the inverter 82.

When node N82 is at "L" level, capacitor 85 is activated and well 9
A channel is formed at 0, and a predetermined capacitance is generated between the gate 94 and the channel via the gate oxide film 93. Conversely, when node N82 is at "H" level, capacitor 85 is inactivated and no channel is formed, so that the capacitance of capacitor 85 is extremely small. When the level of the node N82 is between the “L” level and the “H” level, a capacitance corresponding to the level is generated.

The capacitor 86 is formed of an N-channel MOS transistor formed on the surface of a P-type well 100 of a semiconductor substrate, as shown in FIG. N
The source 101 and the drain 102 of the channel MOS transistor are both connected to the ground potential GND line, and the gate 104 is connected to the output node N of the inverter 82.
82.

When node N 82 is at “H” level, capacitor 86 is activated, a channel is formed in well 100 below gate 104, and a predetermined amount is formed between gate 104 and the channel via gate oxide film 103. Capacitance occurs. Conversely, when node N82 is at "L" level, capacitor 86 is inactivated and no channel is formed, so that the capacitance of capacitor 86 is extremely small. When the level of the node N82 is between the “H” level and the “L” level, a capacitance corresponding to the level is generated.

Next, the operation of the delay circuit shown in FIGS. 16 and 17 will be described. When input signal VI is at “L” level, output nodes N81 of inverters 81-84
To N84 are “H” level, “L” level,
The levels are “H” level and “L” level. At this time, the capacitor 85 is activated and charged, and the capacitor 86 is inactivated and the capacitance is extremely small. The input signal VI changes from “L” level to “H”.
When the level falls, the levels of output nodes N81 to N84 of inverters 81 to 84 are sequentially inverted to "L" level, "H" level, "L" level and "H" level, respectively. At this time, the capacitor 85 is deactivated and its capacitance becomes extremely small, and the capacitor 86 is activated and charged. Therefore, the delay time of the delay circuit is the sum of the inversion time of the inverters 81 to 84 and the charge and discharge time of the capacitors 85 and 86.

Conversely, when input signal VI is at "H" level, output nodes N81 to N84 of inverters 81 to 84
Are respectively "L" level, "H" level, "L" level and "H" level. At this time, the capacitor 86 is activated and charged, and the capacitor 85 is inactivated and its capacitance is extremely small. When input signal VI falls from "H" level to "L" level, output nodes N81-N81 of inverters 81-84 are output.
The level of N84 is sequentially inverted, and the “H” level,
The “L” level, the “H” level, and the “L” level are set. At this time, the capacitor 86 is deactivated and its capacitance becomes extremely small, and the capacitor 85 is activated and charged. Also in this case, the delay time of the delay circuit is determined by the inversion time of inverters 81 to 84 and the capacitor 8.
It is the sum of the charge and discharge time of 5,86.

[0013]

By the way, in a semiconductor integrated circuit device, a power supply voltage has been reduced along with an increase in integration density. In recent years, a device having a high power supply voltage VCC (for example, 5 V) and a low power supply voltage VCC have been developed. For example, 3.3V)
Are mixed, and an ultra-low voltage (1.8 V or less) device is also being developed. In such a situation, it is desirable to have a device that operates similarly regardless of what power supply voltage is applied between the very low voltage and the high voltage. For this reason, the delay circuit is required to have a small voltage dependence of the delay time in a wide voltage range from an extremely low voltage to a high voltage.

However, in the conventional delay circuits shown in FIGS. 16 and 17, the difference between the delay times when the power supply voltage VCC is extremely low and when it is high is extremely large. This is because the MOS transistors 87 and 8 at high voltage
This is because the driving capability of the MOS transistors 87 and 88 becomes small and the voltage dependence becomes large when the voltage becomes extremely low, though the driving capability of the MOS transistor 8 is large and the voltage dependence is relatively small.

Therefore, in the conventional delay circuit, if the optimum delay time is set at an ultra-low voltage, the delay time becomes too short at a high voltage and normal operation cannot be performed. Conversely, the required delay time is set at a high voltage. Then, when the voltage is extremely low, the delay time increases, and a high-speed semiconductor integrated circuit cannot be obtained.

Therefore, a main object of the present invention is to provide a delay circuit in which the delay time has a small power supply voltage dependency.

[0017]

The invention according to claim 1 is
A delay circuit that is input to an input node, delays a signal that transits from a first power supply potential to a second power supply potential at a certain time by a predetermined time, and outputs the delayed signal to an output node, comprising at least one inverting circuit, a capacitor, A first transistor; and a reference potential generating unit. At least one inverting circuit is connected between the input node and the output node, and inverts and outputs a signal. One electrode of the capacitor is connected to a reference potential line. The first transistor is connected between the other electrode of the capacitor and the output node. The reference potential generating means sets the second power supply potential by a predetermined voltage so as to increase the driving capability of the first transistor in accordance with the increase in the potential difference between the first and second power supply potentials. Is applied to the input electrode of the first transistor.

According to a second aspect of the invention, at least one inverting circuit according to the first aspect of the present invention includes a second transistor of a first conductivity type and a third transistor of a second conductivity type. A second transistor of the first conductivity type is connected between the line of the first power supply potential and the output node, and its input electrode is connected to the input node. A third transistor of the second conductivity type is connected between the line of the second power supply potential and the output node, and its input electrode is connected to the input node.

According to a third aspect of the present invention, the reference potential generating means according to the first or second aspect of the present invention comprises:
And at least one fourth transistor connected between the first power supply potential and the second power supply potential, wherein the signal has transitioned from the first power supply potential to the second power supply potential. , The level of the second power supply potential of the input node is shifted toward the first power supply potential by the threshold voltage of at least one fourth transistor to generate a reference potential.

According to a fourth aspect of the present invention, the reference potential generating means according to the first or second aspect of the present invention includes at least a series connection between the second power supply potential line and the first power supply potential line. A reference potential is generated by shifting the level of the second power supply potential toward the first power supply potential by the threshold voltage of the at least one diode means.

According to a fifth aspect of the present invention, the delay circuit according to the fourth aspect of the present invention is provided in a semiconductor device, and the reference potential generating means is further connected in series with the diode means.
Including switch means that conducts only during the active period of the semiconductor device.

In the invention according to claim 6, claims 1 to 5 are provided.
A plurality of sets of the capacitor, the first transistor, and the reference potential generating means according to any one of the inventions are provided, and the driving capability of the first transistor increases in accordance with the increase in the potential difference between the first and second power supply potentials. The rate at which they are performed differs for each set.

According to a seventh aspect of the present invention, there is provided a delay circuit which delays a signal which is input to an input node and changes from a first power supply potential to a second power supply potential at a certain time by a predetermined time and outputs the delayed signal to an output node. A first transistor of a first conductivity type, a second transistor of a first conductivity type, a second transistor of a first conductivity type,
, A third transistor of the second conductivity type, a fourth transistor of the second conductivity type, and reference potential generating means.
A first electrode of a first transistor of a first conductivity type is connected to a line of a first power supply potential. A second transistor of the first conductivity type is connected between the second electrode of the first transistor and the output node, and its input electrode is connected to the input node. A first electrode of a third transistor of the second conductivity type is connected to a second power supply potential line. A fourth transistor of the second conductivity type is connected between the second electrode of the third transistor and the output node, and its input electrode is connected to the input node. The reference potential generating means is connected to the input electrodes of the first and third transistors, respectively, such that the driving capability of the first and third transistors decreases in accordance with the increase in the potential difference between the first and second power supply potentials. First and second reference potentials are provided.

According to an eighth aspect of the present invention, the fifth aspect of the present invention further comprises a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type. A fifth transistor of the first conductivity type is connected between the line of the first power supply potential and the output node, and its input electrode is connected to the input node. A sixth transistor of the second conductivity type is connected between the line of the second power supply potential and the output node, and its input electrode is connected to the input node.

In a ninth aspect of the present invention, a plurality of sets of the first to fourth transistors and the reference potential generating means of the eighth aspect of the present invention are provided, and the potential difference between the first and second power supply potentials is increased. The rate at which the driving capabilities of the first and third transistors decrease in accordance with the relationship varies for each set.

According to a tenth aspect of the present invention, there is provided a delay circuit which delays a signal which is input to an input node and transitions from a first power supply potential to a second power supply potential at a certain time by a predetermined time and outputs the delayed signal to an output node. And a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a back bias generating unit. A first transistor of the first conductivity type is connected between the first power supply potential line and the output node, and its input electrode is connected to the input node. A second transistor of the second conductivity type is connected between the line of the second power supply potential and the output node, and its input electrode is connected to the input node. The back bias generating means is provided on a substrate of the first and second transistors so that a threshold voltage of the first and second transistors increases in accordance with an increase in a potential difference between the first and second power supply potentials. A first and a second back bias are provided, respectively.

[0027]

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention. Referring to FIG. 1, this delay circuit differs from the delay circuit of FIG.
S transistors 1 and 2 and N channel MOS transistors 3 and 4 are newly provided.

P channel MOS transistor 1 is connected between capacitor 85 and output node N 82 of inverter 82. P-channel MOS transistor 2 is connected between input node N80 of the delay circuit and the gate (node N1) of P-channel MOS transistor 1, and its gate receives ground potential GND.

N channel MOS transistor 3 is connected between capacitor 86 and output node N 82 of inverter 82. N-channel MOS transistor 4 is connected between input node N80 of the delay circuit and the gate (node N3) of N-channel MOS transistor 3, and its gate receives power supply potential VCC.

Next, the operation of the delay circuit will be described. When input signal VI transitions from "L" level to "H" level, node N3 attains potential VCC-Vthn4 which is lower than power supply potential VCC by threshold voltage Vthn4 of N-channel MOS transistor 4. Power supply voltage VC
When C is at a high voltage, N-channel MOS transistor 3
Is sufficiently conductive and has high driving capability, but the power supply voltage VCC
Becomes lower, the driving capability of N-channel MOS transistor 3 decreases. Accordingly, when the voltage is high, the capacitor 86 is added, so that the delay time becomes longer due to the effect. Since the voltage rises only to the potential VCC-Vthn4 of the threshold voltage drop of 4, the influence of the capacitor 86 is almost eliminated.

That is, when the voltage is high, if the influence of the capacitor 86 is not exerted, the delay time is shortened because the driving capability of the MOS transistor is large. However, the delay time is actually so short because the influence of the capacitor 86 is large. No. At low voltage, the delay time is long because the driving capability of the MOS transistor is small.
Has almost no effect, and there is no difference in the delay time from the high voltage.

Conversely, when the input signal VI changes from the "H" level to the "L" level, the node N1 changes to the P-channel M
It becomes the threshold potential Vthp2 of the OS transistor 2.
When the power supply voltage VCC is high, the P-channel MOS transistor 1 conducts sufficiently and has a large driving capability, but as the power supply voltage VCC decreases, the driving capability of the P-channel MOS transistor 1 decreases. Therefore, when the voltage is high, the capacitor 85 is added, so that the delay time becomes longer due to the effect.
Since the driving capability of the S transistor 1 is small, and the gate of the capacitor 85 does not decrease to the ground potential GND but only to the threshold potential Vthp2 of the P-channel MOS transistor 2, the influence of the capacitor 85 is almost eliminated.

That is, when the voltage is high, if the effect of the capacitor 85 is not exerted, the delay time is shortened because the driving capability of the MOS transistors 87 and 88 is large, but the delay time is actually large because the effect of the capacitor 85 is large. Not so short. At low voltage, the MOS transistor 8
Although the delay time is long because the driving capability of 7,88 is small, there is almost no influence of the capacitor 85, so that there is no difference in the delay time with the high voltage.

As described above, in this embodiment, the difference in delay time can be eliminated in a wide power supply voltage range in any transition.

The capacitors 85 and 86 and the node N8
Since the signals input to the gates of the MOS transistors 1 and 3 for controlling the connection to the MOS transistor 2 change analogously from a low voltage to a high voltage, the specification of the power supply voltage may be in a continuous range from the low voltage to the high voltage. It is effective when it is.

Note that M inserted between input node N80 and node N1 and between input node N80 and node N3
The number of OS transistors connected in series and the threshold voltage of each MOS transistor may be set according to the standard of the power supply voltage range.

In this embodiment, the case where the capacitors 85 and 86 formed of MOS transistors are used has been described. However, a normal capacitor whose both electrodes are formed of metal may be used.

Further, in this embodiment, the delay circuit
The case where the inverters are constituted by the inverters 81 to 84 is described. However, the number of inverters is not limited to four, but may be an even number. If the inverter is used for inverting the input signal VI, an odd number may be used. . The rear two-stage inverter 83,
Reference numeral 84 denotes a circuit connected by the capacitors 85 and 86 in order to match the waveform of the dull signal waveform with the logic. When the input capacitance and the wiring capacitance of the next stage are small and there is no need to shape the waveform, or depending on the logic, 2 is used. It doesn't have to be a step.

In this embodiment, the inverter 8
Although the example in which the delay circuit is constituted by 1 to 84 has been described, the delay circuit may be constituted by a NAND gate or a NOR gate other than the inverter.

When the node N80 is directly connected to the MOS transistors 1 and 3 without providing the MOS transistors 2 and 4, the MOS transistors 1 and 3 conduct even when the power supply potential VCC is as low as about 1.5V. , Capacitor 8
The impact of 5,86 is still significant. Therefore, in this case, the effects of the capacitors 85 and 86 cannot be changed between the high voltage and the ultra-low voltage, and the power supply voltage dependence of the delay time cannot be eliminated.

[Second Embodiment] FIG. 2 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention. Referring to FIG. 2, this delay circuit is different from the delay circuit of FIG. 1 in that capacitors 85 and 86 are respectively connected to capacitors 85a and 85b; 86a and 86b.
It is divided and P channel MOS transistors 5 and 6 and N channel MOS transistors 7 and 8 are newly provided.

The P-channel MOS transistors 1 and 5
Each is connected between the gates of capacitors 85a and 85b and output node N82 of inverter 82. P-channel MOS transistor 6 is connected between node N1 and the gate (node N5) of P-channel MOS transistor 5, and its gate receives ground potential GND. N-channel MOS transistors 3 and 7 are connected between the gates of capacitors 86a and 86b and output node N82 of inverter 82, respectively. N-channel MOS transistor 8 is connected between node N3 and the gate of N-channel MOS transistor 7 (node N7), and its gate receives power supply potential VCC.

Next, the operation of the delay circuit will be described. When input signal VI transitions from "L" level to "H" level, node N3 attains VCC-Vthn4, which is lower than power supply potential VCC by threshold voltage Vthn4 of N-channel MOS transistor 4, and node N7 has power supply potential. VCC to N-channel MOS transistor 4,
The potential becomes VCC-Vthn4-Vthn8, which is lower by eight threshold voltages Vthn4 and Vthn8. At the time of high voltage, N-channel MOS transistors 3 and 7 are sufficiently conductive and have high driving capability, so that capacitors 86a and 86b
However, as the voltage becomes lower, the driving capability of N-channel MOS transistor 7 decreases, and the effect of capacitor 86b is almost eliminated. When the voltage is further lowered, the driving capability of N-channel MOS transistor 3 is weakened, and the effect of capacitor 86a is almost eliminated.

That is, at the time of high voltage, if there is no influence of the capacitors 86a and 86b, the MOS transistor 8
The delay time is shortened due to the large driving ability of the transistors 7, 88, but the delay time is not so short actually because the influence of the capacitors 86a, 86b is large. At low voltage, the delay time is long because the driving capability of the MOS transistors 87, 88 is small, but there is almost no effect of the capacitors 86a, 86b, so that there is no difference in delay time from high voltage. The same applies to the case where the input signal VI transitions from “H” level to “L” level.

In this embodiment, the same effect as in the first embodiment can be obtained. [Third Embodiment] FIG. 3 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention. Referring to FIG. 3, this delay circuit differs from the delay circuit of FIG. 1 in that capacitors 85 and 86 are divided into capacitors 85a and 85b; 86a and 86b, respectively.
The point is that channel MOS transistors 11 and 12 and N channel MOS transistors 13 and 14 are newly provided.

P channel MOS transistors 1 and 11
Are connected between the gates of capacitors 85a and 85b and nodes N82 and N83, respectively. P channel MO
S transistor 12 is connected to output node N of inverter 81.
81 is connected between the gate of P-channel MOS transistor 11 (node N11) and the gate of P-channel MOS transistor 12 receives ground potential GND.

N channel MOS transistors 3 and 13
Are connected between the gates of capacitors 86a and 86b and nodes N82 and N83, respectively. N-channel MO
S transistor 14 is connected to output node N of inverter 81.
It is connected between 81 and the gate of N channel MOS transistor 13 (node N13), and the gate of N channel MOS transistor 14 receives power supply potential VCC.

The delay time from input node N80 to node N82 has no voltage dependency due to the same operation as described in the first embodiment. Further, the delay time from the node N81 to the node N83 has no voltage dependency by the same operation. Therefore, the delay time from input node N80 to output node N84 does not depend on voltage in a wide power supply voltage range.

In combination with the second embodiment, a plurality of series-connected MOS transistors and capacitors are connected in parallel to one node, and the influence of the capacitors on the delay circuit is changed stepwise according to the power supply voltage. It does not matter.

[Fourth Embodiment] FIG. 4 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. Referring to FIG. 4, this delay circuit differs from the delay circuit of FIG. 1 in that inverters 83 and 84 are removed, the drains of MOS transistors 1 and 3 are connected to node N81 instead of node N82, and capacitor 85 , 86 are replaced by ordinary capacitors 15, 16. Capacitors 15 and 16 are composed of two dielectric films.
It is a normal capacitor sandwiched between two metal electrodes.

As in the first embodiment, the potentials of the gates (nodes N1 and N3) of MOS transistors 1 and 3 change so as to eliminate the power supply voltage dependence of the delay time of the delay circuit. Further, since capacitors 15 and 16 are not capacitors formed of MOS transistors but are ordinary capacitors, MOS transistors 1 and 3 operate at high voltage regardless of whether node N81 is at "L" level or "H" level. When conductive, it functions as a capacitor. Therefore, it is possible to eliminate the dependency of the delay time on the power supply voltage in a wide range of the power supply voltage VCC.

In this embodiment, two delay circuits are used.
Although the description has been given of the case where the inverter is composed of two stages,
The number of stages is not limited to the number of stages, and may be an even number of stages, and may be an odd number of stages if used for inverting the input signal VI. The rear-stage inverter 82 is connected to shape the signal waveform dulled by the capacitors 15 and 16 and to match the logic of the input signal VI and the output signal VO. In the case where the input capacitance or wiring capacitance of the next stage is small and it is not necessary to shape the waveform, or depending on the logic, one stage may be used.

[Fifth Embodiment] FIG. 5 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. Referring to FIG. 5, this delay circuit
This is a circuit in which the circuits of Embodiment 2 and Embodiment 4 are combined. That is, this delay circuit is different from the delay circuit of FIG. 2 in that inverters 83 and 84 are removed, drains of MOS transistors 1, 3, 5, and 7 are connected to node N81 instead of node N82, and capacitors 85a and 85
b, 86a, 86b are capacitors 15a, 15b, 16
a and 16b. The capacitors 15a and 15b are obtained by dividing the capacitor 15 into two, and the capacitors 16a and 16b are obtained by dividing the capacitor 16 into two.

The potentials of the gates (nodes N1, N3, N5, N7) of MOS transistors 1, 3, 5, and 7 change so as to eliminate the power supply voltage dependence of the delay time of the delay circuit, as in the second embodiment. I do. MOS transistors 1 and 2
When the nodes 3, 5, and 7 are turned on, regardless of whether the node N81 is at the "L" level or the "H" level, the capacitor 1
5a, 15b, 16a, and 16b function as capacitors. Therefore, it is possible to eliminate the dependency of the delay time on the power supply voltage in a wide range of the power supply voltage VCC.

[Sixth Embodiment] FIG. 6 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. Referring to FIG. 6, this delay circuit
Two-stage inverters 81 and 82 connected in series, reference potential generation circuits 17 and 18, a capacitor 85 and a P-channel MOS transistor 19 connected in series between a power supply potential VCC line and an output node N81 of inverter 81. And a capacitor 86 connected in series between the ground potential GND line and the output node N81 of the inverter 81.
And an N-channel MOS transistor 20.

The gate of P channel MOS transistor 19 has reference potential VRP generated by reference potential generating circuit 17.
In response, the gate of N-channel MOS transistor 20 receives reference potential VRN generated by reference potential generating circuit 18. The reference potential VRP increases the driving capability of the P-channel MOS transistor 19 when the power supply potential VCC is high, and increases the driving capability of the P-channel MOS transistor 19 when the power supply potential VCC is low.
To reduce the driving ability of the motor. Reference potential VR
N is an N-channel MOS when the power supply voltage VCC is high.
The driving capability of the transistor 20 is increased, and the driving capability of the N-channel MOS transistor 20 is reduced at a low voltage.

When the power supply voltage VCC is high, the MOS
Since the driving capability of transistors 19 and 20 is large, capacitors 85 and 86 are added to output node N81 of inverter 81, and thus the delay time becomes long. When the voltage is low, the driving capability of MOS transistors 19 and 20 is small, so that capacitor 8 is connected to output node N81 of inverter 81.
The effect of 5,86 is almost eliminated. As a result, the voltage dependence of the delay time can be eliminated.

In this embodiment, the case where the capacitors 85 and 86 formed of MOS transistors are used has been described, but a normal capacitor having a dielectric film sandwiched between two metal electrodes may be used.

In this embodiment, the delay circuit is
Although the case has been described in which the inverters are constituted by the inverters 81 and 82 in stages, the number of inverters is not limited to two, but may be an even stage, and may be an odd stage if the input signal VI is inverted.

Further, in this embodiment, an example has been shown in which the delay circuit is constituted by an inverter.
An AND gate or a NOR gate may be used.

FIGS. 7A and 7B are circuit diagrams illustrating the configurations of the reference potential generating circuits 17 and 18, respectively. Reference potential generation circuit 17 includes P-channel MOS transistors 21 and 22 and resistance element 23. P-channel MOS transistor 21 and resistance element 23 are each connected between a line of power supply potential VCC and output node N21, and P-channel MOS transistor 22 is connected between output node N21 and a line of ground potential GND. . The gates of P-channel MOS transistors 21 and 22 are connected to a power supply potential VCC line and a ground potential GND line, respectively.

Reference potential generating circuit 18 includes N-channel MOS transistors 31 and 32 and a resistance element 33. N-channel MOS transistor 31 has power supply potential V
N is connected between the line CC and the output node N31.
Channel MOS transistor 32 and resistance element 33
Are connected between the output node N31 and the line of the ground potential GND, respectively. Gates of N-channel MOS transistors 31 and 32 are connected to a power supply potential VCC line and a ground potential GND line, respectively.

The MOS transistors 21 and 32 and the resistance elements 23 and 33 are provided to prevent a small current from flowing to the output nodes N21 and N31 to prevent the output nodes N21 and N31 from floating. Output node N2
Reference potentials VRP and VRN corresponding to the power supply potential VCC are output from 1 and N31, respectively.

According to such reference potential generation circuits 17 and 18, since reference potentials VRP and VRN change analogously from low voltage to high voltage, the standard of power supply voltage VCC is continuously changed from low voltage to high voltage. This is effective in such a case.

As elements for preventing output nodes N21 and N31 from becoming floating, resistance elements 23 and 33 and MOS transistor 2 in the cut region are used.
Alternatively, only one of 1, 31 may be provided.

Also, as shown in FIG.
S transistor 24 and P-channel MOS transistor 34 may be further provided. N-channel MOS transistor 24 is connected between the drain of P-channel MOS transistor 22 and the line of ground potential GND, and receives signal CS at its gate. P-channel MOS transistor 34 is connected between the drain of N-channel MOS transistor 31 and the line of power supply potential VCC, and has its gate receiving signal / CS.

In the standby state of the semiconductor integrated circuit device, signal CS attains the "L" level, and MOS transistor 24,
34 becomes non-conductive, the reference potential generating circuit is inactivated, and current consumption is reduced. When the semiconductor integrated circuit device is active, signal CS attains the "H" level, MOS transistors 24 and 34 are turned on, the reference potential generating circuit is activated, and reference potentials VRP and VRN are output.

As shown in FIGS. 9A and 9B,
P channel MOS transistor 24 and N channel M
P-channel MOS transistors 25 and 26 and N-channel MOS transistors 35 and 36 may be provided instead of OS transistor 34. P-channel MOS transistors 25 and 26 are connected between the line of power supply potential VCC and the source of P-channel MOS transistor 21 and resistance element 23, respectively, and both gates receive signal / CS. N channel MOS transistor 3
Reference numerals 5 and 36 denote a ground potential GND line, the source of the N-channel MOS transistor 32 and the resistance element 3 respectively.
3 and each gate receives the signal CS together.

In the standby state of the semiconductor integrated circuit device, signal CS attains the "L" level, and MOS transistor 25,
26, 35, and 36 become nonconductive, the reference potential generating circuit is inactivated, and current consumption is reduced. When the semiconductor integrated circuit device is active, the signal CS becomes “H” level,
The MOS transistors 25, 26, 35, and 36 are turned on to activate the reference potential generation circuit, and the reference potentials VRP, VR
N is output.

As shown in FIGS. 10A and 10B, any one of the reference potential generating circuits of FIGS. 7 to 9 (the circuit of FIG. 8 is used in FIG. 10). ), The reference potentials VRP and VRN generated by
The output may be output via switching inverters 41, 42; More specifically, each of switching inverters 41 to 44 includes P-channel MOS transistors 45 and 46 and N-channel MOS transistors 47 and 48 connected in series between a power supply potential VCC line and a ground potential GND line. The gate of P channel MOS transistor 45 receives signal / CS,
The gate of N-channel MOS transistor 48 is connected to signal CS.
Accordingly, MOS transistors 46 and 47 form an inverter. When the signal CS goes to the “H” level in the active mode, the MOS transistors 45 and 48 are turned on and M
The inverter including the OS transistors 46 and 47 is activated. When power supply voltage VCC is high, reference potentials VRP and VRN attain an "L" level and an "H" level, respectively, and MOS transistor 1 of the delay circuit in FIG.
9 and 20 conduct. When power supply voltage VCC is low, reference potentials VRP and VRN attain "H" level and "L" level, respectively, and MOS transistors 19 and 20 of the delay circuit in FIG. 6 are turned off. Thereby, the voltage dependence of the delay time can be eliminated. This reference potential generating circuit is effective when an ultra-low voltage product and a high voltage product are made with one mask set.

The reference potential VR having the characteristics described above
Any circuit other than the circuits shown in FIGS. 7 to 10 may be used as long as P and VRN can be obtained.

[Seventh Embodiment] FIG. 11 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a seventh embodiment of the present invention. Referring to FIG. 11, this delay circuit includes two stages of inverters 81 and 82 connected in series, reference potential generating circuits 51 and 52, and a power supply potential VCC line and an output node N 81 of inverter 81. A capacitor 85a and a P-channel MOS transistor 53 connected in series, a power supply potential VCC line and an inverter 8
A capacitor 85b and a P-channel MOS transistor 55 connected in series with the first output node N81;
A capacitor 86a and an N-channel MOS transistor 54 connected in series between a line of ground potential GND and an output node N81 of inverter 81;
86b and N channel MO connected in series between the
And an S transistor 56. The gates of P-channel MOS transistors 53 and 55 receive reference potentials VRP1 and VRN2 generated by reference potential generating circuit 51. The gates of N-channel MOS transistors 54 and 56 are connected to reference potentials VRN1 and VR generated by reference potential generating circuit 52, respectively.
Receive N2.

Reference potentials VRP1, VRP2, VRN1,
VRN2 changes as follows. That is, when the power supply voltage VCC is high, the MOS transistors 53 to 5
6 becomes large, and the MOS transistors 53-5
6 conducts well. When the power supply voltage VCC decreases, M
The driving capability of the OS transistors 53 and 54 decreases.
When the power supply voltage VCC further decreases, the driving capability of MOS transistors 55 and 56 decreases, and capacitor 85
The effects of a, 85b, 86a, and 86b are almost eliminated. Reference potentials VRP1, VRP2, VRN1, VRN2
May be generated by a circuit as shown in FIGS.

When the power supply voltage VCC is high, the MOS
Since the driving capability of the transistors 53 to 56 is large, the capacitors 85a and 85 are connected to the output node N81 of the inverter 81.
5b, 86a and 86b are added, so that the delay time becomes longer. When the power supply potential VCC becomes low, the driving capability of the MOS transistors 53 and 54 decreases, and the effects of the capacitors 85a and 86a are almost eliminated. When the power supply voltage VCC further decreases, the driving capabilities of the MOS transistors 55 and 56 also decrease, and the effects of all the capacitors 85a, 85b, 86a and 86b are almost eliminated. As a result, the voltage dependence of the delay time can be eliminated.

In this embodiment, a series connection of a MOS transistor and a capacitor is connected to the power supply side and the ground side.
Although each pair is provided, three or more pairs may be connected to each of the power supply side and the ground side.

[Eighth Embodiment] FIG. 12 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. Referring to FIG. 12, the delay circuit includes an inverter 81, a reference potential generation circuit 57,
58, P-channel MOS transistors 61 and 62 and N-channel MOS transistors 63 and 64.

Reference potential generating circuits 57 and 58 output reference potentials VRP and VRN in accordance with power supply potential VCC, respectively. P channel MOS transistors 61 and 62 are connected to a line of power supply potential VCC and output node N8 of inverter 81.
The N-channel MOS transistors 63 and 64 are connected in series between the output node N81 of the inverter 81 and the line of the ground potential GND. MOS
The gates of transistors 61 and 64 are connected to reference potentials VRP and VRP output from reference potential generation circuits 57 and 58, respectively.
Receive RN. The gates of the MOS transistors 62 and 63 are connected to the MOS transistor 8 of the inverter 81, respectively.
7,88 gates.

The reference potential VRP is such that when the power supply voltage VCC is at a high voltage, the driving capability of the P-channel MOS transistor 61 is small and the P-channel MOS transistor 61 hardly conducts. The driving capability of the transistor 61 increases, and the P-channel MOS transistor 61 changes so as to conduct sufficiently. Reference potential VRN changes such that N-channel MOS transistor 64 hardly conducts when power supply voltage VCC is high, and N-channel MOS transistor 64 sufficiently conducts when power supply voltage VCC is low.

Next, the operation of the delay circuit will be described. When input signal VI transitions from the "L" level to the "H" level, if power supply voltage VCC is at a high voltage, N-channel MOS transistor 64 is hardly conductive, and output node N81 is controlled by N-channel MOS transistor 88. Reduced to "L" level, N channel M
N channel MOS transistors 63 and 64 connected in parallel to OS transistor 88 have almost no effect. When the power supply potential VCC is low, the N-channel MO
Since S transistor 64 is sufficiently conductive, output node N81 is pulled down to the "L" level by both N channel MOS transistor 88 and N channel MOS transistors 63 and 64 connected in parallel thereto. As a result, in this delay circuit, the voltage dependence of the delay time in a wide power supply voltage VCC is eliminated. Similarly, when the input signal VI transitions from the “H” level to the “L” level, the voltage dependence of the delay time is eliminated.

When this delay circuit is connected to an even number of stages,
A delay circuit having no voltage dependency in a wide range of power supply voltage VCC and not inverting the logic of input signal VI can be configured. Further, when the odd number of delay circuits are connected, it is possible to configure a delay circuit that has no voltage dependency over a wide range of power supply voltage VCC and inverts the logic of input signal VI.

In this embodiment, an example in which the present invention is applied to the inverter 81 has been described. However, the present invention can be applied to a NAND gate or a NOR gate other than the inverter 81.

Further, the circuit of this embodiment may be combined with the circuits shown in the first to seventh embodiments. For example, capacitors may be inserted between the power supply potential VCC line and the source of P-channel MOS transistor 61 and between the ground potential GND line and the source of N-channel MOS transistor 64, respectively.

Ninth Embodiment FIG. 13 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a ninth embodiment of the present invention. Referring to FIG. 13, this delay circuit differs from the delay circuit of FIG. 12 in that reference potential generation circuits 55 and 56 are replaced by reference potential generation circuits 71 and 72, and P channel MOS transistors 65 and 66 and N channel MOS transistors 67 and 68 are newly provided.

Reference potential generating circuits 71 and 72 output reference potentials VRP1 and VRP2 and reference potentials VRN1 and VRN2 according to power supply potential VCC, respectively. N-channel MOS transistors 65 and 66 are connected in series between a power supply potential VCC line and an output node N81 of inverter 81, and N-channel MOS transistors 67 and 68 are connected between output node N81 of inverter 81 and a ground potential GND line. Connected in series.

P channel MOS transistors 61 and 65
Receive reference potentials VRP1 and VRP2 from reference potential generating circuit 71, respectively. Gates of N-channel MOS transistors 65 and 68 receive reference potentials VRN1 and VRN2 from reference potential generating circuit 72, respectively. The gates of N-channel MOS transistors 66 and 67 are connected to MOS transistor 8 of inverter 81, respectively.
7,88 gates.

Reference potentials VRP1, VRP2, VRN1,
VRN2 changes as follows. When power supply voltage VCC is high, P-channel MOS transistors 61 and 6
5 and N-channel MOS transistors 64 and 68 hardly conduct. When the power supply voltage VCC decreases, MO
The S transistors 61 and 64 become conductive. When the power supply voltage VCC further decreases, the MOS transistor 65,
68 also conducts well.

When input signal VI transitions from "L" level to "H" level, when power supply voltage VCC is at a high voltage, MOS transistors 61, 64, 65, and 68 hardly conduct, so output node N81 is at a low level. N channel M
N-channel MOS transistors 63, 64, 64 pulled down to “L” level by OS transistor 88 and connected in parallel with N-channel MOS transistor 88
There is almost no effect of 67 and 68.

When power supply potential VCC falls, N-channel MOS transistor 64 becomes sufficiently conductive, and output node N81 is connected to N-channel MOS transistor 64 and N-channel MOS transistor 64 connected in parallel thereto.
It is lowered to “L” level by both OS transistors 63 and 64.

When power supply voltage VCC further decreases, N-channel MOS transistor 68 also becomes sufficiently conductive, and output node N81 is connected to N-channel MOS transistor 88 and N-channel M transistor connected in parallel thereto.
OS transistors 63 and 64 and N-channel MOS transistors 67 and 68 lower the level to "L" level. Thus, in this delay circuit, the voltage dependence of the delay time in a wide range of power supply voltage VCC is eliminated. Similarly, when the input signal VI transitions from the “H” level to the “L” level, the voltage dependence of the delay time is eliminated.

In this embodiment, two MOS transistors
Although a case has been described where two sets of series-connected transistors are connected to the power supply side and the ground side, three or more sets may be connected to the power supply side and the ground side, respectively.

The circuit of this embodiment may be combined with the circuits of the first to seventh embodiments.

[Tenth Embodiment] FIG. 14 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a tenth embodiment of the present invention. Referring to FIG.
This delay circuit differs from the conventional delay circuit of FIG.
The difference is that a VBBP generation circuit 73 and a VBBN generation circuit 74 are newly provided. VBBP generation circuit 73
Outputs the back bias VBBP of the P-channel MOS transistors 87 of the inverters 81 to 84. VBB
N generation circuit 74 outputs a back bias VBBN of N channel MOS transistor 88 of inverters 81-84.

The back bias VBBP is equal to the power supply voltage VC.
This is a positive potential that becomes low when C is at a high voltage and becomes high when the power supply voltage VCC is at a low voltage. Back bias VB
BN is a negative potential that becomes deep when the power supply voltage VCC is high and becomes shallow when the power supply voltage VCC is low. Such back bias VBBP, VBBN is set to M
When applied to the OS transistors 87 and 88, the threshold voltages of the MOS transistors 87 and 88 increase when the voltage is high, and the threshold voltages of the MOS transistors 87 and 88 decrease when the voltage is low. This makes it possible to compensate for the voltage dependency of the driving capability of MOS transistors 87 and 88, and eliminate the voltage dependency of the delay time.

The MOS transistors of the circuits shown in the first to ninth embodiments may be provided with the back bias VBBP and VBBN having the voltage dependency as in this embodiment. By doing so, a greater effect can be obtained for realizing a delay circuit having no voltage dependence over a wide range of power supply voltages.

That is, normally, the back bias of the P-channel MOS transistor is the power supply potential VCC, and the back bias of the N-channel MOS transistor is the ground potential GND. In this case, when the power supply potential VCC decreases, the threshold voltage of the P-channel MOS transistor increases, so that the delay time increases. Therefore, the voltage dependence of the delay time can be further reduced by changing the back bias of the MOS transistors of the first to ninth embodiments as in the tenth embodiment.

FIG. 15 is a circuit block diagram illustrating the configuration of VBBN generation circuit 74. Referring to FIG. 15, VBBN generating circuit 74 includes a charge pump circuit 75.
And a level detection circuit 76. Charge pump circuit 75 includes a ring oscillator and a pump capacitor, discharges positive charges from the P-type well in which N-channel MOS transistor 88 is formed, and sets the P-type well to a negative potential. The positive charge discharging capability of the charge pump circuit 75 increases as the power supply voltage VCC increases. Therefore, the higher the power supply voltage VCC, the deeper the potential of the P-type well, that is, the back bias VBBN, in the negative direction.

The level detection circuit 76 is an N-channel MOS
The potential of the P-type well in which the transistor 88 is formed is detected, and when the potential becomes deeper than the reference potential, a signal STP is supplied to the charge pump circuit 75 to charge the charge pump circuit 7.
5 is stopped. The reference potential has a power supply voltage dependency, and the higher the power supply voltage VCC is, the more the signal STP is not output until the back bias VBBN becomes deeper. As a result, it is possible to generate a deeper back bias VBBN as the power supply voltage VCC becomes higher.

[0098]

As described above, according to the first aspect of the present invention, the capacitor and the first transistor are connected in series between the reference potential line and the output node of the delay circuit, and the first and second power supplies are connected. A reference in which the second power supply potential is level-shifted to the first power supply potential side by a predetermined voltage so that the driving capability of the first transistor increases in accordance with the potential difference between the potentials, that is, the increase in the power supply voltage. A potential is applied to the input electrode of the first transistor. Therefore, even if the power supply voltage increases and the driving capability of the inverting circuit increases, the driving capability of the first transistor increases and the effect of the capacitor increases, so that the voltage dependence of the delay time of the delay circuit is reduced. be able to.

According to a second aspect of the present invention, at least one inverting circuit according to the first aspect of the present invention includes a second conductive type second conductive circuit connected in series between the first and second power supply potential lines. A transistor and a third transistor of the second conductivity type. Thereby, an inversion circuit can be easily configured.

According to a third aspect of the present invention, the reference potential generating means according to the first or second aspect of the present invention comprises:
And at least one fourth transistor connected between the input electrode of the first transistor and the second power supply potential applied to the input node by the threshold voltage of the at least one fourth transistor. The reference potential is generated by shifting the level to the power supply potential side. In this case, the reference potential can be generated with a very simple configuration.

According to a fourth aspect of the present invention, the reference potential generating means of the first or second aspect of the present invention comprises at least one diode means and a resistance element connected in series between the second and first power supply potential lines. And the level of the second power supply potential is shifted between the first power supply potential by the threshold voltage of at least one diode means to generate a reference potential. In this case, a stable reference potential can be generated.

According to a fifth aspect of the present invention, the delay circuit according to the fourth aspect of the present invention is provided in a semiconductor device, and the reference potential generating means is further connected in series with the diode means.
Including switch means that conducts only during the active period of the semiconductor device. In this case, it is possible to prevent a through current from flowing to the reference potential generating circuit in a standby period other than the active period of the semiconductor device, and to reduce current consumption.

In the invention according to claim 6, claims 1 to 5
A plurality of sets of the capacitor, the first transistor, and the reference potential generating means according to any one of the inventions are provided, and the driving capability of the first transistor increases in accordance with the increase in the potential difference between the first and second power supply potentials. The proportions differ for each set. In this case, the effect of the capacitor on the increase in the power supply voltage can be finely adjusted, and the voltage dependence of the delay time of the delay circuit can be further reduced.

According to the seventh aspect of the present invention, the first and the second
The first and second transistors of the first conductivity type and the fourth and third transistors of the second conductivity type are connected in series between power supply potential lines, and an inverter is formed by the second and fourth transistors. And the input electrodes of the first and third transistors are connected to the input electrodes of the first and third transistors, respectively, so that the driving capability of the first and third transistors decreases in accordance with the potential difference between the first and second power supply potentials, that is, the increase in the power supply voltage. First
And a second reference potential. Therefore, even if the power supply voltage increases and the driving capabilities of the second and fourth transistors increase, the driving capabilities of the first and third transistors decrease, so that the voltage dependence of the delay time of the delay circuit is reduced. can do.

According to an eighth aspect of the present invention, in addition to the seventh aspect, the fifth transistor of the first conductivity type and the second conductivity type connected in series between the first and second power supply potential lines are provided. An inverter comprising a sixth transistor of the type is further provided. In this case, even if the power supply voltage increases and the driving capabilities of the second, fourth, fifth, and sixth transistors increase, the driving capabilities of the first and third transistors decrease. Voltage dependency of the delay time can be reduced.

According to the ninth aspect of the present invention, a plurality of sets of the first to fourth transistors and the reference potential generating means of the eighth aspect of the present invention are provided to reduce the potential difference between the first and second power supply potentials. The rate at which the driving capabilities of the first and third transistors decrease accordingly differs for each set. In this case, the voltage dependence of the delay time of the delay circuit can be further reduced.

According to the tenth aspect, the first transistor of the first conductivity type and the second transistor of the second conductivity type are connected in series between the lines of the first and second power supply potentials, The first and second transistors have first and second transistors, respectively, so that the threshold voltage of the first and second transistors increases in accordance with the potential difference between the first and second power supply potentials, that is, the increase in the power supply voltage. And a second back bias. Therefore, the power supply voltage increases and the first
Even if the driving capability of the second transistor increases, the threshold voltage of the first and second transistors increases, so that the voltage dependence of the delay time of the delay circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating the configuration of a reference potential generating circuit shown in FIG. 6;

8 is a circuit diagram showing an improved example of the reference potential generation circuit shown in FIG.

FIG. 9 is a circuit diagram showing another modified example of the reference potential generation circuit shown in FIG. 7;

FIG. 10 is a circuit diagram showing still another improved example of the reference potential generation circuit shown in FIG. 7;

FIG. 11 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 12 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 13 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

FIG. 14 is a circuit block diagram showing a configuration of a delay circuit of a semiconductor integrated circuit device according to a tenth embodiment of the present invention.

FIG. 15 is a circuit block diagram illustrating a configuration of a VBBN generation circuit shown in FIG. 14;

FIG. 16 is a circuit diagram showing a configuration of a delay circuit of a conventional semiconductor integrated circuit device.

FIG. 17 is a cross-sectional view showing a configuration of the capacitor shown in FIG.

[Explanation of symbols]

1,2,5,6,11,19,21,22,25,2
6,34,45,46,53,55,61,62,6
5, 66, 87 P-channel MOS transistors, 3,
4,7,8,13,20,24,31,32,35,3
6,47,48,54,56,63,64,67,6
8,88 N-channel MOS transistors, 15,1
6,85,86 capacitors, 17,18,51,5
2, 57, 58, 71, 72 Reference potential generation circuit, 2
3, 33 resistance element, 41 to 43 switching inverter, 73 VBBP generation circuit, 74 VBBN generation circuit, 75 charge pump circuit, 76 level detection circuit, 81 to 84 inverter, 90, 100 well,
91, 101 source, 92, 102 drain, 9
3,103 gate oxide film, 94,104 gate.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Eiki Kawamura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (10)

[Claims] An input is input to an input node, and at a certain time, a first
A delay circuit that delays a signal that transitions from the power supply potential to the second power supply potential by a predetermined time and outputs the delayed signal to an output node, wherein the delay circuit is connected between the input node and the output node, and inverts the signal. At least one inverting circuit for outputting, a capacitor having one electrode connected to a line of a reference potential, a first transistor connected between the other electrode of the capacitor and the output node, and the first and second transistors The level of the second power supply potential is shifted toward the first power supply potential by a predetermined voltage so that the driving capability of the first transistor increases in accordance with the increase in the potential difference between the power supply potentials. A reference potential generating means for applying a reference potential to an input electrode of the first transistor. 2. The at least one inverting circuit is connected between the first power supply potential line and the output node, and has an input electrode connected to the input node. Two transistors, and the second
2. The delay circuit according to claim 1, further comprising a third transistor of a second conductivity type connected between the power supply potential line and the output node, the input electrode of which is connected to the input node. 3. 3. The at least one fourth transistor connected between the input node and an input electrode of the first transistor, the input electrode receiving the second power supply potential. Responsive to a transition of the signal from the first power supply potential to the second power supply potential, the second power supply potential of the input node to a threshold voltage of the at least one fourth transistor. 3. The delay circuit according to claim 1, wherein the reference potential is generated by shifting a level of the reference potential toward the first power supply potential by a voltage. 4. 4. The reference potential generating means includes at least one diode means and a resistance element connected in series between the line of the second power supply potential and the line of the first power supply potential, and 3. The delay circuit according to claim 1, wherein the reference potential is generated by level-shifting the second power supply potential toward the first power supply potential by the threshold voltage of the at least one diode unit. 4. 5. The semiconductor device according to claim 5, wherein the delay circuit is provided in a semiconductor device, and the reference potential generating unit further includes a switch unit connected in series with the diode unit and conducting only during an active period of the semiconductor device. 5. The delay circuit according to 4. 6. A plurality of sets of said capacitor, said first transistor and said reference potential generating means are provided, and said first transistor is driven according to an increase in a potential difference between said first and second power supply potentials. The delay circuit according to any one of claims 1 to 5, wherein a rate at which the capability increases is different for each set. 7. An input signal is input to an input node, and the first
A delay circuit that delays a signal that changes from the power supply potential to the second power supply potential by a predetermined time and outputs the delayed signal to an output node, wherein a first electrode of the delay circuit is connected to the line of the first power supply potential. A first transistor of the first conductivity type, a second transistor connected between a second electrode of the first transistor and the output node, and an input electrode connected to the input node; A third transistor of a second conductivity type connected to the line of the second power supply potential, connected between a second electrode of the third transistor and the output node, and an input electrode thereof Decreases the drive capability of the fourth transistor of the second conductivity type connected to the input node, and the first and third transistors in response to an increase in the potential difference between the first and second power supply potentials You And a reference potential generating means for applying first and second reference potentials to input electrodes of the first and third transistors, respectively. 8. A fifth transistor of a first conductivity type, which is connected between the first power supply potential line and the output node, and whose input electrode is connected to the input node, and 8. The delay circuit according to claim 7, wherein a sixth transistor of a second conductivity type is connected between a line of a second power supply potential and said output node, and has an input electrode connected to said input node. . 9. A plurality of sets of said first to fourth transistors and said reference potential generating means are provided, and said first and third transistors are set according to an increase in a potential difference between said first and second power supply potentials. 9. The delay circuit according to claim 8, wherein the rate at which the driving capability of the transistor decreases differs for each set. 10. A delay circuit that is input to an input node, delays a signal that transitions from a first power supply potential to a second power supply potential at a certain time by a predetermined time, and outputs the delayed signal to an output node. A first transistor of a first conductivity type connected between a power supply potential line and the output node, the input electrode of which is connected to the input node; the second power supply potential line and the output node And a second transistor of a second conductivity type whose input electrode is connected to the input node; and
The first and second transistors are provided on the substrates of the first and second transistors, respectively, such that the threshold voltages of the first and second transistors increase in accordance with the increase in the potential difference between the first and second power supply potentials. A delay circuit, comprising: a back bias generating means for applying a back bias.