JP2000138348A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be protected against the occurrence of latch-ups after power is applied. SOLUTION: This semiconductor device operates in such a manner that transistors MN1, MN2, MP1, and MP2 are operated under the control of a reset circuit 14 until sufficient time elapses after a power supply is applied, including a time from a point of time when a power supply VDD2 is applied to another time when a power supply VDD1 is applied, an N well 11 is connected to a power supply voltage VDD2 terminal, and a P well 12 is connected to a ground potential VSS terminal. With this setup, a substrate potential can be restrained from falling into a floating state so as not to cause a latch-up. After a prescribed time has elapsed, the transistors MN1, MN2, MP1, and MP2 are all turned off under the control of the reset circuit 14, and a bias voltage is applied to the N well 11 and the P well 12 corresponding to their polarity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a CMOS semiconductor device having a structure for applying a bias voltage different from a power supply potential or a ground potential to a substrate.

[0002]

2. Description of the Related Art In a CMOS semiconductor device, in order to reduce power consumption while maintaining high-speed operation, an integrated circuit is designed using a field-effect transistor having a low threshold, and is driven at a low voltage. . In this case, in order to reduce the current when the circuit is not operating at all, that is, so-called standby leakage current, or to compensate for fluctuations in the threshold value even when the circuit is operating, the substrate or well power supply potential or the ground potential is used. Some devices apply different substrate bias voltages. In such an apparatus, the substrate or the wiring for providing the well potential is not connected to the power supply wiring or the ground wiring. For this reason, at the time of turning on the power where the operation of the substrate potential control circuit is insufficient, there is a risk that the power supply voltage becomes higher than the substrate potential and latch-up occurs. As a means for preventing such a situation, a technique of fixing the substrate at an appropriate potential until a certain period of time has elapsed since power-on is used.

[0003]

However, as described later, when a plurality of power supply systems are provided, there is a problem that latch-up occurs immediately after the power is turned on. Therefore,
An object of the present invention is to provide a semiconductor device capable of preventing occurrence of latch-up after power-on.

[0004]

A semiconductor device according to the present invention operates by applying at least one of at least two types of power supply or ground potential to a source.
A semiconductor device in which OSFETs are formed in a plurality of different semiconductor layers, respectively, wherein at least one of the power supplies is first turned on, and all other power supplies are turned on and a predetermined period of time from when the power supply is turned on is stable. A potential control unit including means for fixing the potential of each layer to the highest power supply potential or the ground potential of the at least two types of power supplies according to the conductivity type of the semiconductor layer. The potential control unit includes a substrate bias circuit, and the substrate bias circuit includes a first substrate bias voltage equal to or higher than a power supply potential applied to the MOSFET and a second substrate bias voltage equal to or lower than ground potential. And the potential control unit, after the lapse of the predetermined period, changes each potential of the semiconductor layer to the first substrate bias voltage or the second substrate bias voltage according to the conductivity type of the semiconductor layer. Characterized in that it includes means for fixing to The substrate bias circuit is supplied with the highest power supply potential of the at least two types of power supplies, and in the predetermined period, after the highest power supply potential of the at least two types of power supplies is turned on, all other power supplies are turned on. This includes a period until the power is turned on.

The potential control section includes a reset circuit for measuring the predetermined period. The reset circuit includes an oscillator for outputting a clock, and starts counting the clock after the power is first turned on. A counter that outputs a signal indicating that the count value has reached a maximum value, and a data holding circuit that changes its output when the signal is input from the counter after the predetermined period has elapsed. It is characterized by. The oscillator is provided with an enable terminal, and the output of the data holding circuit is supplied to the enable terminal, so that when the output of the data holding circuit changes, the output of the clock is stopped. I do. The oscillator includes a ring oscillator to which an odd number of inverters with a Schmitt trigger function are connected. The potential control unit includes at least one or more switching elements, and the reset circuit turns on the switching elements during the predetermined period, and turns off the switching elements after the predetermined period has elapsed. It is characterized in that such a control signal is generated. Further, the semiconductor device according to the present invention has at least 2
At least one or more N-type semiconductor layers and at least one or more P-type semiconductor layers formed with at least one MOSFET that operates by applying any one of a power supply and a ground potential to a source; A substrate bias circuit that outputs a first substrate bias voltage equal to or higher than a respective power supply potential applied to the MOSFET applied to the layer, and a second substrate bias voltage equal to or lower than the ground potential applied to the P-type semiconductor layer; A first switching element for applying the highest power supply potential or the first substrate bias potential of the at least two types of power supplies to the N-type semiconductor layer in accordance with one control voltage; A second switching element for applying the ground potential or the second substrate bias potential to the P-type semiconductor layer, Characterized in that it comprises a reset circuit for generating a second control voltage.

[0006] The reset circuit is configured to maintain the highest power supply potential at least for a predetermined period including a period from when one of the power supplies is first turned on to when all other power supplies are turned on and the power supply is stabilized. The first control voltage applied to the N-type semiconductor layer and controlling the first switching element so that the first substrate bias potential is applied after the lapse of the predetermined period; and during the predetermined period. Generates a second control voltage for controlling the second switching element such that the ground potential is applied to the P-type semiconductor layer, and after the lapse of the predetermined period, the second substrate bias potential is applied. It is characterized by the following. The reset circuit includes an oscillator that outputs a clock and a signal that indicates that the count value has reached a maximum value after the clock that starts counting after the first applied potential of the power supply reaches a predetermined potential. And a data holding circuit whose output changes when the signal is input from the counter after the predetermined period has elapsed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. Here, an apparatus having a circuit configuration as shown in FIG. 15 is assumed. The substrate bias circuit 1 is supplied with the power supply voltage VDD2 and generates a substrate bias voltage. A plurality of elements (inverters) IN100 and IN101 present in the internal circuit INCKT1 apply the substrate bias voltage generated by the substrate bias circuit 1 to the substrate. However, the device IN100 and the device IN
101 is different from the power supply to be supplied.
101 is a power supply voltage VDD supplied to the substrate bias circuit 1
2 operates by being supplied with a power supply voltage VDD1 different from the power supply voltage VDD1. The reason for using a separate power supply in this way is that the internal circuit wants to use a power supply voltage that is as low as possible to reduce power consumption, while the substrate bias circuit generates the substrate bias voltage required to sufficiently change the threshold. This is because there is a demand to use as high a power supply voltage as possible. Therefore, here, VDD1 <VDD2. In the current integrated circuit, the operating voltage of the internal circuit is
Normally, the operating voltage of an interface circuit that interfaces with a peripheral device provided outside the chip is higher. For example, if a power supply for the interface circuit is used as a power supply for the substrate bias circuit, it is not necessary to prepare a special power supply for the substrate bias circuit.

Now, in such an integrated circuit, the power supply VDD1
Is turned on before the power supply VDD2, the substrate potential of the internal circuit remains at the floating potential, and latch-up occurs. In the internal circuit INCKT1 shown in FIG. 15, when the power supply VDD2 is turned on after the power supply VDD1, the element I
N101 causes latch-up. In order to prevent such latch-up from occurring, it is necessary to turn on the power supply VDD1 and the power supply VDD2 simultaneously or with a slight delay from the power supply VDD1. However, as shown in FIG. 16, when two power supplies are turned on, a time difference τd usually occurs between the timings of turning on the two power supplies, and the value may be on the order of several tens μsec. In the conventional device, as a method of preventing latch-up, the substrate is appropriately applied from the time when one power supply (VDD2) is turned on until a certain period determined by the CR time constant provided by the capacitance / resistance circuit elapses. A technique of fixing the potential to a certain level has been used. But C
In order to generate a delay time longer than the order of several tens of microseconds by the R time constant, an extremely large capacitance and resistance are required. Therefore, such a CR is formed on the same semiconductor substrate.
Creating a circuit was almost impossible due to chip area.

Therefore, in the embodiment of the present invention described below, the substrate is fixed to an appropriate potential other than the substrate bias voltage (for example, a power supply potential or a ground potential) for a predetermined period in order to prevent latch-up at power-on. In such a case, a structure is provided in which the substrate is fixed at an appropriate potential for a sufficiently long time including a time required from when the first power is turned on to when all other powers are turned on. Hereinafter, the first of the present invention.
The seventh to seventh embodiments will be described with reference to the drawings.
The semiconductor device according to the first embodiment of the present invention has a configuration as shown in FIG. A P-channel MOS transistor PTr is formed in the N-well 11, and an N-channel MOS transistor NTr is formed in the P-well 12. The transistors PTr and NTr form an internal circuit of the device. And
The P-channel transistor PTr and the N-channel transistor NTr are connected to each other.
A MOS logic element is configured. Here, N well 1
1 has N or N formed on the surface of a P or N type semiconductor substrate.
The P-well 12 includes a P-type well formed on the surface of the P-type or N-type semiconductor substrate or a surface portion of the P-type semiconductor substrate.

A node n5 to which the N well 11 is connected;
One output terminal of the substrate bias circuit 13 that outputs the substrate bias voltage Vsub1 is connected by a diode D1. The node n6 to which the P well 12 is connected and the other output terminal of the substrate bias circuit 13 that outputs the substrate bias voltage Vsub2 are connected by a diode D2. Further, the source and drain of the P-channel MOS transistor MP1 are connected between the power supply voltage VDD2 terminal and the node n5, and the gate thereof is connected to the terminal for outputting Vsub1 of the substrate bias circuit 13 via the node n3. I have. The source of the N-channel MOS transistor MN1 is connected between the ground voltage VSS terminal and the node n6.
The drain is connected, and the gate is connected to the terminal for outputting Vsub2 of the substrate bias circuit 13 via the node n4. N is connected between the node n3 and the ground voltage VSS terminal.
The drain and source of the channel type MOS transistor MN2 are connected, and the gate is connected to one output terminal of the reset circuit 14 via the node n1. Node n4
The drain and source of the P-channel MOS transistor MP2 are connected between the power supply voltage VDD2 terminal and the gate, and the gate is connected to the other output terminal of the reset circuit 14 via the node n2.

Here, a power supply voltage VDD2 is supplied to the substrate bias circuit 13, the reset circuit 14, the transistor MP1, and the transistor MP2. However, the power supply voltage VDD1 is supplied to the transistor PTr that forms a part of the internal circuit. Here, it is assumed that the relationship of VDD1 <VDD2 holds. The substrate bias circuit 13 generates a substrate bias voltage to be applied to each substrate of the N well 11 and the P well 12. When the power supply VDD2 is turned on and the power supply voltage VDD2 is stably operated, a substrate bias voltage Vsub1 higher than the power supply voltage VDD2 is generated for the N well 11, and a substrate bias voltage lower than the ground voltage VSS for the P well 12 is generated. A voltage Vsub2 is generated. The reset circuit 14 performs a period from when the power supply VDD2 is turned on to when the remaining power supply VDD1 is turned on, preferably, after the power supplies VDD2 and VDD1 are turned on in order, both potentials and
The power supply voltage VDD2 is output to the output node n1 and the ground voltage VSS is output to the output node n2 until a predetermined period T including a period until the output of the substrate bias circuit 13 becomes stable elapses. After a lapse of a predetermined period T, the output is inverted and the ground voltage VSS and the node n
2 is supplied with the power supply voltage VDD2.

Next, an example of a specific configuration of the reset circuit according to the first embodiment will be described. Here, as described above with reference to FIG.
1. Since VDD2 is used, it is necessary to set restrictions on the timing of turning on the respective power supplies VDD1 and VDD2 so as not to cause latch-up. In order to prevent the latch-up from occurring, if it is necessary to turn on the power supply VDD1 after a lapse of time τd after turning on the power supply VDD2, a T that satisfies the condition of 0 <τd <T is introduced. This T is a constant determined as a rating in the present semiconductor device. However, if it is set too short, it becomes difficult to design the power supply system. Therefore, it may be set to about several tens of μsec or more, for example, T = 100 μsec. Now, the substrate potentials of the N well 11 and the P well 12, that is, the potentials of the nodes n5 and n6 are, as described above,
Substrate bias circuit 13 or transistors MN1, MN
Controlled by P1. When the transistors MN1, MP1M, MN2, and MP2 are off, the substrate bias circuit 13 supplies the power supply voltage V to the N well 1 and the node n3.
Substrate bias voltage Vsub1 higher than DD1 is applied to P well 1
2 and a node n4 are supplied with a substrate bias voltage Vsub2 lower than the ground potential Vss. However, the transistor MN
1, when MP1, MN2, and MP2 are in the ON state, the N well 11 and the node n4 are fixed to the power supply potential VDD2, and the P well 12 and the node n3 are connected regardless of the substrate bias voltage generated by the substrate bias circuit 13. Is the ground potential Vss
Need to be fixed to That is, each transistor size is selected so that control by these transistors has priority over the output of the substrate bias circuit 13.

When the transistors MN2 and MP2 are off and the substrate bias voltage output from the substrate bias circuit 13 is applied to the wells 11 and 12, the diodes D1 and D2 turn off the transistors MP1 and MN1 completely. A necessary potential difference is applied between the gate and the source so as to be in a state. Next, a detailed configuration and operation inside the reset circuit 14 will be described with reference to FIG. The reset circuit 14 provides a signal (potential of the nodes n1 and n2 in FIG. 1) for fixing the wells 11 and 12 to the power supply voltage VDD2 or the ground voltage Vss for a predetermined period T from the time of turning on the power. It is. Here, the feature of the reset circuit 14 according to the present embodiment is that the oscillator 21 and the counter 22 for counting its output clock are used for determining the predetermined period T instead of the CR time constant provided by the resistor and the capacitor. The point is that it is used. As a result, the well 11 is connected to the power supply potential VDD2 and the well 12 is connected to the ground potential V for a long period T that cannot be realized by the CR time constant provided by the on-chip capacitance and resistance.
Can be fixed to ss. When a CR time constant is used as in the related art, it is impossible to determine a time of about 10 μsec due to the chip area. However, in the reset circuit 14 of the present embodiment, by appropriately designing the frequency of the oscillator 21 and the number of stages of the counter 22, a period T on the order of msec can be realized. Here, the resistor R and the capacitor C shown in FIG. 2 are not used for setting the time constant RC, but are used only for generating a signal for initializing the counter 22 and the flip-flop FF. Is done. All the elements included in the reset circuit 14 operate by being supplied with the power supply voltage VDD2.

This reset circuit includes a resistor R, a capacitor C, inverters IN1 to IN4, an oscillator 21, a counter 22,
It has a D-type flip-flop FF. Here, the output 1 is connected to the transistor MN2 via the node n1 shown in FIG.
The output 2 is connected to the gate of the transistor MP2 via the node n2 in FIG. The power supply voltage VDD2 terminal and the ground voltage VSS terminal are divided by a resistor R and a capacitor C. The signal of the node nr1 to be divided is amplified by the two-stage inverters IN1 and IN2 and output from the output node nr2. You. This output signal is input to the reset terminal of the counter circuit 22,
Further, it is input to the reset terminal R of the flip-flop FF. The counter 22 is a cyclic counter. When a pulse is input from the oscillator 21, the counter 22 sequentially counts up from 0, and when it reaches N (N is an integer of 1 or more), returns the count value to 0 and counts up again. To go.
Then, only when the count value reaches N, the power supply voltage VDD
A pulse of logic "1" corresponding to 2 is output. By such a combination of the counter 22 and the oscillator 21, a pulse is generated every N cycles of the output clock of the oscillator 21.

The output 2 voltage is stored in the flip-flop FF. Immediately after the power supply VDD2 is turned on, the potential of the node nr2 is the ground voltage VSS. This potential is input to the reset terminal R to be in a reset state, and logic "0" data corresponding to the ground voltage VSS is held. As a result, the output Q of the flip-flop FF becomes logic “0”, and the output 1 of the reset circuit becomes logic “1”.
Output 2 goes to logic "0". The operation of this embodiment including the reset circuit 14 will be described with reference to FIG. 3 which is a time chart of a power supply potential and an output waveform. First,
At the stage before the power supply VDD2 is turned on, the capacitance charges of all the elements shown in FIG.
Is the ground voltage VSS. The node nr1 rises slightly later than the power supply voltage VDD2. This node nr1
Is amplified by the two-stage inverters IN1 and IN2, the potential of the node nr2 remains at the ground voltage VSS for a while, even when the power supply voltage VDD2 is stabilized, and then rises rapidly to reach the power supply voltage VDD2. . While the potential of the node nr1 is at the ground voltage VSS, both the counter 22 and the flip-flop FF are reset, and the respective internal data becomes logic "0". As a result, the output 1 of the reset circuit 14 has a logic “1” and the output 2 has a logic “0”.

When the potential of the node nr2 rises, the counter 22 starts counting up in synchronization with the clock given from the oscillator 21, and when the count value reaches N, the logic "1" is output from the output node nr4 of the counter 22. Is output. When a pulse is output from the output node nr4, this pulse is input to the clock terminal of the flip-flop FF, and the internal data is rewritten to logic "1". As a result, the output Q of the flip-flop FF becomes logic “1”, the output 1 is inverted to logic “0”, and the output 2 is inverted to logic “1”. The output of the counter 22 is (N + 1)
It becomes "0" again by the pulse, and outputs "1" every time N pulses are counted. However, the input terminal D of the flip-flop FF is fixed to the power supply voltage VDD2. Therefore, regardless of the output voltage of the counter 22, the data stored in the flip-flop FF does not change thereafter. Therefore, the potential of the output 1 is “1” immediately after the power is turned on, becomes “0” after a predetermined time T has elapsed, and does not change as it is. The potential of the output 2 is "0" immediately after the power supply VDD2 is turned on, and becomes "1" after a predetermined time T has elapsed, and does not change as it is. Such outputs 1 and 2 are connected to transistors MN2,
When used as the gate voltage of MP2, these transistors MN2 and MP2 are turned on immediately after the power supply VDD2 is turned on. Accordingly, the transistors MN1 and MP1 are also turned on. When the predetermined time T has elapsed, the transistors MN1,
MN2, MP1, and MP2 are all turned off, and thereafter remain off. Therefore, the potential of the well 11 is equal to the power supply VDD.
Immediately after turning on 2, the power supply potential VDD2 is fixed, the potential of the well 12 is fixed to the ground potential Vss, and after a predetermined time T has elapsed, the substrate bias voltages Vsub1 and Vsub2 generated by the substrate bias circuit 13 are applied.

As described above, immediately after the power supply VDD2 is turned on,
Since the power supply potential VDD2 is not stable, the substrate potential generation circuit 1
3 cannot operate stably. In addition, power supply VDD
2 before power supply VD
When D1 is turned on, latch-up may occur. However, according to the present embodiment, the transistors MP1 and MN1 are reset by the reset circuit 14 until the predetermined period T including the period τd elapses after the power supply VDD2 is turned on.
The N well 11 is fixed to the power supply potential VDD2, and the P well 12 is fixed to the ground potential Vss. As a result, the well potential does not float and latch-up can be prevented. Next, only the configuration of the reset circuit 14 in the first embodiment that is different from that shown in FIG. 2 will be described below as second to sixth embodiments of the present invention. Note that parts other than the reset circuit 14 are the same as those shown in FIG. 1, and a description thereof will be omitted. FIG. 4 shows a configuration of a reset circuit in a semiconductor device according to the second embodiment. In the reset circuit according to this embodiment, an RS flip-flop including two NAND gates NA1 and NA2 is used instead of the D-type flip-flop FF in the reset circuit according to the first embodiment.

The counter 22 is a cyclic counter that counts up to N, as in the first embodiment. That is, it counts up sequentially from 0, and after counting up to N, it returns to 0 and counts up again. When the reset input is "0", the internal data of the counter 22 is "0" and the output is "1".
Do not count up while resetting. When the reset input becomes “1”, counting up starts in synchronization with the clock output from the oscillator 21. The output of the counter 22 outputs "0" only when the internal data is counted up and reaches the maximum value N, and otherwise outputs the power supply potential VDD2. That is, a negative pulse is generated every N cycles of the output clock of the oscillator 21. FIG.
Fig. 2 shows a time chart of the power supply voltage and the output waveform. A point between the power supply potential VDD2 and the ground potential Vss divided by the resistor R and the capacitor C becomes the potential of the node nr1. The signal at the node nr1 is amplified by the two-stage inverters IN1 and IN2 and reaches the potential at the node nr2.
2 and the reset terminal of the RS flip-flop. Immediately after the power supply VDD2 is turned on, the node nr2 is "0" and the node nr4 is "1". Therefore, the output 1 of the RS flip-flop is “1” and the output 2 is “0”.

Thereafter, when the potential of the node nr2 rises, the RS flip-flop maintains the state where the output 1 is "1" and the output 2 is "0". The counter 22 is released from the reset state and starts counting. When the N-th pulse is counted, the output node nr4 of the counter 22 changes from “0” to “1”. Therefore, the output 1 of the RS flip-flop changes to “0” and the output 2 changes to “1”. The output of the counter 22 becomes “1” again by the (N + 1) th pulse, and outputs “0” every time N pulses are counted. However, the state of the RS flip-flop does not change. Therefore, the data stored in the RS flip-flop does not change thereafter regardless of the output voltage of the counter 22. Therefore, the potential of the output 1 is "1" immediately after the power supply VDD2 is turned on, becomes "0" after a predetermined time T has elapsed, and does not change as it is. The potential of the output 2 is “0” immediately after the power supply VDD2 is turned on.
It becomes "1" after the elapse of the predetermined time T, and does not change as it is. When these outputs 1 and 2 are used as the gate voltages of the transistors MN2 and MP2 shown in FIG. 1, the transistors MN2 and MP2 are turned on immediately after the power is turned on.
The transistors MN1 and MP1 are also turned on. When the predetermined time T has elapsed, the transistors MN1, MN2, MP1, M
P2 is all turned off, and thereafter maintains the off state.

As described above, according to the first and second embodiments, the substrate potential immediately after power-on is the power supply potential VDD2,
After a predetermined time T has passed, the substrate bias voltage generated by the substrate bias circuit 13 is fixed via the diodes D1 and D2. At this time, a voltage higher than the N well 11 by the forward voltage of the diode D1 is applied to the gate of the transistor MP1, and a voltage lower than the P well 12 by the forward voltage of the diode D2 is applied to the gate of the transistor MN1. Is done. Thereby, both the transistors MP1 and MN1 maintain the off state. In the first and second embodiments, the oscillator 21 and the counter 22 continue to operate even after the predetermined time T has elapsed. Originally, in an apparatus using a substrate bias circuit, it is assumed that although a power is supplied to the semiconductor device by applying a substrate bias potential to the substrate, a leakage current in an operation stop state is reduced. ing. Therefore, when the oscillator 21 and the counter 22 are operated for a necessary period, the effect of reducing the leak current is further increased. In consideration of such points, the following third to sixth embodiments release the reset state after the predetermined time T has elapsed, and oscillate the oscillator 21 used to determine the predetermined time T. By stopping the operation, useless power consumption is suppressed.

FIG. 6 shows a configuration of a reset circuit according to the third embodiment. The configuration other than the reset circuit is the same as in the first and second embodiments, and the description is omitted.
The third embodiment is characterized in that an enable terminal is provided in an oscillator 21a, and an output 1 is input thereto as an enable signal. The oscillator 21a does not oscillate while the enable signal is "0", and starts oscillating when it becomes "1". The operation in the present embodiment is based on the AND gate A
This is almost the same as the fourth embodiment described below to which N1 is added. Therefore, the operations in both embodiments will be described together using a time chart common to the third and fourth embodiments. The semiconductor device according to the fourth embodiment of the present invention includes a reset circuit having a configuration as shown in FIG. In the present embodiment, the third
In comparison with the embodiment, the enable signal of the oscillator 21a is connected to the node nr2 and the output 1 using the AND gate AN1.
The difference is that it is generated by performing a logical AND operation on. As a result, the oscillator 21a and the counter 22 can simultaneously start operating immediately after the power is turned on. FIG. 8 shows a time chart of the power supply potential and the output waveform in the third embodiment and the fourth embodiment. The potential obtained by dividing the power supply potential VDD2 and the ground potential Vss by the resistance R and the capacitance C is defined as the potential of the node nr1. The potential of the node nr1 is amplified by the two-stage inverters IN1 and IN2, reaches the potential of the node nr2, and is input to the counter 22 and the reset terminal of the flip-flop FF. The counter 22 is provided in the first,
This is a cyclic counter that counts up to N, as in the second embodiment. That is, it counts up sequentially from 0, returns to 0 when it counts up to N, and counts up again. While the reset input is "0", its internal data and output remain reset to "0" and do not count up. When the reset input becomes "1", counting up is started in synchronization with the clock output from the oscillator 21a. The output of the counter 22 outputs “1” only when the internal data is counted up and reaches the maximum value N. Thereby, the oscillator 21a
The counter 22 can generate a pulse every N cycles of the output clock.

When the power supply VDD2 is turned on, the flip-flop FF is reset and "0" is held. That is, immediately after the power is turned on, the output 1 is “1”.
The output 2 is "0". Then, the node nr
When the potential of 2 rises, the reset state is released and the counter 22 starts counting. When the N-th pulse is counted, the potential of the output node nr4 of the counter 22 changes from “0” to “1”. Thereby, the flip-flop FF is triggered and the internal data is rewritten to “1”. As a result, the output 1 changes to “0” and the output 2 changes to “1”. At this time, the enable signal of the oscillator 21a becomes "0", and the oscillator 21a stops oscillating. Accordingly, the counter 22 also stops counting. Therefore, the reset circuit consumes only a small amount of power due to the leak current. Each of the third and fourth embodiments is a modification of the first embodiment. An enable signal is introduced to the oscillator 21a, and after the reset is completed, the operations of the oscillator 21a and the counter 22 are stopped. This has the effect of suppressing wasteful power consumption. Similarly, the second
Also in the second embodiment, by introducing an enable signal to the oscillator, the operation of the oscillator and the counter is stopped, and power consumption can be suppressed. The configuration in this case will be described below as fifth and sixth embodiments of the present invention.

FIG. 9 shows a configuration of a reset circuit according to the fifth embodiment. Portions other than the reset circuit are the same as those in the first to fourth embodiments. The feature of the fifth embodiment is that, like the third and fourth embodiments, an enable terminal is provided in the oscillator 21a, and the output 1 is input thereto as an enable signal. The oscillator 21a does not oscillate while the enable signal is "0", and starts oscillating when it becomes "1". The operation in the present embodiment is almost the same as the sixth embodiment described below in which an AND gate AN1 is added. Therefore, the operation in both embodiments will be described together using a time chart common to the fifth and sixth embodiments. The semiconductor device according to the sixth embodiment includes a reset circuit having a configuration as shown in FIG.
This embodiment is different from the fifth embodiment in that the enable signal of the oscillator 21a is generated by performing a logical AND operation of the node nr2 and the output 1 using the AND gate AN1. As a result, the oscillator 21a and the counter 22 can simultaneously start operating immediately after the power is turned on. FIG. 11 shows a time chart of the power supply potential and the output waveform in the fifth embodiment and the sixth embodiment. The potential obtained by dividing the power supply potential VDD2 and the ground potential Vss by the resistance R and the capacitance C is defined as the potential of the node nr1. The potential of this node nr1 is changed to two-stage inverters IN1 and IN1.
2 to reach the potential of the node nr2,
2 and the reset terminal of the flip-flop FF. The counter 22 is a cyclic counter that counts up to N, as in the first and second embodiments. That is, the count is sequentially increased from 0, and N
After counting up, it returns to 0 and counts up again. While the reset input is "0", its internal data is kept at "0" and the output is kept at "1", so that it does not count up. When the reset input becomes “1”,
The count-up is started in synchronization with the clock output from the oscillator 21a. The output of the counter 22 outputs “0” only when the internal data is counted up and reaches the maximum value N. As a result, the counter 22 can generate a negative pulse every N cycles of the clock output from the oscillator 21a.

Immediately after the power supply VDD2 is turned on, the node nr2 is "0" and the node nr4 is "1". Therefore, the output 1 of the RS flip-flop is “1” and the output 2 is “0”. Thereafter, when the potential of the node nr2 increases,
The RS flip-flop is in the holding state, the output 1 remains at “1” and the output 2 remains at “0” and does not change. Further, the counter 22 is released from the reset state and starts counting. When the N-th pulse is counted, the potential of the output node nr4 of the counter 22 changes from “1” to “0”. As a result, the output 1 of the RS flip-flop changes to “0” and the output 2 changes to “1”. At this time, oscillator 2
The enable signal of 1a becomes "0", and the oscillator 21a stops the oscillating operation. Accordingly, the counter 22 also stops counting. Therefore, the reset circuit consumes only a small amount of power due to the leak current. The above first to first
In all of the sixth embodiments, the configuration of the entire apparatus is as shown in FIG. On the other hand, in a seventh embodiment of the present invention described below, the configuration of the entire apparatus is as shown in FIG. The present embodiment is characterized in that the substrate bias circuit 13 and a circuit for controlling the gate voltages of the transistors MP1 and MN1 are separated.

More specifically, compared to the first to sixth embodiments, the diodes D1 and D2 are removed,
Two output terminals of the substrate bias circuit 13 and a node n5,
n6 is short-circuited, and the charge pump 15
Is provided. The charge pump 15 is supplied with the potential of the output node n2 of the reset circuit 14 as an enable signal, is controlled in operation state, and controls the potentials of the nodes n3 and n4. In this case, the changes in the potentials of the nodes n1 to n4 and the potentials of the N well 11 and the P well 12 are the same as in the first to sixth embodiments. Power supply V
Until a predetermined period T elapses from the input of DD2, the output node n1 of the reset circuit 14 is at the power supply voltage VDD2, the output node n2 is at the ground voltage VSS, and the transistors MN2 and MN
P2 is turned on. During this time, the node n2 is connected to the ground voltage V
Since the potential is SS, the charge pump 15 input with this potential as an enable signal is in a non-operating state, and each output is in a high impedance state. Therefore, the potentials of the nodes n3 and n4 are determined by the transistors MN2 and NP2. Node n3 is at ground voltage VSS and node n4
Becomes the power supply voltage VDD, and the transistors MP1 and MN1
Are turned on together.

While all of the transistors MN2, MP2, MP1, and MN1 are on, the substrate bias circuit 13
Irrespective of the substrate bias voltages Vsub1 and Vsub2 at which the power supply voltage VDD2 is applied.
And the P well 12 and the node n6 are connected to the ground voltage VSS.
Fixed to As described above, while the predetermined period T does not elapse, the transistors MN2, MP2, MP1, and MN1 are all turned on, the N well 11 is fixed at the power supply voltage VDD2, and the P well 12 is fixed at the ground voltage VSS. After the elapse of the predetermined period T, the output node n1 of the reset circuit 14 changes to the ground voltage VSS, the output node n2 changes to the power supply voltage VDD2, and both the transistors MN2 and MP2 are turned off. The enable signal of the power supply voltage VDD2 is input to the charge pump 15, and the charge pump 15 enters an operation state. A node n3, to which one output node of the charge pump 15 is connected, rises to a substrate voltage Vsub1 higher than the power supply voltage VDD2, and a node n4, to which the other output node is connected, has a substrate voltage lower than the ground voltage VSS. The voltage drops below the voltage Vsub 2. in this way,
After the elapse of the predetermined period T, the potentials of the nodes n3 and n4 are determined by the output of the charge pump 15. As a result, the transistors MP1 and MN1 are turned off. As a result, the substrate bias voltage Vsub 1 output from the substrate potential generating circuit 13 is applied to the N well 11, and the substrate bias voltage Vsub 2 is applied to the P well node 1.

As described above, in the present embodiment, the charge pump 15 has the enable terminal, and is connected to the node n2. With this enable signal, the charge pump 15 stops operating when the transistors MN2 and MP2 are on, and operates when the transistors MN2 and MP2 are off. Therefore, as in the configuration shown in FIG. 1, when the transistors MN2 and MP2 are on, the output of the substrate bias circuit 13 and the transistors MN2 and MP2
2 does not collide with the gates of the transistors MN1 and MP1. For this reason, the size of the transistors MN2 and MP2 can be reduced. Next, an example of an oscillator used inside the reset circuit 14 will be described. It is effective that the oscillators 21 and 21a used in the first to sixth embodiments oscillate at a low frequency such as several MHz or less. This is because the counter can be configured with a small number of stages even when the reset period T on the order of msec is realized. However, in the case of oscillating at such a low frequency, as shown in FIG. 13B, the rising of the input waveform to the inverter becomes gentle, so that the input waveform is easily affected by noise. The output may oscillate at a frequency significantly higher than the original frequency. When such an output is input to the counter, each pulse is incorrectly counted as an original clock and counted. Therefore, an erroneous operation of releasing the reset in a time much shorter than the original predetermined time T is caused.

In order to prevent such a phenomenon, it is desirable to form a ring oscillator using inverters IN11 to INm (m is an odd number of 3 or more) having a Schmitt trigger function as shown in FIG. Inverters with a Schmitt trigger function have different thresholds for the rising and falling edges of the input waveform, so the input level when the output changes from low level to high level and when the output drops from high level to low level Has a hysteresis characteristic that the input level is different. By using such an inverter, even when noise is superimposed on the signal waveform of each element, a malfunction in the operation of counting the predetermined period T is prevented from occurring. The above-described embodiments are merely examples, and do not limit the present invention. The circuit configurations shown as the first to seventh embodiments are examples, and various modifications can be made as necessary. For example, the reset circuits in the first to seventh embodiments measure the predetermined period T by counting the number of clocks. However, the present invention is not limited to this, and the reset circuit may be configured to start monitoring the power supply voltage after the power is turned on, and measure that a certain period of time has elapsed after detecting that the level is sufficiently stabilized.

[0029]

According to the semiconductor device of the present invention having the above-described structure, a period from when one of the power supplies is turned on to when all of the other power supplies are turned on until the predetermined period elapses. The substrate may be at a first potential or a second potential depending on its conductivity type.
By fixing the potential of the substrate, the substrate can be prevented from floating and latch-up can be prevented from occurring.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a reset circuit in the semiconductor device according to the first embodiment.

FIG. 3 is a time chart showing a change in potential of each node in the semiconductor device according to the first embodiment;

FIG. 4 is a circuit diagram showing a configuration of a reset circuit in a semiconductor device according to a second embodiment.

FIG. 5 is a time chart showing a change in potential of each node in the semiconductor device according to the second embodiment;

FIG. 6 is a circuit diagram showing a configuration of a reset circuit in a semiconductor device according to a third embodiment.

FIG. 7 is a circuit diagram showing a configuration of a reset circuit in a semiconductor device according to a fourth embodiment.

FIG. 8 is a time chart showing a change in potential of each node in the semiconductor device according to the third and fourth embodiments.

FIG. 9 is a circuit diagram showing a configuration of a reset circuit in a semiconductor device according to a fifth embodiment.

FIG. 10 is a circuit diagram showing a configuration of a reset circuit in a semiconductor device according to a sixth embodiment.

FIG. 11 is a time chart showing a change in potential of each node in the semiconductor device according to the fifth and sixth embodiments.

FIG. 12 is a circuit diagram showing a configuration of a semiconductor device according to a seventh embodiment.

FIG. 13 is an explanatory diagram showing a problem in a case where an inverter without a Schmitt trigger is used as an inverter used in an oscillator in a reset circuit in the semiconductor device according to the first to seventh embodiments;

FIG. 14 is a circuit diagram showing a ring oscillator configured using an inverter with a Schmitt trigger function as an example of an oscillator in a reset circuit in the semiconductor device according to the first to seventh embodiments;

FIG. 15 is a circuit diagram showing an internal circuit which is formed on a substrate to which a substrate bias potential generated by a substrate bias circuit is applied and has an element which is operated by being supplied with a different power supply voltage.

FIG. 16 is an explanatory diagram showing a time difference when first and second power supplies for supplying different power supply voltages are respectively turned on.

[Explanation of symbols]

Reference Signs List 11 N-type substrate 12 P-type substrate 13 Substrate bias circuit 14 Reset circuit 15 Charge pump 21 21a Oscillator 22 Counter circuit Ptr, MP1, MP2 P-channel MOS transistor Ntr, MN1, MN2 N-channel MOS transistor D1, D2 Diode FF D Type flip-flop

Claims (14)

[Claims] At least one of at least one of a power supply and a ground, which operates by applying at least one of a power supply and a ground potential to a source.
A semiconductor device in which one MOSFET is formed in a plurality of different semiconductor layers, at least during a predetermined period from when one of the power supplies is first turned on to when all other power supplies are turned on and stabilized.
A semiconductor comprising a potential control unit including means for fixing the potential of each of the semiconductor layers to the highest power supply potential or the ground potential of the at least two types of power supplies according to the conductivity type of the semiconductor layer. apparatus. 2. The potential control section includes a substrate bias circuit, wherein the substrate bias circuit has a first substrate bias voltage equal to or higher than a power supply potential applied to the MOSFET and a second substrate bias voltage equal to or lower than ground potential. And a substrate bias voltage, wherein the potential control unit, after the lapse of the predetermined period, sets each potential of the semiconductor layer according to the conductivity type of the semiconductor layer,
2. The semiconductor device according to claim 1, further comprising: means for fixing the first substrate bias voltage or the second substrate bias voltage. 3. The substrate bias circuit is supplied with the highest power supply potential of the at least two types of power supplies. During the predetermined period, the highest power supply potential of the at least two types of power supplies is supplied. 3. The semiconductor device according to claim 2, including a period from when the power is turned on until all other power supplies are turned on. 4. The potential control section includes a reset circuit for measuring the predetermined period, the reset circuit comprising: an oscillator for outputting a clock; and a counter for counting the clock after the power supply is first turned on. And a counter that outputs a signal indicating that the count value has reached the maximum value, and a data holding circuit whose output changes when the predetermined period has elapsed and the signal is input from the counter. The semiconductor device according to claim 1, further comprising: 5. An oscillator is provided with an enable terminal, and when the output of the data holding circuit is changed by the output of the data holding circuit being given to the enable terminal, the output of the clock is stopped. The semiconductor device according to claim 4, wherein: 6. The semiconductor device according to claim 4, wherein said oscillator includes a ring oscillator to which an inverter having a Schmitt trigger function is connected in an odd number of stages. 7. The potential control section includes at least one or more switching elements, wherein the reset circuit turns on the switching elements during the predetermined period, and after the predetermined period has elapsed, 5. The semiconductor device according to claim 4, wherein a control signal for turning off the switching element is generated. 8. At least one of at least two kinds of power supplies or ground potentials being applied to a source to operate.
At least one or more N
-Type semiconductor layer, at least one or more P-type semiconductor layers, a first substrate bias voltage equal to or higher than a respective power supply potential applied to the MOSFET applied to the N-type semiconductor layer, and applied to the P-type semiconductor layer. A substrate bias circuit that outputs a second substrate bias voltage that is equal to or lower than the ground potential; and, according to a first control voltage, the highest power supply potential or the first substrate bias potential of the at least two types of power supplies. A first switching element to be applied to the mold semiconductor layer, and the ground potential or the second
Applying a substrate bias potential to the P-type semiconductor layer.
And a reset circuit that generates the first and second control voltages. 9. The reset circuit according to claim 1, wherein said reset circuit includes a power supply circuit for supplying power to said highest power supply potential for at least a predetermined period including a period from when one of said power supplies is first turned on to when all other power supplies are turned on and stabilizes. Is applied to the N-type semiconductor layer, and after the lapse of the predetermined period, the first control voltage for controlling the first switching element so that the first substrate bias potential is applied; and During the period, the ground potential is applied to the P-type semiconductor layer, and after the lapse of the predetermined period, a second control voltage for controlling the second switching element is applied so that the second substrate bias potential is applied. 9. The semiconductor device according to claim 8, wherein the semiconductor device is generated. 10. A reset circuit, comprising: an oscillator for outputting a clock; and a count of the clock is started after a potential applied first of the power supply reaches a predetermined potential, and a count value reaches a maximum value. 10. A counter which outputs a signal notifying that the signal has been output, and a data holding circuit whose output changes when the signal is input from the counter after the predetermined period has elapsed.
13. The semiconductor device according to claim 1. 11. A first output terminal of the substrate bias circuit, the anode being connected to a first output terminal for outputting the first substrate bias voltage, and the cathode being connected to the N-type semiconductor layer.
A cathode is connected to a second output terminal of the substrate bias circuit that outputs the second substrate bias voltage;
A second diode having an anode connected to the type semiconductor layer; and the first switching element has a source and a drain between a highest power supply potential node of the at least two types of power sources and the N-type semiconductor layer. A first P-channel MOS connected to the first output terminal and having a gate connected to the first output terminal
A transistor, and a first N-channel MOS transistor having a drain and a source connected between the gate of the first P-channel MOS transistor and the ground potential node; A source and a drain are connected between the P-type semiconductor layer and the ground potential node, and a second N-type gate is connected to the second output terminal.
A second P-channel MOS transistor having a drain and a source connected between a gate of the second N-channel MOS transistor and the highest power supply potential node of the at least two types of power supplies; 11. The semiconductor device according to claim 10, comprising: 12. A first P-channel MOS transistor having a source and a drain connected between the highest power supply potential node of the at least two types of power supplies and the N-type semiconductor layer. A transistor;
Of a P-channel type MOS transistor having a drain and a source connected between the gate and the ground potential node.
A second N-channel MOS transistor having a source and a drain connected between the P-type semiconductor layer and a ground potential node; The second N
A second P-channel MOS transistor having a drain and a source connected between the gate of the channel-type MOS transistor and the highest power supply potential node of the at least two types of power supplies;
And a charge pump circuit controlled by the reset circuit and connected to respective gates of the first P-channel MOS transistor and the second N-channel MOS transistor. The semiconductor device according to claim 10, wherein: 13. The oscillator is provided with an enable terminal, and when the output of the data holding circuit is changed by the output of the data holding circuit being given to the enable terminal, the output of the clock is stopped. 13. The semiconductor device according to claim 11, wherein: 14. The semiconductor device according to claim 11, wherein said oscillator includes a ring oscillator in which an inverter having a Schmitt trigger function is connected in an odd number of stages.