KR100458473B1 - Power on reset circuit - Google Patents

Abstract

The present invention relates to a power-on reset circuit, comprising: a first power-on reset unit for enabling and outputting a first power-on reset signal when a power supply voltage (VDD) down level is less than or equal to the data retention voltage (V _DR ); A second power-on reset unit for enabling and outputting a second power-on reset signal when the voltage VDD down level is equal to or greater than the data retention voltage V _DR ; and when the first power-on reset signal is low level, A noise filter unit counting a predetermined number of clock signals to filter the second power-on reset signal, and driven when an externally input latch signal is enabled, the first driving voltage being below a predetermined voltage level at which program cell data is read. A third power-on reset unit for outputting a third power-on reset signal using the power-on reset signal and the filtered second power-on reset signal; and when the third power-on reset signal is enabled, the reset timer A reset timer unit for counting the clock signal and outputting an overflow signal when the count signal is counted for a predetermined number of times; and receiving the overflow signal from the reset timer unit using the third power-on reset signal to generate a chip reset signal. It characterized in that it comprises an SR latch portion for outputting.

Description

Power on reset circuit

The present invention relates to a power-on reset circuit, comprising a wave-on reset unit detecting three detection levels, and outputting a high-level power-on reset signal according to each level to reset the chip. The present invention relates to a power-on reset circuit for improving chip stability.

Generally in DRAM, resistors in the chip are floating before power is applied. In this floating state, when power is supplied to the chip, a resistor in the chip is set to an undesired state, causing the chip to malfunction.

In addition, when the power supply falls below a certain voltage, a macro block inside the chip may become unstable and the chip may malfunction.

To solve this problem, a chip has a power on reset circuit. This power-on reset circuit initially outputs a reset signal to prevent the power supply from ramping up or down and destabilizing the chip.

1 is a configuration diagram of a conventional power-on reset circuit.

The conventional power-on reset circuit is composed of a power-on reset unit 1, a reset timer 2, and an SR latch unit 3.

The power on reset unit 1 detects the power supply voltage VDD and outputs a power on reset signal POR. At this time, the power-on reset signal POR is enabled when the power supply voltage VDD rises from the low level to the high level, and is disabled when the power supply voltage VDD rises above the predetermined level.

The reset timer 2 receives the power-on reset signal POR and the reset timer clock signal RTC, and counts the reset timer clock signal RTC when the power-on reset signal POR is enabled. The reset timer 2 outputs an overflow signal when the clock signal RTC is counted for a predetermined number or more.

The SR latch unit 3 outputs a high level chip reset signal RST when the power-on reset signal POR is enabled. At this time, upon receiving an overflow signal from the reset timer 2, the chip reset signal RST is disabled.

FIG. 2 is a detailed circuit diagram of the power on reset unit of FIG. 1.

The power-on reset unit 1 includes a capacitor C1, a buffer B1, NMOS transistors N1, N2, N3, PMOS transistor P1, and inverters I1, I2.

The power-on reset signal (POR) is enabled The timing is determined by the resistance ratio of the resistor R1 and the NMOS transistor N1. At this time, the NMOS transistor N1 and the resistor R1 operate in a linear region, and are sensitive to process changes. .

3 is an operation timing diagram of a conventional power-on reset circuit, and includes a power supply voltage VDD, a power-on reset signal POR, a reset timer clock signal RTC, a data according to a reset timer clock signal, and an overflow. The state of the signal overflow and the chip reset signal RST is shown.

When the power supply voltage VDD rises from a low level to a high level, the power-on reset signal POR is enabled, and when the power supply voltage VDD rises and remains above a predetermined level, the power-on reset signal POR is dis- played. Able to be.

At this time, the chip reset signal RST is enabled at the moment when the power-on reset signal POR is disabled, and the chip reset signal RST is disabled at the moment the overflow signal is enabled. That is, when the reset timer clock signal RTC is counted and the predetermined number or more is exceeded, the overflow signal is enabled, and thus the chip reset signal RST is disabled.

Such conventional power-on reset circuit data Li there is motion during the ramp-up (ramp-up) in the tension voltage (V _DR) below the level, the data retention voltage (V _DR) is powered down or in the vicinity of the level, due to the leakage current It may cause malfunction when ramping up. Here, the data retention voltage V _DR is a voltage at which the CMOS element is operated.

In addition, when the power supply voltage VDD is too low, there is a problem that the chip reset signal RST is likely to malfunction when the program cell data is read.

An object of the present invention for solving the above problems is to provide a plurality of power-on reset unit, to prevent the malfunction caused when the power is down or the lamp up due to leakage current near the data retention voltage (V _DR ) level There is.

Another object of the present invention is to maintain the chip reset state until the program cell data is correctly read at the time of power-up, and to enable the chip reset signal when a stable reading value is obtained.

Still another object of the present invention is to provide a chip stability by minimizing the effects of the process change by providing an element that is not sensitive to process changes in the device of the power-on reset unit.

1 is a configuration diagram of a conventional power-on reset circuit.

FIG. 2 is a detailed circuit diagram of the power on reset unit of FIG. 1. FIG.

3 is an operation timing diagram of a conventional power on reset circuit.

4 is a block diagram of a power-on reset circuit according to an embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the power on reset unit 41 of FIG. 4.

6A and 6B are operation timing diagrams of the power-on reset unit 41.

7A and 7B are operation timing diagrams of the power-on reset unit 42 and the noise filter 44.

8 is a detailed circuit diagram of the power-on reset unit 43 of FIG.

9A and 9B are operational timing diagrams of a power on reset circuit according to an embodiment of the present invention.

According to an aspect of the present invention, a first power-on reset unit for enabling and outputting a first power-on reset signal when a power supply voltage VDD down level is less than or equal to the data retention voltage V _DR , and a power supply voltage ( VDD) a second power-on reset unit for enabling and outputting a second power-on reset signal when the down level is equal to or greater than the data retention voltage V _DR ; and a clock signal when the first power-on reset signal is low level. Is counted more than a predetermined number to filter the second power-on reset signal, and is driven when the latch signal inputted from the outside is enabled, and the first power-on is below a predetermined voltage level at which the program cell data is read. A third power-on reset unit for outputting a third power-on reset signal using the reset signal and the filtered second power-on reset signal, and a reset timer clock signal when the third power-on reset signal is enabled. A reset timer unit for counting and outputting an overflow signal when a predetermined number is counted, and an SR for receiving an overflow signal from the reset timer unit and outputting a chip reset signal using the third power-on reset signal; And a latch unit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a configuration diagram of a power-on reset circuit according to an embodiment of the present invention.

The power-on reset circuit is composed of a power-on reset signal generator 40, a reset timer 45, and an SR latch unit 46.

The power on reset signal generator 40 includes a power on reset parts 41 to 43 and a noise filter 44.

Power-on reset unit 41 is a power supply voltage (VDD) and a data retention voltage (V _DR) comparing the level if the power supply voltage (VDD) is below the data retention voltage (V _DR) level power-on reset with a high level Output the signal POR1. At this time, if the power-on reset signal POR1 is at a high level, the power-on reset signal 42 and the noise filter 44 are reset to clear the power-on reset signal POR2, and the power-on reset signal POR1 is low. At the level, the power-on reset unit 42 and the noise filter 44 are driven.

Power-on reset unit 42 compares a power supply voltage (VDD) and a data retention voltage (V _DR) level, the power supply voltage (VDD), the data retention voltage (V _DR) level greater than a high level state the power-on The reset signal POR2 is output.

At this time, the power-on reset unit 42 receives the power-on reset signal POR1 and the power-on reset enable signal POR2_EN so that the power-on reset signal POR1 is at a low level and the power-on reset enable signal POR2_EN is received. ) Is driven when high level.

The noise filter 44 receives and filters the power on reset signal POR2 having a high level when the power on reset signal POR1 is at a low level, and outputs the filtered power on reset signal NF_POR2. At this time, the filtering of the noise filter 44 is controlled by the noise filter clock signal CLK and the delay control signal DCON.

That is, the noise filter 44 counts the noise filter clock signal CLK, counts more than the clock number determined by the delay control signal DCON, and filters the power-on reset signal POR2 when it overflows, and delay control signal. After the delay time determined by (DCON), the filtered power-on reset signal NF_POR2 is output. Therefore, when the power on reset signal POR2 is at the low level, the filtered power on reset signal NF_POR2 is also output at the low level.

The power on reset unit 43 is driven by receiving the latch signal POR3_Latch of the high level, and the power on reset signal POR1 and the filtered power on reset signal NF_POR2 output from the power on reset unit 41 are driven. Outputs a power-on reset signal (POR3).

At this time, the power-on reset unit 43 receives the signal d output from the external program memory 81 and is below a voltage level at which the program cell data is correctly read. Outputs a power-on reset signal (POR3).

The reset timer 45 counts the reset timer clock signal RTC upon receiving the high level power-on reset signal POR3, and outputs an overflow signal when the reset timer clock counts for a predetermined number or more.

The SR latch unit 46 receives the power-on reset signal POR3 and outputs the chip reset signal RST. At this time, the logic state of the chip reset signal RST is determined according to whether the reset timer 45 overflows. That is, when the chip reset signal RST is enabled and output and receives an overflow signal from the reset timer 45, the chip reset signal RST is disabled and output.

In this way, the power-on-reset circuit outputs the supply voltage (VDD) is smaller than the data retention voltage (V _DR) level and outputs a high-level state power-on-reset signal (POR1) a reset signal (RST), the power supply voltage (VDD), the data retention voltage (V _DR) level is greater than the high level state of the power, and on the output a reset signal (POR2) outputs the reset signal (RST) to a program memory 81 from the program cell data reading correctly The reset signal RST is output up to the voltage level.

Thus, by outputting the power supply voltage (VDD) a data retention voltage (V _DR) a reset signal (RST) in the above level, to the chip is operating in a stable manner.

FIG. 5 is a detailed circuit diagram of the power on reset unit 41 of FIG. 4.

The power-on reset unit 41 includes a capacitor C2, a buffer B2, a PMOS transistor P2, an NMOS transistor N4 and N5, an AND gate AND, an inverter I3, and a monostable multivibrator. (monostable multivibrator).

The capacitor C2 is connected between the power supply voltage VDD and the node a to charge and discharge. The NMOS transistor N4 is connected between the node a and the ground voltage VSS and controlled by the value of the node C.

The output of the node a becomes the input of the monostable multivibrator 50 and is output as the power-on reset signal POR2 through the buffer B2.

The monostable multivibrator 50 determines the potential at the time when the power-on reset signal POR1 is enabled, receives the output of the node a, and outputs it to the node b.

The AND gate AND performs the logic operation by receiving the power-on reset signal POR2 and the output of the monostable multivibrator 50. The output of the AND gate AND is inverted through the inverter I3 via the NMOS transistor N5 to control the PMOS transistor P2. At this time, the NMOS transistor N5 functions as a diode.

That is, the potential of the node b is transferred to the node c via the NMOS transistor N5. Therefore, when the potential of the node b is high level, the potential of the node c also becomes high level.

When ramped up according to the applied power voltage VDD, the node a is discharged through the NMOS transistor N5 and outputs a power-on reset signal POR1 through the buffer B2.

As described above, the monostable multivibrator is provided in place of the process change-sensitive resistor and the NMOS transistor device to enable operation in the saturation region to minimize the influence of the process change.

6A and 6B are operation timing diagrams of the power on reset unit 41.

FIG. 6A is an operation timing diagram when the ramp-up rate of the power supply voltage VDD is fast, and the power supply voltage VDD and the output and power of the nodes a, b, and c of FIG. The operation state of the on reset signal POR1 is shown.

The signal of the node a is ramped up according to the power supply voltage VDD, and is an enable signal of the monostable multivibrator 50. The signal of the node a is enabled and is specified as a t2 part after the t1 part. At the potential Vth, the monostable multivibrator 50 is activated so that the signal of the node b becomes high level.

That is, in the timing diagram of the node a of FIG. 6A, the t1 portion is a stable state in which the signal of the node b, which is the output of the monostable multivibrator 50, is at a low level, and the t2 portion is a monostable multivibrator 50. The signal of the node b, which is the output of N, is unstable with a high level state. As a result, the node c is also at a high level.

FIG. 6B is an operation timing diagram when the ramp-up rate of the power supply voltage VDD is slow. The power supply voltage VDD and the output and power of the nodes a, b, and c of FIG. The operation state of the on reset signal POR1 is shown.

7A and 7B are operation timing diagrams of the power on reset unit 42 and the noise filter 44.

FIG. 7A illustrates the power supply voltage VDD and the power on reset signal POR1, when the power on reset unit 42 and the noise filter 44 are enabled when the power on reset enable signal POR2_EN is at a high level. POR2), an operation timing diagram of the filtered power-on reset signal NF_POR2, the noise filter clock signal CLK, and the delay control signal DCON.

The power-on reset enable signal POR2_EN is a signal that reads program memory cell data. The power-on reset enable signal POR2_EN is at a high level when the read value is incorrect, or at a low level when the read value is correct.

As shown in FIG. 7A, when the power supply voltage VDD is enabled, the power on reset signal POR1 is enabled, and accordingly, the power on reset signal POR2 is enabled. Thereafter, when the number of clocks of the noise filter clock signal CLK reaches a predetermined number or more, the power-on reset signal POR2 is filtered to enable the filtered power-on reset signal NF_POR2.

FIG. 7B illustrates a case where the power on reset unit 42 and the noise filter 44 are disabled when the power on reset enable signal POR2_EN is at a low level.

FIG. 8 is a detailed circuit diagram of the power on reset unit 43 of FIG. 4.

The power-on reset unit 43 is composed of a D flip-flop 82 that receives data read from the program memory 81, an inverter I4, and an oragate OR, and the voltage at which the program cell data is read correctly. The power-on reset signal POR3 is output below the level. At this time, the power-on reset signal POR3 becomes high level until the correct data is read from the program memory 81.

The OR gate receives the power on reset signal POR1 and the filtered power on reset signal NF_POR2 and performs a logical operation, and outputs the result to the D flip-flop 82.

The D flip-flop 82 receives the signal of the node d, which is the output of the program memory 81, through the data terminal D, receives the output of the oragate OR, through the reset terminal rst, and receives a latch signal. (POR3_Latch) is received at the clock terminal ck, and the power-on reset signal POR3 is output through the Q terminal Q.

9A and 9B are operation timing diagrams of the power-on reset circuit when the ramp-up rate is slow, and the power supply voltage when the power-on reset enable signal POR2_EN is enabled and the noise filter amount is "0". A timing diagram of the VDD, the power-on reset signals POR1, POR2, and POR3, the latch signal POR3_Latch, the node d, the chip reset signal RST, and the reset timer clock RTC are shown.

9A illustrates a case where the power supply voltage VDD level is greater than the data retention voltage V _DR level, and FIG. 9B illustrates a case where the power supply voltage VDD level is lower than the data retention voltage V _DR level.

When the power supply voltage VDD level rises, the power-on reset signals POR1, POR2, and POR3 are enabled. When the power supply voltage VDD level rises above a certain level, the power-on reset signal POR1, POR2, and POR3 are disabled.

When the signal of the node d becomes high level, the power supply voltage VDD is changed according to the characteristics of the cell and the sense amplifier. This characteristic makes the power-on reset signal POR3 for setting the chip reset variable so that efficient chip operation is possible.

The latch signal POR3_Latch is set by the power-on reset signal POR1 and the filtered power-on reset signal NF_POR2 and is enabled and disabled according to the power-on reset signal POR3. The signal and the power-on reset enable signal POR2_EN are stably latched.

The chip reset signal RST is enabled according to the power-on reset signal POR3, and then the power-on reset signal POR3 is enabled so that the reset timer is operated to be disabled at a certain point before overflow occurs.

In FIG. 9A, the chip reset signal RST is output at a portion where the power supply voltage VDD down level is greater than the data retention voltage V _DR . In FIG. 9B, the power supply voltage VDD down level is the data retention voltage V. FIG. It can be seen that the chip reset signal RST is disabled in the portion of _DR or less.

In this manner, when the power supply voltage VDD down level is equal to or greater than the data retention voltage V _DR , the chip reset signal RST is output. When the power supply voltage VDD is lower than the data retention voltage V _DR , the chip reset signal RST is displayed. The chip operation is stabilized by enabling the chip reset to be maintained at a power supply voltage level at which the reading of the program cell data does not work properly.

As described above, the power-on reset circuit according to the present invention has an effect of more stable chip operation by outputting the chip reset signal above the data retention voltage (V _DR ) level.

In addition, there is an effect of minimizing the effects of process changes when enabling the power-on reset signal below the data retention voltage (V _DR ) level.

In addition, when the program memory is used, the chip reset is maintained at the power supply voltage level at which the reading of the program cell data does not operate properly.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

A first power-on reset unit for enabling and outputting a first power-on reset signal when the power supply voltage VDD down level is less than or equal to the data retention voltage V _DR ; A second power on reset unit configured to enable and output a second power on reset signal when the power supply voltage VDD down level is equal to or greater than the data retention voltage V _DR ; A noise filter configured to filter the second power on reset signal by counting a predetermined number of clock signals when the first power on reset signal is at a low level; When the externally input latch signal is enabled, the third power-on reset signal is driven using the first power-on reset signal and the filtered second power-on reset signal below a predetermined voltage level at which program cell data is read. A third power-on reset unit configured to output the power; A reset timer unit counting a reset timer clock signal when the third power-on reset signal is enabled and outputting an overflow signal when the third power-on reset signal is counted; And And an SR latch unit which receives an overflow signal from the reset timer unit and outputs a chip reset signal by using the third power on reset signal. The method of claim 1, wherein the first power-on reset unit Charging / discharging means for charging and discharging the power supply voltage; A monostable multivibrator that receives an output of the charging / discharging means to determine a potential at which the first power-on reset signal is enabled; First inverting means for inverting and outputting the output of the charging / discharging means; Logic operation means for performing a logic operation on the output of the monostable multivibrator and the output of the first inversion means; And And a switching means controlled by an output of said logic operation means, said power-on reset circuit comprising a feedback structure. The method of claim 1, wherein the third power on reset unit Logic operation means for receiving the first power on reset signal and the filtered second power on reset signal and performing logical operation; And And a D flip-flop which receives the output of said logic operation means, reads data from a program memory, and outputs a third power-on reset signal in accordance with the clock of the latch signal.