JPS6286729U - - Google Patents
Info
- Publication number
- JPS6286729U JPS6286729U JP17810685U JP17810685U JPS6286729U JP S6286729 U JPS6286729 U JP S6286729U JP 17810685 U JP17810685 U JP 17810685U JP 17810685 U JP17810685 U JP 17810685U JP S6286729 U JPS6286729 U JP S6286729U
- Authority
- JP
- Japan
- Prior art keywords
- signals
- gate
- mos fet
- latch circuit
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Description
第１図は本考案に係る半導体ラツチ回路の一実
施例の構成図、第２図は第１図のトランスミツシ
ヨン・インバータの具体的構成図、第３図は第１
図のトランスミツシヨン・インバータの入出力関
係を示した図、第４図及び第５図は第１図のトラ
ンスミツシヨン・インバータのチツプ上における
構成を示したステイツク線図、第６図は第２図の
トランスミツシヨン・インバータの他の表示法を
示した図、第７図は半導体ラツチ回路の従来例の
構成図、第８図は第７図のクロツクド・インバー
タの具体的構成図、第９図は第７図のクロツクド
・インバータの入出力関係を示した図である。
ＴＩＮＶ１，ＴＩＮＶ２……トランスミツシヨ
ン・インバータ、ＣＩ３，ＣＩ４……クロツクド
・インバータ、Ｉ３′，Ｉ４……ＣＭＯＳインバ
ータ。
FIG. 1 is a block diagram of an embodiment of the semiconductor latch circuit according to the present invention, FIG. 2 is a specific block diagram of the transmission inverter of FIG. 1, and FIG.
Figures 4 and 5 are stake diagrams showing the configuration of the transmission inverter in Figure 1 on a chip, and Figure 6 is a diagram showing the input/output relationship of the transmission inverter in Figure 1. 2 is a diagram showing another method of displaying the transmission inverter, FIG. 7 is a configuration diagram of a conventional example of a semiconductor latch circuit, and FIG. 8 is a specific configuration diagram of the clocked inverter shown in FIG. FIG. 9 is a diagram showing the input/output relationship of the clocked inverter of FIG. 7. TINV1, TINV2...Transmission inverter, CI3 , CI4 ...Clocked inverter, I3 ', I4 ...CMOS inverter.
Claims (1)
・ゲートを用いてデータをラツチする半導体ラツ
チ回路において、 Ｐチヤネル形ＭＯＳ ＦＥＴのドレイン又はソ
ースとＮチヤネル形ＭＯＳ ＦＥＴのドレイン又
はソースをそれぞれ接続し、一方の接続点にＣＭ
ＯＳインバータの出力端を接続し、前記一方及び
他方の接続点から取り出した信号をそれぞれ出力
信号、前記ＣＭＯＳインバータに与える信号を入
力信号とするとともに、前記Ｐチヤネル形及びＮ
チヤネル形ＭＯＳ ＦＥＴのゲートに与える信号
でオン・オフする回路を１個のゲートとして構成
したトランスミツシヨン・インバータを有するこ
とを特徴とする半導体ラツチ回路。[Claim for Utility Model Registration] In a semiconductor latch circuit that latches data using a transmission gate composed of MOS FETs, the drain or source of a P-channel MOS FET and the drain or source of an N-channel MOS FET are Connect each and connect CM to one connection point.
The output terminals of the OS inverters are connected, and the signals taken out from the one and other connection points are used as output signals, and the signals given to the CMOS inverter are used as input signals, and the P channel type and N
A semiconductor latch circuit characterized by having a transmission inverter configured as one gate, which is turned on and off by a signal applied to the gate of a channel type MOS FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17810685U JPS6286729U (en) | 1985-11-19 | 1985-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17810685U JPS6286729U (en) | 1985-11-19 | 1985-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6286729U true JPS6286729U (en) | 1987-06-03 |
Family
ID=31119933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17810685U Pending JPS6286729U (en) | 1985-11-19 | 1985-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6286729U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192059A (en) * | 1990-11-27 | 1992-07-10 | Mitsubishi Electric Corp | Control method for data processing circuit and data latch circuit used to this processing circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115921A (en) * | 1981-12-29 | 1983-07-09 | Nec Corp | Latch circuit |
| JPS6025318A (en) * | 1983-07-22 | 1985-02-08 | Hitachi Ltd | Pseudo static flip-flop |
| JPS6075121A (en) * | 1983-09-30 | 1985-04-27 | Nec Corp | Flip-flop |
-
1985
- 1985-11-19 JP JP17810685U patent/JPS6286729U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115921A (en) * | 1981-12-29 | 1983-07-09 | Nec Corp | Latch circuit |
| JPS6025318A (en) * | 1983-07-22 | 1985-02-08 | Hitachi Ltd | Pseudo static flip-flop |
| JPS6075121A (en) * | 1983-09-30 | 1985-04-27 | Nec Corp | Flip-flop |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192059A (en) * | 1990-11-27 | 1992-07-10 | Mitsubishi Electric Corp | Control method for data processing circuit and data latch circuit used to this processing circuit |
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