JPS6312935U - - Google Patents
Info
- Publication number
- JPS6312935U JPS6312935U JP7485086U JP7485086U JPS6312935U JP S6312935 U JPS6312935 U JP S6312935U JP 7485086 U JP7485086 U JP 7485086U JP 7485086 U JP7485086 U JP 7485086U JP S6312935 U JPS6312935 U JP S6312935U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- channel
- insulated gate
- gate field
- effect transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 6
- 230000005540 biological transmission Effects 0.000 claims 2
- 230000000295 complement effect Effects 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図に示された実施例の動作を示す波形図、
第３図は従来例を示す回路図である。
７……入力端子、８……出力端子、９……Ｐ―
ＭＯＳＦＥＴ、１０……Ｎ―ＭＯＳＦＥＴ、１１
，１２……インバータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the embodiment shown in FIG. 1,
FIG. 3 is a circuit diagram showing a conventional example. 7...Input terminal, 8...Output terminal, 9...P-
MOSFET, 10...N-MOSFET, 11
, 12...Inverter.
Claims (1)
ヤンネル及びＮチヤンネルの絶縁ゲート電界効果
トランジスタと、該絶縁ゲート電界効果トランジ
スタの各々のゲートに相補信号を印加する制御回
路とを備えた伝送ゲート回路に於いて、前記Ｐチ
ヤンネル及びＮチヤンネルの絶縁ゲート電界効果
トランジスタは、ｎ組の並列接続されたＰチヤン
ネル及びＮチヤンネルの絶縁ゲート電界効果トラ
ンジスタから成り、前記制御回路は、前記ｎ組の
各々の絶縁ゲート電界効果トランジスタのゲート
に順次遅延された相補信号を印加する遅延回路を
備えたことを特徴とする伝送ゲート回路。 A transmission gate comprising P-channel and N-channel insulated gate field effect transistors having first and second electrodes commonly connected, respectively, and a control circuit that applies a complementary signal to each gate of the insulated gate field effect transistor. In the circuit, the P-channel and N-channel insulated gate field effect transistors are comprised of n sets of P-channel and N-channel insulated gate field effect transistors connected in parallel, and the control circuit is configured to control each of the n sets of insulated gate field effect transistors. A transmission gate circuit comprising a delay circuit that applies sequentially delayed complementary signals to the gates of insulated gate field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7485086U JPS6312935U (en) | 1986-05-19 | 1986-05-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7485086U JPS6312935U (en) | 1986-05-19 | 1986-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6312935U true JPS6312935U (en) | 1988-01-28 |
Family
ID=30920450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7485086U Pending JPS6312935U (en) | 1986-05-19 | 1986-05-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6312935U (en) |
-
1986
- 1986-05-19 JP JP7485086U patent/JPS6312935U/ja active Pending
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