JPS62203529U - - Google Patents
Info
- Publication number
- JPS62203529U JPS62203529U JP9265786U JP9265786U JPS62203529U JP S62203529 U JPS62203529 U JP S62203529U JP 9265786 U JP9265786 U JP 9265786U JP 9265786 U JP9265786 U JP 9265786U JP S62203529 U JPS62203529 U JP S62203529U
- Authority
- JP
- Japan
- Prior art keywords
- channel transistor
- output
- inverter
- gate
- transistor constituting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の一実施例を示す回路図、第２
図は従来の出力回路を示す回路図、第３図は本考
案を説明するための波形図である。
１，３……入力端子、２，５……出力端子、１
１，１２，１３，１４，１５……Ｐチヤンネルト
ランジスタ、２１，２２，２３，２４，２５……
Ｎチヤンネルトランジスタ、３１……第２のイン
バータの出力波形、３２……第１のインバータの
出力波形、４１，４２……抵抗。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing a conventional output circuit, and FIG. 3 is a waveform diagram for explaining the present invention. 1, 3...Input terminal, 2,5...Output terminal, 1
1, 12, 13, 14, 15...P channel transistor, 21, 22, 23, 24, 25...
N-channel transistor, 31... Output waveform of second inverter, 32... Output waveform of first inverter, 41, 42... Resistor.
Claims (1)
ルトランジスタ及び第１のＰチヤンネルトランジ
スタのゲートと第２のインバータを構成する第２
のＮチヤンネルトランジスタ及び第２のＰチヤン
ネルトランジスタのゲートとが共通接続され、前
記第１のインバータの出力が出力インバータを構
成する第３のＰチヤンネルトランジスタのゲート
に接続され、前記第２のインバータの出力が出力
インバータを構成する第３のＮチヤンネルトラン
ジスタのゲートに接続され、前記第３のＮチヤン
ネルトランジスタ及び第３のＰチヤンネルトラン
ジスタの各々のドレインと出力端子との間に抵抗
体を接続したＣＭＯＳ型出力回路を有することを
特徴とする半導体集積回路装置。 The gates of the first N-channel transistor and the first P-channel transistor constituting the first inverter and the second gate transistor constituting the second inverter.
The gates of the N-channel transistor and the second P-channel transistor are commonly connected, the output of the first inverter is connected to the gate of the third P-channel transistor constituting the output inverter, and the output of the first inverter is connected to the gate of the third P-channel transistor constituting the output inverter. A CMOS whose output is connected to the gate of a third N-channel transistor constituting an output inverter, and a resistor is connected between the drain and the output terminal of each of the third N-channel transistor and the third P-channel transistor. A semiconductor integrated circuit device characterized by having a type output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9265786U JPS62203529U (en) | 1986-06-17 | 1986-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9265786U JPS62203529U (en) | 1986-06-17 | 1986-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203529U true JPS62203529U (en) | 1987-12-25 |
Family
ID=30954555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9265786U Pending JPS62203529U (en) | 1986-06-17 | 1986-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203529U (en) |
-
1986
- 1986-06-17 JP JP9265786U patent/JPS62203529U/ja active Pending