JPH0486340U - - Google Patents
Info
- Publication number
- JPH0486340U JPH0486340U JP12897390U JP12897390U JPH0486340U JP H0486340 U JPH0486340 U JP H0486340U JP 12897390 U JP12897390 U JP 12897390U JP 12897390 U JP12897390 U JP 12897390U JP H0486340 U JPH0486340 U JP H0486340U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- source
- grounded
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
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- Logic Circuits (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
、第３図は従来の論理回路例を示す。
１，２……電流源、ＴＲ１〜ＴＲ５……Ｎ−Ｆ
ＥＴ、Ａ，Ｂ……入力端子、Ｃ……出力端子。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 show examples of conventional logic circuits. 1, 2...Current source, TR1 to TR5 ...N-F
ET, A, B...Input terminal, C...Output terminal.
Claims (1)
を共に接地し、ゲート電極の各々を入力端子Ａ又
はＢに接続し、ドレイン電極を共通にして電流源
１に接続すると共に、ソース電極を接地しドレイ
ン電極を電流源２に接続したＮＦＥＴインバータ
ＴＲ５のゲート電極へ、前記ＴＲ１，ＴＲ２の共
通のドレイン電極を接続してＯＲ回路を構成し、
また該ＯＲ回路に並列に、直接接続した２つのＮ
ＦＥＴ ＴＲ３，ＴＲ４を設け、ＴＲ３のソース
電極を接地し各ゲート電極をそれぞれ入力端子Ａ
又はＢに接続してＮＡＮＤ回路を構成し、その出
力となるＴＲ４のドレイン電極を前記ＴＲ５のド
レイン電極に接続して出力端子Ｃとする排他的Ｏ
Ｒ回路。 The source electrodes of the two NFETs TR 1 and TR 2 are both grounded, each of the gate electrodes is connected to the input terminal A or B, the drain electrodes are connected to the current source 1 in common, and the source electrodes are grounded and the drains are connected to the current source 1. A common drain electrode of the TR 1 and TR 2 is connected to the gate electrode of the NFET inverter TR 5 whose electrode is connected to the current source 2 to form an OR circuit,
In addition, two N
FETs TR 3 and TR 4 are provided, the source electrode of TR 3 is grounded, and each gate electrode is connected to input terminal A.
Or, an exclusive O is connected to B to form a NAND circuit, and the drain electrode of TR 4 , which is the output thereof, is connected to the drain electrode of TR 5 to form the output terminal C.
R circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12897390U JPH0486340U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12897390U JPH0486340U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486340U true JPH0486340U (en) | 1992-07-27 |
Family
ID=31876406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12897390U Pending JPH0486340U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486340U (en) |
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1990
- 1990-11-30 JP JP12897390U patent/JPH0486340U/ja active Pending