JPH033849U

JPH033849U -

Info

Publication number: JPH033849U
Application number: JP6328389U
Authority: JP
Priority date: 1989-05-31
Filing date: 1989-05-31
Publication date: 1991-01-16

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の回路図、第２図ａ
乃至ｅは第１図の回路の各部の信号波形図、第３
図は本考案の第２実施例の回路図、第４図は従来
のバツフア回路の回路図、第５図はその等価回路
図、第６図ａ乃至ｃは第４図の回路の各部の信号
波形図である。１……入力端子、２，４……ＰチヤネルＭＯＳ
トランジスタ、３，５……ＮチヤネルＭＯＳトラ
ンジスタ、６……２入力論理和ゲート、７……２
入力論理積ゲート、８……第１の電源（ＶＤＤ）
、９……第２の電源（ＧＮＤ）、１０……出力端
子、１１……時間差回路、１２，１３……遅延素
子、ＩＮＶ_１……第１のＣＭＯＳインバータ、Ｉ
ＮＶ_２……第２のＣＭＯＳインバータ。 Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2a
3 to 3 are signal waveform diagrams of each part of the circuit in Figure 1.
The figure is a circuit diagram of the second embodiment of the present invention, Figure 4 is a circuit diagram of a conventional buffer circuit, Figure 5 is its equivalent circuit diagram, and Figures 6 a to c are signals of various parts of the circuit in Figure 4. FIG. 1...Input terminal, 2, 4...P channel MOS
Transistor, 3, 5...N channel MOS transistor, 6...2 input OR gate, 7...2
Input AND gate, 8...first power supply (VDD)
, 9... Second power supply (GND), 10... Output terminal, 11... Time difference circuit, 12, 13... Delay element, INV ₁ ... First CMOS inverter, I
_NV2 ...Second CMOS inverter.

Claims

[Claims for Utility Model Registration] 1. A first CMOS inverter composed of a P-channel MOS transistor and an N-channel MOS transistor, and a P-channel MOS transistor and an N-channel MOS transistor connected in cascade to the first CMOS inverter.
A second C composed of channel MOS transistors
MOS inverter and these first and second CMs
The second CMOS is inserted between the OS inverters.
A semiconductor integrated circuit comprising: a time difference circuit that provides a time difference between gate input signals of each MOS transistor of an inverter. 2. The time difference circuit consists of a 2-input OR gate and a 2-input AND gate, one input of each gate is connected to each other and connected to the output of the first CMOS inverter, and the output of each gate is connected to the output of the first CMOS inverter. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is individually connected to the gates of each transistor of two CMOS inverters, and the other input of each gate is connected to the output of the other gate. 3. The semiconductor integrated circuit according to claim 2, wherein a delay element is inserted between the output of each gate and the other input of the other gate.