JPH0247832U - - Google Patents
Info
- Publication number
- JPH0247832U JPH0247832U JP12642188U JP12642188U JPH0247832U JP H0247832 U JPH0247832 U JP H0247832U JP 12642188 U JP12642188 U JP 12642188U JP 12642188 U JP12642188 U JP 12642188U JP H0247832 U JPH0247832 U JP H0247832U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- power supply
- supply terminal
- control transistor
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Description
第１図及び第２図はそれぞれ本考案の一実施例
の回路図及びこの実施例を説明するための各部信
号の波形図、第３図は従来の半導体遅延回路の一
例を示す回路図である。
１……制御クロツク発生回路、２Ａ〜２Ｆ……
インバータ、３Ａ〜３Ｆ……制御用トランジスタ
、４……切換回路、Ｇ１〜Ｇ６……ゲート回路、
Ｉ１〜Ｉ４……インバータ、Ｑ１〜Ｑ１２……ト
ランジスタ。
1 and 2 are a circuit diagram of an embodiment of the present invention and waveform diagrams of various signals for explaining this embodiment, respectively, and FIG. 3 is a circuit diagram showing an example of a conventional semiconductor delay circuit. . 1... Control clock generation circuit, 2A to 2F...
Inverter, 3A to 3F...Control transistor, 4...Switching circuit, G1 to G6 ...Gate circuit,
I1 to I4 ...Inverter, Q1 to Q12 ...Transistor.
Claims (1)
換えて出力する制御クロツク発生回路と、ソース
を第１の電源供給端子と接続しゲートに前記制御
クロツク信号を入力する一導電型の第１の制御用
トランジスタと、ゲートを共に信号入力端子と接
続し前記第１の制御用トランジスタのドレインと
第２の電源供給端子との間に直列接続された一導
電型及び逆導電型のトランジスタを備えたＣＭＯ
Ｓ型の第１のインバータと、ソースを前記第２の
電源供給端子と接続しゲートに前記制御クロツク
信号を入力する逆導電型の第２の制御用トランジ
スタと、ゲートを共に前記第１のインバータの出
力端と接続し前記第１の電源供給端子と前記第２
の制御用トランジスタのドレインとの間に直列接
続された一導電型及び逆導電型のトランジスタを
備えたＣＭＯＳ型の第２のインバータとを有する
ことを特徴とする半導体遅延回路。 a control clock generation circuit that switches and outputs the frequency of a control clock signal in response to a switching signal; a first control transistor of one conductivity type whose source is connected to a first power supply terminal and whose gate inputs the control clock signal; , a CMO comprising transistors of one conductivity type and opposite conductivity type whose gates are both connected to a signal input terminal and which are connected in series between the drain of the first control transistor and a second power supply terminal.
an S-type first inverter, a second control transistor of an opposite conductivity type whose source is connected to the second power supply terminal and whose gate inputs the control clock signal, and whose gate is connected to the first inverter; is connected to the output terminal of the first power supply terminal and the second power supply terminal.
a CMOS type second inverter including transistors of one conductivity type and an opposite conductivity type connected in series between the drain of the control transistor of the semiconductor delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12642188U JPH0247832U (en) | 1988-09-27 | 1988-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12642188U JPH0247832U (en) | 1988-09-27 | 1988-09-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247832U true JPH0247832U (en) | 1990-04-03 |
Family
ID=31377930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12642188U Pending JPH0247832U (en) | 1988-09-27 | 1988-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247832U (en) |
-
1988
- 1988-09-27 JP JP12642188U patent/JPH0247832U/ja active Pending