JPS6178437U - - Google Patents
Info
- Publication number
- JPS6178437U JPS6178437U JP16154584U JP16154584U JPS6178437U JP S6178437 U JPS6178437 U JP S6178437U JP 16154584 U JP16154584 U JP 16154584U JP 16154584 U JP16154584 U JP 16154584U JP S6178437 U JPS6178437 U JP S6178437U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- signal
- gate
- transmission circuit
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008054 signal transmission Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の一例の構成図、第２図はその
説明のための図、第３図〜第５図は他の例の説明
のための図、第６図、第７図は従来の回路の説明
のための図である。
１ａ，１ｂは入力端子、２ａ，２ｂは第１のＭ
ＯＳトランジスタ、３は出力端子、４ａ，４ｂは
第２のＭＯＳトランジスタ、５ａ，５ｂは制御端
子、６は電源端子である。
Figure 1 is a configuration diagram of an example of the present invention, Figure 2 is a diagram for explaining the invention, Figures 3 to 5 are diagrams for explaining other examples, and Figures 6 and 7 are conventional diagrams. FIG. 3 is a diagram for explaining the circuit of FIG. 1a and 1b are input terminals, 2a and 2b are the first M
In the OS transistor, 3 is an output terminal, 4a and 4b are second MOS transistors, 5a and 5b are control terminals, and 6 is a power supply terminal.
Claims (1)
グ素子のゲートに第２のＭＯＳトランジスタのソ
ースドレインを介して制御信号を供給すると共に
、上記第２のＭＯＳトランジスタのゲートに上記
制御信号の高電位レベルに等しい電圧を与えるよ
うにしたことを特徴とする信号伝送回路。 A control signal is supplied to the gate of the switching element consisting of the first MOS transistor via the source drain of the second MOS transistor, and a voltage equal to the high potential level of the control signal is applied to the gate of the second MOS transistor. 1. A signal transmission circuit characterized in that the signal transmission circuit is configured to give a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16154584U JPS6178437U (en) | 1984-10-25 | 1984-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16154584U JPS6178437U (en) | 1984-10-25 | 1984-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6178437U true JPS6178437U (en) | 1986-05-26 |
Family
ID=30719449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16154584U Pending JPS6178437U (en) | 1984-10-25 | 1984-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6178437U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006277789A (en) * | 2005-03-28 | 2006-10-12 | Sony Corp | Shift register and display apparatus |
-
1984
- 1984-10-25 JP JP16154584U patent/JPS6178437U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006277789A (en) * | 2005-03-28 | 2006-10-12 | Sony Corp | Shift register and display apparatus |
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