JPH045728U

JPH045728U -

Info

Publication number: JPH045728U
Application number: JP4591390U
Authority: JP
Priority date: 1990-04-27
Filing date: 1990-04-27
Publication date: 1992-01-20

Description

[Brief explanation of the drawing]

第１図は本考案の実施例の回路図、第２図は従
来回路の回路図を示す。ＴＲ１〜ＴＲ４……トランジスタ、１，２，６
……入力端子、３……出力端子、４……切替回路
、５……バイアス制御回路。 FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 shows a circuit diagram of a conventional circuit. TR1 to TR4...transistor, 1, 2, 6
...Input terminal, 3...Output terminal, 4...Switching circuit, 5...Bias control circuit.

Claims

[Claims for Utility Model Registration] 1. One of the two input clock signals, respectively.
first and second level conversion circuits each having a transistor that converts the level of each signal; and one of the converted output signals of the first and second level conversion circuits in response to a switching control signal applied from the outside. and a bias control circuit that responds to the switching control signal to apply a bias voltage to set a cut-off operation to the transistor of the level conversion circuit that is not selected by the switching circuit. A clock signal switching circuit characterized in that: 2. The clock signal switching circuit according to claim 1, wherein each of said first and second level conversion circuits has a configuration in which emitter followers of said transistors are connected in two stages.