JPS61124095U - - Google Patents

Info

Publication number
JPS61124095U
JPS61124095U JP885685U JP885685U JPS61124095U JP S61124095 U JPS61124095 U JP S61124095U JP 885685 U JP885685 U JP 885685U JP 885685 U JP885685 U JP 885685U JP S61124095 U JPS61124095 U JP S61124095U
Authority
JP
Japan
Prior art keywords
ttl level
gate circuit
level video
input
output terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP885685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP885685U priority Critical patent/JPS61124095U/ja
Publication of JPS61124095U publication Critical patent/JPS61124095U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案にかかる映像増幅回路の一実
施例を示す回路図、第2図は従来の映像増幅回路
を示す回路図である。 1,2…映像信号、3,4…ゲート回路、5…
可変抵抗器、6,7…抵抗器、10…トランジス
タ、11…可変抵抗器。
FIG. 1 is a circuit diagram showing an embodiment of the video amplification circuit according to this invention, and FIG. 2 is a circuit diagram showing a conventional video amplification circuit. 1, 2...Video signal, 3, 4...Gate circuit, 5...
Variable resistor, 6, 7...Resistor, 10...Transistor, 11...Variable resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1のTTLレベルの映像信号が入力される第
1のゲート回路と、第2のTTLレベルの映像信
号が入力される第2のゲート回路と、上記第1、
第2のゲート回路の出力端子のそれぞれに抵抗器
を介して接続された可変電圧源と、上記第1、第
2のゲート回路の出力端子の間に接続された可変
抵抗器とを備え、上記可変抵抗器の中点から上記
第1、第2のTTLレベルの映像信号の合成信号
を取出すようにしたことを特徴とする映像増幅回
路。
a first gate circuit to which a first TTL level video signal is input; a second gate circuit to which a second TTL level video signal is input;
a variable voltage source connected to each of the output terminals of the second gate circuit via a resistor, and a variable resistor connected between the output terminals of the first and second gate circuits; A video amplification circuit characterized in that a composite signal of the first and second TTL level video signals is extracted from the midpoint of the variable resistor.
JP885685U 1985-01-23 1985-01-23 Pending JPS61124095U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP885685U JPS61124095U (en) 1985-01-23 1985-01-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP885685U JPS61124095U (en) 1985-01-23 1985-01-23

Publications (1)

Publication Number Publication Date
JPS61124095U true JPS61124095U (en) 1986-08-05

Family

ID=30488527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP885685U Pending JPS61124095U (en) 1985-01-23 1985-01-23

Country Status (1)

Country Link
JP (1) JPS61124095U (en)

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