JPS61128820U - - Google Patents
Info
- Publication number
- JPS61128820U JPS61128820U JP1171185U JP1171185U JPS61128820U JP S61128820 U JPS61128820 U JP S61128820U JP 1171185 U JP1171185 U JP 1171185U JP 1171185 U JP1171185 U JP 1171185U JP S61128820 U JPS61128820 U JP S61128820U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- bias
- couplers
- circuits
- phase detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図はこの発明の一実施例を示すリミタアン
プの構成図、第２図は従来のリミタアンプの構成
図である。図において、１はＦＥＴ、２は整合回
路、３はバイアス回路、４はコンデンサ、５はゲ
ートバイアス端子、６はドレインバイアス端子、
７は信号入力端子、８は信号出力端子、９は結合
器、１０は位相検出器、１１は制御回路である。
なお、各図中、同一符号は同一または相当部分を
示す。
FIG. 1 is a block diagram of a limiter amplifier showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional limiter amplifier. In the figure, 1 is a FET, 2 is a matching circuit, 3 is a bias circuit, 4 is a capacitor, 5 is a gate bias terminal, 6 is a drain bias terminal,
7 is a signal input terminal, 8 is a signal output terminal, 9 is a coupler, 10 is a phase detector, and 11 is a control circuit.
In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ゲート端子及びドレイン端子にそれぞれ接続され
、上記ＦＥＴにバイアスを供給する二つのバイア
ス回路と、上記各バイアス回路にそれぞれ接続さ
れる二つの整合回路と、上記二つの整合回路にそ
れぞれ接続される二つの結合器と、上記二つの結
合器に共通に接続される一つの位相検出器と、上
記位相検出器に接続される一つの制御回路とを備
えたことを特徴とするＦＥＴリミタアンプ。 An FET whose source terminal is grounded, two bias circuits connected to the gate terminal and drain terminal of the FET and supplying bias to the FET, two matching circuits connected to each of the bias circuits, and Two couplers each connected to two matching circuits, one phase detector commonly connected to the two couplers, and one control circuit connected to the phase detector. FET limiter amplifier featuring
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171185U JPS61128820U (en) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171185U JPS61128820U (en) | 1985-01-30 | 1985-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128820U true JPS61128820U (en) | 1986-08-12 |
Family
ID=30494084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1171185U Pending JPS61128820U (en) | 1985-01-30 | 1985-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128820U (en) |
-
1985
- 1985-01-30 JP JP1171185U patent/JPS61128820U/ja active Pending
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