JPS62203530U - - Google Patents
Info
- Publication number
- JPS62203530U JPS62203530U JP9198186U JP9198186U JPS62203530U JP S62203530 U JPS62203530 U JP S62203530U JP 9198186 U JP9198186 U JP 9198186U JP 9198186 U JP9198186 U JP 9198186U JP S62203530 U JPS62203530 U JP S62203530U
- Authority
- JP
- Japan
- Prior art keywords
- charge pump
- output
- control circuit
- phase detector
- pll synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例の構成図、第２図は
従来の方法の一例の構成図である。
１……位相検波器、２，３……トランジスタ、
４……増幅器、５，６……抵抗器。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional method. 1... Phase detector, 2, 3... Transistor,
4...Amplifier, 5,6...Resistor.
Claims (1)
２つのデジタル信号を出力する位相検波器と、位
相検波器のデジタル出力信号を受けて、ロー出力
、ハイ出力又は高インピーダンスのいずれかの状
態となるチヤージポンプと、チヤージポンプの出
力を受けて低域波及び増幅を行う増幅器とによ
つて構成されるＰＬＬシンセサイザの制御回路に
おいて、分圧回路をチヤージポンプに並列に接続
して成ることを特徴とするＰＬＬシンセサイザの
制御回路。 A phase detector that detects the phase difference between two input signals and outputs at least two digital signals; and upon receiving the digital output signal of the phase detector, becomes one of low output, high output, or high impedance state. A control circuit for a PLL synthesizer comprising a charge pump and an amplifier that receives the output of the charge pump and performs low frequency and amplification, the PLL synthesizer comprising a voltage dividing circuit connected in parallel to the charge pump. control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986091981U JPH0727700Y2 (en) | 1986-06-16 | 1986-06-16 | Control circuit for PLL synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986091981U JPH0727700Y2 (en) | 1986-06-16 | 1986-06-16 | Control circuit for PLL synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62203530U true JPS62203530U (en) | 1987-12-25 |
| JPH0727700Y2 JPH0727700Y2 (en) | 1995-06-21 |
Family
ID=30953261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986091981U Expired - Lifetime JPH0727700Y2 (en) | 1986-06-16 | 1986-06-16 | Control circuit for PLL synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727700Y2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2701794C (en) | 2007-10-02 | 2017-10-31 | Theranos, Inc. | Modular point-of-care devices and uses thereof |
| CN106290159A (en) | 2011-01-21 | 2017-01-04 | 提拉诺斯公司 | Sample uses maximized system and method |
| US9268915B2 (en) | 2011-09-25 | 2016-02-23 | Theranos, Inc. | Systems and methods for diagnosis or treatment |
| US8475739B2 (en) | 2011-09-25 | 2013-07-02 | Theranos, Inc. | Systems and methods for fluid handling |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843930A (en) * | 1981-08-20 | 1983-03-14 | デイビ−・マツキ−・（ロンドン）・リミテツド | Catalytic hydrogenation |
-
1986
- 1986-06-16 JP JP1986091981U patent/JPH0727700Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843930A (en) * | 1981-08-20 | 1983-03-14 | デイビ−・マツキ−・（ロンドン）・リミテツド | Catalytic hydrogenation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727700Y2 (en) | 1995-06-21 |
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