JPH0236237U - - Google Patents
Info
- Publication number
- JPH0236237U JPH0236237U JP11610588U JP11610588U JPH0236237U JP H0236237 U JPH0236237 U JP H0236237U JP 11610588 U JP11610588 U JP 11610588U JP 11610588 U JP11610588 U JP 11610588U JP H0236237 U JPH0236237 U JP H0236237U
- Authority
- JP
- Japan
- Prior art keywords
- output level
- control loop
- loop circuit
- level
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Circuits Of Receivers In General (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
第１図はこの考案の一実施例による制御ループ
回路のブロツク図、第２図はこの考案の他の実施
例を示す制御ループ回路のブロツク図、第３図は
従来の制御ループ回路のブロツク図である。
図において、１はＲＦ入力端子、２はＲＦ増幅
器、３はＬＯ入力端子、４は周波数変換器、５は
ＩＦフイルター、６はＩＦ増幅器、７は周波数補
正器、８はＩＦ出力端子、９は可変減衰器、１０
は方向性結合器、１１はレベル検出器、１２は差
動増幅器、１３は基準電圧を示す。なお、図中、
同一符号は同一、又は相当部分示す。
Fig. 1 is a block diagram of a control loop circuit according to one embodiment of this invention, Fig. 2 is a block diagram of a control loop circuit showing another embodiment of this invention, and Fig. 3 is a block diagram of a conventional control loop circuit. It is. In the figure, 1 is an RF input terminal, 2 is an RF amplifier, 3 is an LO input terminal, 4 is a frequency converter, 5 is an IF filter, 6 is an IF amplifier, 7 is a frequency corrector, 8 is an IF output terminal, and 9 is a variable attenuator, 10
11 is a directional coupler, 11 is a level detector, 12 is a differential amplifier, and 13 is a reference voltage. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.
Claims (1)
ＩＦ信号に周波数変換する周波数変換器の出力レ
ベルを検出し、入力レベルを変化させることによ
り出力レベルを一定にしたことを特徴とする制御
ループ回路。 A control loop circuit characterized in that the output level of a frequency converter that converts a wideband RF input signal whose frequency changes rapidly into an IF signal is detected, and the output level is kept constant by changing the input level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11610588U JPH0236237U (en) | 1988-09-01 | 1988-09-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11610588U JPH0236237U (en) | 1988-09-01 | 1988-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236237U true JPH0236237U (en) | 1990-03-08 |
Family
ID=31358340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11610588U Pending JPH0236237U (en) | 1988-09-01 | 1988-09-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236237U (en) |
-
1988
- 1988-09-01 JP JP11610588U patent/JPH0236237U/ja active Pending
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