JPS63147023U - - Google Patents

Info

Publication number
JPS63147023U
JPS63147023U JP4024187U JP4024187U JPS63147023U JP S63147023 U JPS63147023 U JP S63147023U JP 4024187 U JP4024187 U JP 4024187U JP 4024187 U JP4024187 U JP 4024187U JP S63147023 U JPS63147023 U JP S63147023U
Authority
JP
Japan
Prior art keywords
signal
frequency signal
circuit
passing
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4024187U
Other languages
Japanese (ja)
Other versions
JPH0611632Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987040241U priority Critical patent/JPH0611632Y2/en
Publication of JPS63147023U publication Critical patent/JPS63147023U/ja
Application granted granted Critical
Publication of JPH0611632Y2 publication Critical patent/JPH0611632Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の一実施例を示す回路図、及
び第２図は従来の自動ラウドネス制御回路を示す
回路図である。 １２…コンデンサ、１３…分圧回路、１６…ロ
ーパスフイルタ、１７…可変減衰回路、１８…低
域ブーストアンプ、１９…加算回路。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional automatic loudness control circuit. 12... Capacitor, 13 ... Voltage divider circuit, 16 ... Low pass filter, 17... Variable attenuation circuit, 18... Low range boost amplifier, 19... Adder circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高域信号を通過させる第１信号路と、中域信号
を通過させる第２信号路と、低域信号を通過させ
る第３信号路と、出力信号レベルに応じて前記第
３信号路から得られる低域信号の減衰量を制御す
る可変減衰回路と、該可変減衰回路の出力信号を
増幅するブーストアンプとを備える自動ラウドネ
ス制御回路において、前記第１及び第２信号路か
ら得られる高域信号及び低域信号が共通に印加さ
れる第１入力端子と、前記ブーストアンプの出力
信号が印加される第２入力端子とを有する加算回
路を設け、該加算回路の出力端に低域信号がブー
ストされたオーデイオ信号を得る様にしたことを
特徴とする自動ラウドネス制御回路。 A first signal path for passing a high frequency signal, a second signal path for passing a middle frequency signal, a third signal path for passing a low frequency signal, and an output signal obtained from the third signal path depending on the output signal level. An automatic loudness control circuit comprising a variable attenuation circuit that controls the amount of attenuation of a low-frequency signal, and a boost amplifier that amplifies the output signal of the variable attenuation circuit, the high-frequency signal obtained from the first and second signal paths and An adder circuit having a first input terminal to which a low frequency signal is commonly applied and a second input terminal to which an output signal of the boost amplifier is applied is provided, and the low frequency signal is boosted to the output terminal of the adder circuit. An automatic loudness control circuit characterized in that it obtains an audio signal.
JP1987040241U 1987-03-19 1987-03-19 Automatic loudness control circuit Expired - Lifetime JPH0611632Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987040241U JPH0611632Y2 (en) 1987-03-19 1987-03-19 Automatic loudness control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987040241U JPH0611632Y2 (en) 1987-03-19 1987-03-19 Automatic loudness control circuit

Publications (2)

Publication Number Publication Date
JPS63147023U true JPS63147023U (en) 1988-09-28
JPH0611632Y2 JPH0611632Y2 (en) 1994-03-23

Family

ID=30854156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987040241U Expired - Lifetime JPH0611632Y2 (en) 1987-03-19 1987-03-19 Automatic loudness control circuit

Country Status (1)

Country Link
JP (1) JPH0611632Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244721A (en) * 2007-03-27 2008-10-09 Clarion Co Ltd Voice mixing circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166119U (en) * 1982-04-30 1983-11-05 パイオニア株式会社 Tone control circuit
JPS61158205A (en) * 1984-12-29 1986-07-17 Sony Corp Amplifier circuit of speaker

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166119U (en) * 1982-04-30 1983-11-05 パイオニア株式会社 Tone control circuit
JPS61158205A (en) * 1984-12-29 1986-07-17 Sony Corp Amplifier circuit of speaker

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244721A (en) * 2007-03-27 2008-10-09 Clarion Co Ltd Voice mixing circuit

Also Published As

Publication number Publication date
JPH0611632Y2 (en) 1994-03-23

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