JPS637812U - - Google Patents
Info
- Publication number
- JPS637812U JPS637812U JP10111986U JP10111986U JPS637812U JP S637812 U JPS637812 U JP S637812U JP 10111986 U JP10111986 U JP 10111986U JP 10111986 U JP10111986 U JP 10111986U JP S637812 U JPS637812 U JP S637812U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- pin diode
- phase shifter
- fet
- diode phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
- Amplifiers (AREA)
Description
第1図はこの考案の一実施例を示す構成図、第
2図、第3図は第1図で示した単位増幅器及びP
INダイオード移相器の内容構成図、第4図、第
5図は従来のFET増幅器を示す構成図とその位
相・振幅特性例を示す図であり、図において、1
はFET単位増幅回路、2は入力信号端子、3は
出力信号端子、4はPINダイオード移相器、5
は制御回路、6はFET、7はブロツクコンデン
サ、8はチヨークコイル、9は検出抵抗、10は
検出増幅器、11は検出端子、12,13はゲー
ト及びドレインバイアス端子、14はPINダイ
オード、15はサーキユレータ、16は制御端子
である。なお、各図中同一符号は同一または相当
部分を示す。
Fig. 1 is a block diagram showing an embodiment of this invention, and Figs. 2 and 3 show the unit amplifier and P
4 and 5 are diagrams showing the configuration of a conventional FET amplifier and examples of its phase and amplitude characteristics.
is a FET unit amplifier circuit, 2 is an input signal terminal, 3 is an output signal terminal, 4 is a PIN diode phase shifter, 5
is a control circuit, 6 is an FET, 7 is a block capacitor, 8 is a choke coil, 9 is a detection resistor, 10 is a detection amplifier, 11 is a detection terminal, 12 and 13 are gate and drain bias terminals, 14 is a PIN diode, and 15 is a circulator. , 16 are control terminals. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
された多段増幅器と、上記増幅器の入力側に直列
に接続され、かつPINダイオードを用いたPI
Nダイオード移相器と、上記増幅器の多段の中の
1つとPINダイオード移相器の双方に接続され
、かつ上記PINダイオード移相器の位相を制御
するための制御回路とを備えたことを特徴とする
FET増幅器。 A multistage amplifier configured using FETs (field effect transistors) and a PI connected in series to the input side of the above amplifier and using a PIN diode.
N diode phase shifter; and a control circuit connected to both one of the multiple stages of the amplifier and the PIN diode phase shifter, and for controlling the phase of the PIN diode phase shifter. FET amplifier.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10111986U JPS637812U (en) | 1986-07-01 | 1986-07-01 | |
US06/924,631 US4751473A (en) | 1985-11-05 | 1986-10-29 | FET amplifier circuit |
FR868615423A FR2589648B1 (en) | 1985-11-05 | 1986-11-05 | FIELD-EFFECT TRANSISTOR AMPLIFIER CIRCUIT |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10111986U JPS637812U (en) | 1986-07-01 | 1986-07-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS637812U true JPS637812U (en) | 1988-01-19 |
Family
ID=30971573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10111986U Pending JPS637812U (en) | 1985-11-05 | 1986-07-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS637812U (en) |
-
1986
- 1986-07-01 JP JP10111986U patent/JPS637812U/ja active Pending
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