JPS60119122U - power amplifier - Google Patents

power amplifier

Info

Publication number
JPS60119122U
JPS60119122U JP667284U JP667284U JPS60119122U JP S60119122 U JPS60119122 U JP S60119122U JP 667284 U JP667284 U JP 667284U JP 667284 U JP667284 U JP 667284U JP S60119122 U JPS60119122 U JP S60119122U
Authority
JP
Japan
Prior art keywords
power amplifier
input signal
fet
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP667284U
Other languages
Japanese (ja)
Inventor
粟生 和宏
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP667284U priority Critical patent/JPS60119122U/en
Publication of JPS60119122U publication Critical patent/JPS60119122U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電力増幅器を示す回路図、第2図は入力
信号レベルとFETのドレン電流IDの関係を示す特性
図、第3図は入力信号レベルと出力電力の関係を示す特
性図、第4図はFETのドレイン電力■。と出力電力の
関係を示す特性図、第5図はこの考案の一実施例による
電力増幅器を示す回路−1第6図はこの考案による入力
信号?ベルとFETのドレイン電流Ioの関係を示す特
性図、第7図はこの考案による入力信号レベルと出力電
力の関係を示す特性図である。 1・・・FET、 8・・−FET増幅器出力側整合回
路、9・・−RF出力検波回路、11・・・直流増幅器
、13・・・−送信出力制御用トランジスタ、19・・
・RF結合コンデンサ、20・・−RF検波ダイオード
、22・・・RF信号検知用トランジスタ、26・・・
FETドレイン電圧制御用ツェナーダイオード。なお、
図中同一符号は同一、または相当部分を示す。 ′補正 昭5’16.11 一図面の簡単な説明を次のように補正する。 明細書第9頁第15fi″目において、′ツーエナーダ
イす−ドヨを1ダイオードjに訂正する。
FIG. 1 is a circuit diagram showing a conventional power amplifier, FIG. 2 is a characteristic diagram showing the relationship between input signal level and FET drain current ID, and FIG. 3 is a characteristic diagram showing the relationship between input signal level and output power. Figure 4 shows the FET drain power ■. FIG. 5 is a circuit showing a power amplifier according to an embodiment of this invention. FIG. 6 is an input signal according to this invention. FIG. 7 is a characteristic diagram showing the relationship between the input signal level and the output power according to this invention. DESCRIPTION OF SYMBOLS 1... FET, 8... - FET amplifier output side matching circuit, 9... - RF output detection circuit, 11... DC amplifier, 13... - Transmission output control transistor, 19...
・RF coupling capacitor, 20... -RF detection diode, 22... RF signal detection transistor, 26...
Zener diode for FET drain voltage control. In addition,
The same reference numerals in the figures indicate the same or corresponding parts. 'Amendment 16/11/1971 The brief description of one drawing is amended as follows. In the 15th fi'' of page 9 of the specification, '2-ener-dye-doyo' is corrected to 1-diode j.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電界効果トランジスタ(FET)で構成された電力増幅
器において、その送信出力レベル、および入力信号レベ
ルに応じて上記電界効果トランジスタの動作電源電圧を
制御することにより、上記電力増幅器の出力レベルの安
定化を図っkこ−とを特徴とする電力増幅器。
In a power amplifier configured with a field effect transistor (FET), the output level of the power amplifier is stabilized by controlling the operating power supply voltage of the field effect transistor according to its transmission output level and input signal level. A power amplifier characterized by the following features.
JP667284U 1984-01-20 1984-01-20 power amplifier Pending JPS60119122U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP667284U JPS60119122U (en) 1984-01-20 1984-01-20 power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP667284U JPS60119122U (en) 1984-01-20 1984-01-20 power amplifier

Publications (1)

Publication Number Publication Date
JPS60119122U true JPS60119122U (en) 1985-08-12

Family

ID=30484329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP667284U Pending JPS60119122U (en) 1984-01-20 1984-01-20 power amplifier

Country Status (1)

Country Link
JP (1) JPS60119122U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149593A (en) * 2014-02-06 2015-08-20 株式会社東芝 amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149593A (en) * 2014-02-06 2015-08-20 株式会社東芝 amplifier

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