JPS615016U - Bias circuit for high frequency FET amplifier - Google Patents
Bias circuit for high frequency FET amplifierInfo
- Publication number
- JPS615016U JPS615016U JP8900884U JP8900884U JPS615016U JP S615016 U JPS615016 U JP S615016U JP 8900884 U JP8900884 U JP 8900884U JP 8900884 U JP8900884 U JP 8900884U JP S615016 U JPS615016 U JP S615016U
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- bias circuit
- input terminal
- voltage input
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第1図は本考案の一実施例を示す回路図、第2図〜第4
図はそれぞれ本考案の他の実施例を示す回路図、第5図
及び第6図はGaAaFETのバイアス供給方法を説明
する回路図、第7図は従来のCaAaFET増幅器用バ
イアス回路の回路図である。
1・・・ドレイン電圧入力端子,2・・・ゲート電圧入
力端子、3・・・ドレイン電極用端子、4・・・ゲート
電極用端子、5・・・高周波増幅用FET,6.1 4
・・・ツエナーダイオード、7・・・FET, f3・
・・定電圧回路、9・・・規準電圧端子、10・・・規
準電圧端子、11・・・フォトカプラ、12・・・トラ
ンジスタ、13・・・抵L15,17・・・コンデンサ
、16・・・ダイオード。[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the present invention, Figs.
The figures are circuit diagrams showing other embodiments of the present invention, Figures 5 and 6 are circuit diagrams explaining a bias supply method for a GaAaFET, and Figure 7 is a circuit diagram of a conventional bias circuit for a CaAaFET amplifier. . DESCRIPTION OF SYMBOLS 1... Drain voltage input terminal, 2... Gate voltage input terminal, 3... Terminal for drain electrode, 4... Terminal for gate electrode, 5... FET for high frequency amplification, 6.1 4
...Zener diode, 7...FET, f3・
... Constant voltage circuit, 9... Reference voltage terminal, 10... Reference voltage terminal, 11... Photocoupler, 12... Transistor, 13... Resistor L15, 17... Capacitor, 16... ··diode.
Claims (2)
てドレインが接続された高周波造幅用FETと、このF
ETのゲートに接続されたゲート電圧入力端子と、この
ゲート電圧入力端子に発光側が接続され受光側が前記ス
イッチング素子の制御部に接続されたフォトカプラとを
具備することを特徴とする高周波FET増幅用バイアス
回路。(1) A high frequency width forming FET whose drain is connected to the drain voltage input terminal via a switching element, and this FET.
A high-frequency FET amplification device characterized by comprising a gate voltage input terminal connected to the gate of the ET, and a photocoupler whose light emitting side is connected to the gate voltage input terminal and whose light receiving side is connected to the control section of the switching element. bias circuit.
介して前記ゲート電圧入力端子に接続されていることを
特徴とする実用新案登録請求の咋囲第1項記載の高周波
FET増幅器用バイアス回路。(2) The bias circuit for a high frequency FET amplifier according to paragraph 1 of the utility model registration claim, wherein the light emitting side of the photocoupler is connected to the gate voltage input terminal via a level shift element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8900884U JPS615016U (en) | 1984-06-15 | 1984-06-15 | Bias circuit for high frequency FET amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8900884U JPS615016U (en) | 1984-06-15 | 1984-06-15 | Bias circuit for high frequency FET amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS615016U true JPS615016U (en) | 1986-01-13 |
JPH0246092Y2 JPH0246092Y2 (en) | 1990-12-05 |
Family
ID=30642695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8900884U Granted JPS615016U (en) | 1984-06-15 | 1984-06-15 | Bias circuit for high frequency FET amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS615016U (en) |
-
1984
- 1984-06-15 JP JP8900884U patent/JPS615016U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0246092Y2 (en) | 1990-12-05 |
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