JPS58169711U - FET amplifier - Google Patents

FET amplifier

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Publication number
JPS58169711U
JPS58169711U JP6864982U JP6864982U JPS58169711U JP S58169711 U JPS58169711 U JP S58169711U JP 6864982 U JP6864982 U JP 6864982U JP 6864982 U JP6864982 U JP 6864982U JP S58169711 U JPS58169711 U JP S58169711U
Authority
JP
Japan
Prior art keywords
fet
high frequency
amplifier
fet amplifier
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6864982U
Other languages
Japanese (ja)
Inventor
神内 政幸
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP6864982U priority Critical patent/JPS58169711U/en
Publication of JPS58169711U publication Critical patent/JPS58169711U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の装置の構成図、第2図はこの従−来の装
置のドレインバイアスと高周波入力および高周波出力の
関係を示す説明図、第3図はこの考案の一実施例による
装置の構成図、第4図はこの考案の装置のドレインバイ
アス左高周波入力および高周波出力の関係を示す説明図
、第5図はこの考案の他の実施例を示し、aは構成図、
bは説明図である。 1・・・FET増幅器、2・・・電源回路、3・・・電
源回路、4・・・抵抗器、5・・・スイッチング素子、
6・・・信号発生器、7・・・スイッチング素子。なお
、図中同一符号は同一、又は相当部分を示す。 A ・第4図 − コ 1 ;) ’        QND Vry −Vt > ’@ −”Lp iプ
Fig. 1 is a configuration diagram of a conventional device, Fig. 2 is an explanatory diagram showing the relationship between drain bias, high frequency input, and high frequency output of this conventional device, and Fig. 3 is a diagram of a device according to an embodiment of this invention. 4 is an explanatory diagram showing the relationship between the drain bias left high frequency input and the high frequency output of the device of this invention, FIG. 5 shows another embodiment of this invention, a is a construction diagram,
b is an explanatory diagram. DESCRIPTION OF SYMBOLS 1... FET amplifier, 2... Power supply circuit, 3... Power supply circuit, 4... Resistor, 5... Switching element,
6... Signal generator, 7... Switching element. Note that the same reference numerals in the figures indicate the same or equivalent parts. A ・Figure 4 - Ko1 ;) 'QND Vry -Vt >'@-'Lp iP

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] FETを用いたF:ET増幅器において、高周波増幅す
るFETと、このFETのドレイン電流をFET入力の
高周波信号に同期させてスイッチングする素子と、この
スイッチング素子を駆動するパルスを生成する信号発生
器とを設け、FET増幅器入力の高周波信号に同期させ
てドレイン電流を流すようにしたことを特徴とするFE
T増幅器。
An F:ET amplifier using an FET includes an FET that amplifies high frequency, an element that switches the drain current of this FET in synchronization with a high frequency signal input to the FET, and a signal generator that generates a pulse to drive this switching element. An FE characterized in that a drain current is caused to flow in synchronization with a high frequency signal input to an FET amplifier.
T amplifier.
JP6864982U 1982-05-08 1982-05-08 FET amplifier Pending JPS58169711U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6864982U JPS58169711U (en) 1982-05-08 1982-05-08 FET amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6864982U JPS58169711U (en) 1982-05-08 1982-05-08 FET amplifier

Publications (1)

Publication Number Publication Date
JPS58169711U true JPS58169711U (en) 1983-11-12

Family

ID=30078412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6864982U Pending JPS58169711U (en) 1982-05-08 1982-05-08 FET amplifier

Country Status (1)

Country Link
JP (1) JPS58169711U (en)

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